[PATCH v2] mtd: rawnand: hynix: fix up bit 0 of sdr_timing_mode

[PATCH v2] mtd: rawnand: hynix: fix up bit 0 of sdr_timing_mode

[Hector Palacios]

According to the ONFI specification, bit 0 of 'SDR timing mode support'
(bytes 129-130) "shall be 1". That means the NAND supports at least
timing mode 0.

NAND chip Hynix H27U4G8F2GDA-BI (at least) is reading a 0 on this field
which makes nand_choose_best_sdr_timings() return with error and the
probe function to eventually fail.

Given that sdr_timing_modes bit 0 must be 1 by specification, force
it in case the NAND reports it is not set. This is a safe assumption
because the mode 0 is the minimum (safer) set of timings that the
NAND can work with.

Signed-off-by: Hector Palacios <hector.palacios@digi.com>
---
v2:
  Move patch to Hynix specific fixup hook.
  Use BIT(0) macro.
v1:
  Implement generic patch in nand_base.c.

 drivers/mtd/nand/raw/nand_hynix.c | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/drivers/mtd/nand/raw/nand_hynix.c b/drivers/mtd/nand/raw/nand_hynix.c
index 0d4d4bbfdece..93f97290e3ce 100644
--- a/drivers/mtd/nand/raw/nand_hynix.c
+++ b/drivers/mtd/nand/raw/nand_hynix.c
@@ -728,8 +728,22 @@ static int hynix_nand_init(struct nand_chip *chip)
 	return ret;
 }
 
+static void hynix_fixup_onfi_param_page(struct nand_chip *chip,
+					struct nand_onfi_params *p)
+{
+	/*
+	 * Certain chips might report a 0 on sdr_timing_mode field
+	 * (bytes 129-130). This has been seen on H27U4G8F2GDA-BI.
+	 * According to ONFI specification, bit 0 of this field "shall be 1".
+	 * Force this bit if unset.
+	 */
+	if (!(p->sdr_timing_modes && BIT(0)))
+		p->sdr_timing_modes |= BIT(0);
+}
+
 const struct nand_manufacturer_ops hynix_nand_manuf_ops = {
 	.detect = hynix_nand_decode_id,
 	.init = hynix_nand_init,
 	.cleanup = hynix_nand_cleanup,
+	.fixup_onfi_param_page = hynix_fixup_onfi_param_page,
 };

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Re: [PATCH v2] mtd: rawnand: hynix: fix up bit 0 of sdr_timing_mode

[Miquel Raynal]

Hi Hector,

hector.palacios@digi.com wrote on Thu, 23 Feb 2023 13:27:36 +0100:

> According to the ONFI specification, bit 0 of 'SDR timing mode support'
> (bytes 129-130) "shall be 1". That means the NAND supports at least
> timing mode 0.
> 
> NAND chip Hynix H27U4G8F2GDA-BI (at least) is reading a 0 on this field
> which makes nand_choose_best_sdr_timings() return with error and the
> probe function to eventually fail.
> 
> Given that sdr_timing_modes bit 0 must be 1 by specification, force
> it in case the NAND reports it is not set. This is a safe assumption
> because the mode 0 is the minimum (safer) set of timings that the
> NAND can work with.
> 
> Signed-off-by: Hector Palacios <hector.palacios@digi.com>
> ---
> v2:
>   Move patch to Hynix specific fixup hook.
>   Use BIT(0) macro.
> v1:
>   Implement generic patch in nand_base.c.
> 
>  drivers/mtd/nand/raw/nand_hynix.c | 14 ++++++++++++++
>  1 file changed, 14 insertions(+)
> 
> diff --git a/drivers/mtd/nand/raw/nand_hynix.c b/drivers/mtd/nand/raw/nand_hynix.c
> index 0d4d4bbfdece..93f97290e3ce 100644
> --- a/drivers/mtd/nand/raw/nand_hynix.c
> +++ b/drivers/mtd/nand/raw/nand_hynix.c
> @@ -728,8 +728,22 @@ static int hynix_nand_init(struct nand_chip *chip)
>  	return ret;
>  }
>  
> +static void hynix_fixup_onfi_param_page(struct nand_chip *chip,
> +					struct nand_onfi_params *p)
> +{
> +	/*
> +	 * Certain chips might report a 0 on sdr_timing_mode field
> +	 * (bytes 129-130). This has been seen on H27U4G8F2GDA-BI.
> +	 * According to ONFI specification, bit 0 of this field "shall be 1".
> +	 * Force this bit if unset.
> +	 */
> +	if (!(p->sdr_timing_modes && BIT(0)))

Shall be 			  &

But TBH you can certainly just set the bit blindly.

> +		p->sdr_timing_modes |= BIT(0);
> +}
> +
>  const struct nand_manufacturer_ops hynix_nand_manuf_ops = {
>  	.detect = hynix_nand_decode_id,
>  	.init = hynix_nand_init,
>  	.cleanup = hynix_nand_cleanup,
> +	.fixup_onfi_param_page = hynix_fixup_onfi_param_page,
>  };


Thanks,
Miquèl

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