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From: Miquel Raynal <miquel.raynal@bootlin.com>
To: Bruce Suen <bruce_suen@163.com>
Cc: linux-mtd@lists.infradead.org, richard@nod.at, vigneshr@ti.com
Subject: Re: [PATCH] mtd: spinand: Add support for XTX XT26xxxDxxxxx
Date: Mon, 9 Oct 2023 14:58:39 +0200	[thread overview]
Message-ID: <20231009145839.0651dd29@xps-13> (raw)
In-Reply-To: <20231007090954.4569-1-bruce_suen@163.com>

Hi Bruce,

bruce_suen@163.com wrote on Sat,  7 Oct 2023 05:09:54 -0400:

> Add Support XTX Technology XT26G01DXXXXX, XT26G11DXXXXX, XT26Q01DXXXXX,
> XT26G02DXXXXX, XT26G12DXXXXX, XT26Q02DXXXXX, XT26G04DXXXXX, and
> XT26Q04DXXXXX SPI NAND.
> 
> These are 3V/1.8V 1G/2G/4Gbit serial SLC NAND flash device with on-die
> ECC(8bit strength per 512bytes).
> 
> Datasheet Links:
> - http://www.xtxtech.com/download/?AId=458
> - http://www.xtxtech.com/download/?AId=495
> 
> Signed-off-by: Bruce Suen <bruce_suen@163.com>
> ---
>  drivers/mtd/nand/spi/xtx.c | 135 +++++++++++++++++++++++++++++++++++++
>  1 file changed, 135 insertions(+)
> 
> diff --git a/drivers/mtd/nand/spi/xtx.c b/drivers/mtd/nand/spi/xtx.c
> index 3911520f7..ddc69ef76 100644
> --- a/drivers/mtd/nand/spi/xtx.c
> +++ b/drivers/mtd/nand/spi/xtx.c
> @@ -15,6 +15,13 @@
>  #define XT26G0XA_STATUS_ECC_8_CORRECTED	(3 << 4)
>  #define XT26G0XA_STATUS_ECC_UNCOR_ERROR	(2 << 4)
>  
> +#define XT26XXXD_STATUS_ECC_MASK	    GENMASK(7, 4)
> +#define XT26XXXD_STATUS_ECC_NO_DETECTED     (0 << 4)
> +#define XT26XXXD_STATUS_ECC_1_7_CORRECTED   (1 << 4)
> +#define XT26XXXD_STATUS_ECC_8_CORRECTED     (3 << 4)
> +#define XT26XXXD_STATUS_ECC_UNCOR_ERROR     (2 << 4)
> +
>  static SPINAND_OP_VARIANTS(read_cache_variants,
>  		SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 1, NULL, 0),
>  		SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0),
> @@ -84,6 +91,54 @@ static int xt26g0xa_ecc_get_status(struct spinand_device *spinand,
>  	return status >> 2;
>  }
>  
> +
> +static int xt26xxxd_ooblayout_ecc(struct mtd_info *mtd, int section,
> +				   struct mtd_oob_region *region)
> +{
> +	if (section)
> +		return -ERANGE;
> +
> +	region->offset = mtd->oobsize / 2;
> +	region->length = mtd->oobsize / 2;

This is strange, are you sure this is always the case? Isn't the offset
related to the number of bytes used by the ECC engine strength rather
than a position in oobsize?
 
> +
> +	return 0;
> +}
> +
> +static int xt26xxxd_ooblayout_free(struct mtd_info *mtd, int section,
> +				   struct mtd_oob_region *region)
> +{
> +	if (section)
> +		return -ERANGE;
> +
> +	region->offset = 1;

Please reserve 2 bytes for the BBM.

> +	region->length = mtd->oobsize / 2 - 1;

"- 2"

> +
> +	return 0;
> +}
> +
> +static const struct mtd_ooblayout_ops xt26xxxd_ooblayout = {
> +	.ecc = xt26xxxd_ooblayout_ecc,
> +	.free = xt26xxxd_ooblayout_free,
> +};
> +
> +static int xt26xxxd_ecc_get_status(struct spinand_device *spinand,
> +					 u8 status)
> +{
> +	switch (status & STATUS_ECC_MASK) {
> +	case XT26XXXD_STATUS_ECC_NO_DETECTED:
> +		return 0;
> +	case XT26XXXD_STATUS_ECC_UNCOR_ERROR:
> +		return -EBADMSG;
> +	case XT26XXXD_STATUS_ECC_1_7_CORRECTED:
> +		return 4+((status & XT26XXXD_STATUS_ECC_MASK) >> 6);

Can you justify the calculation?

Also please run checkpatch.pl --strict.

> +	case XT26XXXD_STATUS_ECC_8_CORRECTED:
> +		return 8;
> +	default:
> +		break;
> +	}
> +
> +	return -EINVAL;
> +}
>  static const struct spinand_info xtx_spinand_table[] = {
>  	SPINAND_INFO("XT26G01A",
>  		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0xE1),
> @@ -115,6 +170,86 @@ static const struct spinand_info xtx_spinand_table[] = {
>  		     SPINAND_HAS_QE_BIT,
>  		     SPINAND_ECCINFO(&xt26g0xa_ooblayout,
>  				     xt26g0xa_ecc_get_status)),
> +	SPINAND_INFO("XT26G01D",
> +		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x31),
> +		     NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1),
> +		     NAND_ECCREQ(8, 512),
> +		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
> +					      &write_cache_variants,
> +					      &update_cache_variants),
> +		     0,
> +		     SPINAND_ECCINFO(&xt26xxxd_ooblayout,
> +				     xt26xxxd_ecc_get_status)),
> +	SPINAND_INFO("XT26G11D",
> +		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x34),
> +		     NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1),
> +		     NAND_ECCREQ(8, 512),
> +		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
> +					      &write_cache_variants,
> +					      &update_cache_variants),
> +		     SPINAND_HAS_QE_BIT,
> +		     SPINAND_ECCINFO(&xt26xxxd_ooblayout,
> +				     xt26xxxd_ecc_get_status)),
> +	SPINAND_INFO("XT26Q01D",
> +		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x51),
> +		     NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1),
> +		     NAND_ECCREQ(8, 512),
> +		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
> +					      &write_cache_variants,
> +					      &update_cache_variants),
> +		     0,
> +		     SPINAND_ECCINFO(&xt26xxxd_ooblayout,
> +				     xt26xxxd_ecc_get_status)),
> +	SPINAND_INFO("XT26G02D",
> +		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x32),
> +		     NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1),
> +		     NAND_ECCREQ(8, 512),
> +		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
> +					      &write_cache_variants,
> +					      &update_cache_variants),
> +		     0,
> +		     SPINAND_ECCINFO(&xt26xxxd_ooblayout,
> +				     xt26xxxd_ecc_get_status)),
> +	SPINAND_INFO("XT26G12D",
> +		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x35),
> +		     NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1),
> +		     NAND_ECCREQ(8, 512),
> +		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
> +					      &write_cache_variants,
> +					      &update_cache_variants),
> +		     SPINAND_HAS_QE_BIT,
> +		     SPINAND_ECCINFO(&xt26xxxd_ooblayout,
> +				     xt26xxxd_ecc_get_status)),
> +	SPINAND_INFO("XT26Q02D",
> +		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x52),
> +		     NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1),
> +		     NAND_ECCREQ(8, 512),
> +		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
> +					      &write_cache_variants,
> +					      &update_cache_variants),
> +		     0,
> +		     SPINAND_ECCINFO(&xt26xxxd_ooblayout,
> +				     xt26xxxd_ecc_get_status)),
> +	SPINAND_INFO("XT26G04D",
> +		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x33),
> +		     NAND_MEMORG(1, 4096, 256, 64, 2048, 40, 1, 1, 1),
> +		     NAND_ECCREQ(8, 512),
> +		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
> +					      &write_cache_variants,
> +					      &update_cache_variants),
> +		     0,
> +		     SPINAND_ECCINFO(&xt26xxxd_ooblayout,
> +				     xt26xxxd_ecc_get_status)),
> +	SPINAND_INFO("XT26Q04D",
> +		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x53),
> +		     NAND_MEMORG(1, 4096, 256, 64, 2048, 40, 1, 1, 1),
> +		     NAND_ECCREQ(8, 512),
> +		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
> +					      &write_cache_variants,
> +					      &update_cache_variants),
> +		     0,
> +		     SPINAND_ECCINFO(&xt26xxxd_ooblayout,
> +				     xt26xxxd_ecc_get_status)),
>  };
>  
>  static const struct spinand_manufacturer_ops xtx_spinand_manuf_ops = {


Thanks,
Miquèl

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  reply	other threads:[~2023-10-09 12:58 UTC|newest]

Thread overview: 4+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-10-07  9:09 [PATCH] mtd: spinand: Add support for XTX XT26xxxDxxxxx Bruce Suen
2023-10-09 12:58 ` Miquel Raynal [this message]
2023-10-11  3:09   ` Bruce Suen
2023-10-11  7:09     ` Miquel Raynal

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