From: Jakub Czapiga <czapiga@google.com>
Cc: Jakub Czapiga <czapiga@google.com>,
Tudor Ambarus <tudor.ambarus@linaro.org>,
Pratyush Yadav <pratyush@kernel.org>,
Michael Walle <mwalle@kernel.org>,
Miquel Raynal <miquel.raynal@bootlin.com>,
Richard Weinberger <richard@nod.at>,
Vignesh Raghavendra <vigneshr@ti.com>,
linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org
Subject: [PATCH] mtd: spi-nor: xmc: add support for XM25QH128C and XM25QH256C
Date: Mon, 17 Mar 2025 18:21:06 +0000 [thread overview]
Message-ID: <20250317182107.2060739-1-czapiga@google.com> (raw)
Both chips support SFDP (JESD216).
XM25QH128C only supports 3-bit Block-Protection with Top-Bottom
configuration bit.
XM25QH256C supports 4-bit Block-Protection with Top-Bottom configuration
bit on SR(6).
Signed-off-by: Jakub Czapiga <czapiga@google.com>
---
drivers/mtd/spi-nor/xmc.c | 12 +++++++++++-
1 file changed, 11 insertions(+), 1 deletion(-)
diff --git a/drivers/mtd/spi-nor/xmc.c b/drivers/mtd/spi-nor/xmc.c
index d5a06054b0dd..963a44c3909a 100644
--- a/drivers/mtd/spi-nor/xmc.c
+++ b/drivers/mtd/spi-nor/xmc.c
@@ -19,7 +19,17 @@ static const struct flash_info xmc_nor_parts[] = {
.name = "XM25QH128A",
.size = SZ_16M,
.no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ,
- },
+ }, {
+ .id = SNOR_ID(0x20, 0x40, 0x18),
+ .name = "XM25QH128C",
+ .size = SZ_16M,
+ .flags = SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB,
+ }, {
+ .id = SNOR_ID(0x20, 0x40, 0x19),
+ .name = "XM25QH256C",
+ .size = SZ_32M,
+ .flags = SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_4BIT_BP | SPI_NOR_TB_SR_BIT6,
+ }
};
/* XMC (Wuhan Xinxin Semiconductor Manufacturing Corp.) */
--
2.49.0.rc1.451.g8f38331e32-goog
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next reply other threads:[~2025-03-17 18:21 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-03-17 18:21 Jakub Czapiga [this message]
2025-03-18 6:27 ` [PATCH] mtd: spi-nor: xmc: add support for XM25QH128C and XM25QH256C Tudor Ambarus
2025-03-18 11:01 ` Jakub "Kuba" Czapiga
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