* [PATCH v3 37/41] mtd: spi-nor: spansion: sort flash_info database
From: Michael Walle @ 2023-09-08 10:16 UTC (permalink / raw)
To: Tudor Ambarus, Pratyush Yadav, Miquel Raynal, Richard Weinberger,
Vignesh Raghavendra
Cc: linux-kernel, linux-mtd, Michael Walle
In-Reply-To: <20230807-mtd-flash-info-db-rework-v3-0-e60548861b10@kernel.org>
The flash ID is the new primary key into our database. Sort the entry by
it. Keep the most specific ones first, because there might be ID
collisions between shorter and longer ones.
Signed-off-by: Michael Walle <mwalle@kernel.org>
---
drivers/mtd/spi-nor/spansion.c | 174 ++++++++++++++++++++---------------------
1 file changed, 87 insertions(+), 87 deletions(-)
diff --git a/drivers/mtd/spi-nor/spansion.c b/drivers/mtd/spi-nor/spansion.c
index 5953df6aff93..fd2652aa6c1e 100644
--- a/drivers/mtd/spi-nor/spansion.c
+++ b/drivers/mtd/spi-nor/spansion.c
@@ -757,28 +757,35 @@ static const struct spi_nor_fixups s25fs_s_nor_fixups = {
static const struct flash_info spansion_nor_parts[] = {
{
+ .id = SNOR_ID(0x01, 0x02, 0x12),
+ .name = "s25sl004a",
+ .size = SZ_512K,
+ }, {
+ .id = SNOR_ID(0x01, 0x02, 0x13),
+ .name = "s25sl008a",
+ .size = SZ_1M,
+ }, {
+ .id = SNOR_ID(0x01, 0x02, 0x14),
+ .name = "s25sl016a",
+ .size = SZ_2M,
+ }, {
.id = SNOR_ID(0x01, 0x02, 0x15, 0x4d, 0x00),
.name = "s25sl032p",
.size = SZ_4M,
.no_sfdp_flags = SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ,
+ }, {
+ .id = SNOR_ID(0x01, 0x02, 0x15),
+ .name = "s25sl032a",
+ .size = SZ_4M,
}, {
.id = SNOR_ID(0x01, 0x02, 0x16, 0x4d, 0x00),
.name = "s25sl064p",
.size = SZ_8M,
.no_sfdp_flags = SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ,
}, {
- .id = SNOR_ID(0x01, 0x20, 0x18, 0x4d, 0x00, 0x80),
- .name = "s25fl128s0",
- .size = SZ_16M,
- .sector_size = SZ_256K,
- .no_sfdp_flags = SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ,
- .mfr_flags = USE_CLSR,
- }, {
- .id = SNOR_ID(0x01, 0x20, 0x18, 0x4d, 0x01, 0x80),
- .name = "s25fl128s1",
- .size = SZ_16M,
- .no_sfdp_flags = SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ,
- .mfr_flags = USE_CLSR,
+ .id = SNOR_ID(0x01, 0x02, 0x16),
+ .name = "s25sl064a",
+ .size = SZ_8M,
}, {
.id = SNOR_ID(0x01, 0x02, 0x19, 0x4d, 0x00, 0x80),
.name = "s25fl256s0",
@@ -787,31 +794,16 @@ static const struct flash_info spansion_nor_parts[] = {
.no_sfdp_flags = SPI_NOR_SKIP_SFDP | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ,
.mfr_flags = USE_CLSR,
}, {
- .id = SNOR_ID(0x01, 0x02, 0x19, 0x4d, 0x01, 0x80),
- .name = "s25fl256s1",
+ .id = SNOR_ID(0x01, 0x02, 0x19, 0x4d, 0x00, 0x81),
+ .name = "s25fs256s0",
.size = SZ_32M,
- .no_sfdp_flags = SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ,
- .mfr_flags = USE_CLSR,
- }, {
- .id = SNOR_ID(0x01, 0x02, 0x20, 0x4d, 0x00, 0x80),
- .name = "s25fl512s",
- .size = SZ_64M,
.sector_size = SZ_256K,
- .flags = SPI_NOR_HAS_LOCK,
.no_sfdp_flags = SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ,
.mfr_flags = USE_CLSR,
}, {
- .id = SNOR_ID(0x01, 0x20, 0x18, 0x4d, 0x01, 0x81),
- .name = "s25fs128s1",
- .size = SZ_16M,
- .no_sfdp_flags = SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ,
- .mfr_flags = USE_CLSR,
- .fixups = &s25fs_s_nor_fixups,
- }, {
- .id = SNOR_ID(0x01, 0x02, 0x19, 0x4d, 0x00, 0x81),
- .name = "s25fs256s0",
+ .id = SNOR_ID(0x01, 0x02, 0x19, 0x4d, 0x01, 0x80),
+ .name = "s25fl256s1",
.size = SZ_32M,
- .sector_size = SZ_256K,
.no_sfdp_flags = SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ,
.mfr_flags = USE_CLSR,
}, {
@@ -820,6 +812,14 @@ static const struct flash_info spansion_nor_parts[] = {
.size = SZ_32M,
.no_sfdp_flags = SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ,
.mfr_flags = USE_CLSR,
+ }, {
+ .id = SNOR_ID(0x01, 0x02, 0x20, 0x4d, 0x00, 0x80),
+ .name = "s25fl512s",
+ .size = SZ_64M,
+ .sector_size = SZ_256K,
+ .flags = SPI_NOR_HAS_LOCK,
+ .no_sfdp_flags = SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ,
+ .mfr_flags = USE_CLSR,
}, {
.id = SNOR_ID(0x01, 0x02, 0x20, 0x4d, 0x00, 0x81),
.name = "s25fs512s",
@@ -837,6 +837,13 @@ static const struct flash_info spansion_nor_parts[] = {
.id = SNOR_ID(0x01, 0x20, 0x18, 0x03, 0x01),
.name = "s25sl12801",
.size = SZ_16M,
+ }, {
+ .id = SNOR_ID(0x01, 0x20, 0x18, 0x4d, 0x00, 0x80),
+ .name = "s25fl128s0",
+ .size = SZ_16M,
+ .sector_size = SZ_256K,
+ .no_sfdp_flags = SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ,
+ .mfr_flags = USE_CLSR,
}, {
.id = SNOR_ID(0x01, 0x20, 0x18, 0x4d, 0x00),
.name = "s25fl129p0",
@@ -845,51 +852,34 @@ static const struct flash_info spansion_nor_parts[] = {
.no_sfdp_flags = SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ,
.mfr_flags = USE_CLSR,
}, {
- .id = SNOR_ID(0x01, 0x20, 0x18, 0x4d, 0x01),
- .name = "s25fl129p1",
+ .id = SNOR_ID(0x01, 0x20, 0x18, 0x4d, 0x01, 0x80),
+ .name = "s25fl128s1",
.size = SZ_16M,
.no_sfdp_flags = SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ,
.mfr_flags = USE_CLSR,
}, {
- .id = SNOR_ID(0x01, 0x02, 0x12),
- .name = "s25sl004a",
- .size = SZ_512K,
- }, {
- .id = SNOR_ID(0x01, 0x02, 0x13),
- .name = "s25sl008a",
- .size = SZ_1M,
- }, {
- .id = SNOR_ID(0x01, 0x02, 0x14),
- .name = "s25sl016a",
- .size = SZ_2M,
- }, {
- .id = SNOR_ID(0x01, 0x02, 0x15),
- .name = "s25sl032a",
- .size = SZ_4M,
+ .id = SNOR_ID(0x01, 0x20, 0x18, 0x4d, 0x01, 0x81),
+ .name = "s25fs128s1",
+ .size = SZ_16M,
+ .no_sfdp_flags = SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ,
+ .mfr_flags = USE_CLSR,
+ .fixups = &s25fs_s_nor_fixups,
}, {
- .id = SNOR_ID(0x01, 0x02, 0x16),
- .name = "s25sl064a",
- .size = SZ_8M,
+ .id = SNOR_ID(0x01, 0x20, 0x18, 0x4d, 0x01),
+ .name = "s25fl129p1",
+ .size = SZ_16M,
+ .no_sfdp_flags = SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ,
+ .mfr_flags = USE_CLSR,
}, {
- .id = SNOR_ID(0xef, 0x40, 0x13),
- .name = "s25fl004k",
+ .id = SNOR_ID(0x01, 0x40, 0x13),
+ .name = "s25fl204k",
.size = SZ_512K,
- .no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ,
+ .no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ,
}, {
- .id = SNOR_ID(0xef, 0x40, 0x14),
- .name = "s25fl008k",
+ .id = SNOR_ID(0x01, 0x40, 0x14),
+ .name = "s25fl208k",
.size = SZ_1M,
- .no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ,
- }, {
- .id = SNOR_ID(0xef, 0x40, 0x15),
- .name = "s25fl016k",
- .size = SZ_2M,
- .no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ,
- }, {
- .id = SNOR_ID(0xef, 0x40, 0x17),
- .name = "s25fl064k",
- .size = SZ_8M,
- .no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ,
+ .no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ,
}, {
.id = SNOR_ID(0x01, 0x40, 0x15),
.name = "s25fl116k",
@@ -905,16 +895,6 @@ static const struct flash_info spansion_nor_parts[] = {
.name = "s25fl164k",
.size = SZ_8M,
.no_sfdp_flags = SECT_4K,
- }, {
- .id = SNOR_ID(0x01, 0x40, 0x13),
- .name = "s25fl204k",
- .size = SZ_512K,
- .no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ,
- }, {
- .id = SNOR_ID(0x01, 0x40, 0x14),
- .name = "s25fl208k",
- .size = SZ_1M,
- .no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ,
}, {
.id = SNOR_ID(0x01, 0x60, 0x17),
.name = "s25fl064l",
@@ -934,10 +914,11 @@ static const struct flash_info spansion_nor_parts[] = {
.no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ,
.fixup_flags = SPI_NOR_4B_OPCODES,
}, {
- .id = SNOR_ID(0x34, 0x2b, 0x19, 0x0f, 0x08, 0x90),
- .name = "s25fs256t",
- .mfr_flags = USE_CLPEF,
- .fixups = &s25fs256t_fixups
+ .id = SNOR_ID(0x04, 0x2c, 0xc2, 0x7f, 0x7f, 0x7f),
+ .name = "cy15x104q",
+ .size = SZ_512K,
+ .sector_size = SZ_512K,
+ .flags = SPI_NOR_NO_ERASE,
}, {
.id = SNOR_ID(0x34, 0x2a, 0x1a, 0x0f, 0x03, 0x90),
.name = "s25hl512t",
@@ -954,6 +935,11 @@ static const struct flash_info spansion_nor_parts[] = {
.mfr_flags = USE_CLPEF,
.flags = NO_CHIP_ERASE,
.fixups = &s25hx_t_fixups
+ }, {
+ .id = SNOR_ID(0x34, 0x2b, 0x19, 0x0f, 0x08, 0x90),
+ .name = "s25fs256t",
+ .mfr_flags = USE_CLPEF,
+ .fixups = &s25fs256t_fixups
}, {
.id = SNOR_ID(0x34, 0x2b, 0x1a, 0x0f, 0x03, 0x90),
.name = "s25hs512t",
@@ -970,12 +956,6 @@ static const struct flash_info spansion_nor_parts[] = {
.mfr_flags = USE_CLPEF,
.flags = NO_CHIP_ERASE,
.fixups = &s25hx_t_fixups
- }, {
- .id = SNOR_ID(0x04, 0x2c, 0xc2, 0x7f, 0x7f, 0x7f),
- .name = "cy15x104q",
- .size = SZ_512K,
- .sector_size = SZ_512K,
- .flags = SPI_NOR_NO_ERASE,
}, {
.id = SNOR_ID(0x34, 0x5a, 0x1a),
.name = "s28hl512t",
@@ -1001,6 +981,26 @@ static const struct flash_info spansion_nor_parts[] = {
.name = "s28hs02gt",
.mfr_flags = USE_CLPEF,
.fixups = &s28hx_t_fixups,
+ }, {
+ .id = SNOR_ID(0xef, 0x40, 0x13),
+ .name = "s25fl004k",
+ .size = SZ_512K,
+ .no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ,
+ }, {
+ .id = SNOR_ID(0xef, 0x40, 0x14),
+ .name = "s25fl008k",
+ .size = SZ_1M,
+ .no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ,
+ }, {
+ .id = SNOR_ID(0xef, 0x40, 0x15),
+ .name = "s25fl016k",
+ .size = SZ_2M,
+ .no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ,
+ }, {
+ .id = SNOR_ID(0xef, 0x40, 0x17),
+ .name = "s25fl064k",
+ .size = SZ_8M,
+ .no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ,
}
};
--
2.39.2
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^ permalink raw reply related
* [PATCH v3 41/41] mtd: spi-nor: core: get rid of the INFOx() macros
From: Michael Walle @ 2023-09-08 10:16 UTC (permalink / raw)
To: Tudor Ambarus, Pratyush Yadav, Miquel Raynal, Richard Weinberger,
Vignesh Raghavendra
Cc: linux-kernel, linux-mtd, Michael Walle
In-Reply-To: <20230807-mtd-flash-info-db-rework-v3-0-e60548861b10@kernel.org>
Now that all flash_info tables are converted to the new format, remove
the old INFOx() macros.
Signed-off-by: Michael Walle <mwalle@kernel.org>
Reviewed-by: Tudor Ambarus <tudor.ambarus@linaro.org>
---
drivers/mtd/spi-nor/core.h | 65 ----------------------------------------------
1 file changed, 65 deletions(-)
diff --git a/drivers/mtd/spi-nor/core.h b/drivers/mtd/spi-nor/core.h
index 14c1aa63bc51..93cd2fc3606d 100644
--- a/drivers/mtd/spi-nor/core.h
+++ b/drivers/mtd/spi-nor/core.h
@@ -575,71 +575,6 @@ struct flash_info {
.n_regions = (_n_regions), \
})
-#define SPI_NOR_ID_2ITEMS(_id) ((_id) >> 8) & 0xff, (_id) & 0xff
-#define SPI_NOR_ID_3ITEMS(_id) ((_id) >> 16) & 0xff, SPI_NOR_ID_2ITEMS(_id)
-
-#define SPI_NOR_ID(_jedec_id, _ext_id) \
- .id = &(const struct spi_nor_id){ \
- .bytes = (const u8[]){ SPI_NOR_ID_3ITEMS(_jedec_id), \
- SPI_NOR_ID_2ITEMS(_ext_id) }, \
- .len = !(_jedec_id) ? 0 : (3 + ((_ext_id) ? 2 : 0)), \
- }
-
-#define SPI_NOR_ID6(_jedec_id, _ext_id) \
- .id = &(const struct spi_nor_id){ \
- .bytes = (const u8[]){ SPI_NOR_ID_3ITEMS(_jedec_id), \
- SPI_NOR_ID_3ITEMS(_ext_id) }, \
- .len = 6, \
- }
-
-#define SPI_NOR_GEOMETRY(_sector_size, _n_sectors, _n_banks) \
- .size = (_sector_size) * (_n_sectors), \
- .sector_size = (_sector_size == SZ_64K) ? 0 : (_sector_size), \
- .n_banks = (_n_banks)
-
-/* Used when the "_ext_id" is two bytes at most */
-#define INFO(_jedec_id, _ext_id, _sector_size, _n_sectors) \
- SPI_NOR_ID((_jedec_id), (_ext_id)), \
- SPI_NOR_GEOMETRY((_sector_size), (_n_sectors), 0),
-
-#define INFO0(_sector_size, _n_sectors) \
- SPI_NOR_GEOMETRY((_sector_size), (_n_sectors), 0),
-
-#define INFOB(_jedec_id, _ext_id, _sector_size, _n_sectors, _n_banks) \
- SPI_NOR_ID((_jedec_id), (_ext_id)), \
- SPI_NOR_GEOMETRY((_sector_size), (_n_sectors), (_n_banks)),
-
-#define INFO6(_jedec_id, _ext_id, _sector_size, _n_sectors) \
- SPI_NOR_ID6((_jedec_id), (_ext_id)), \
- SPI_NOR_GEOMETRY((_sector_size), (_n_sectors), 0),
-
-#define CAT25_INFO(_sector_size, _n_sectors, _page_size, _addr_nbytes) \
- .size = (_sector_size) * (_n_sectors), \
- .sector_size = (_sector_size), \
- .page_size = (_page_size), \
- .addr_nbytes = (_addr_nbytes), \
- .flags = SPI_NOR_NO_ERASE | SPI_NOR_NO_FR, \
-
-#define OTP_INFO(_len, _n_regions, _base, _offset) \
- .otp = &(const struct spi_nor_otp_organization){ \
- .len = (_len), \
- .base = (_base), \
- .offset = (_offset), \
- .n_regions = (_n_regions), \
- },
-
-#define FLAGS(_flags) \
- .flags = (_flags), \
-
-#define NO_SFDP_FLAGS(_no_sfdp_flags) \
- .no_sfdp_flags = (_no_sfdp_flags), \
-
-#define FIXUP_FLAGS(_fixup_flags) \
- .fixup_flags = (_fixup_flags), \
-
-#define MFR_FLAGS(_mfr_flags) \
- .mfr_flags = (_mfr_flags), \
-
/**
* struct spi_nor_manufacturer - SPI NOR manufacturer object
* @name: manufacturer name
--
2.39.2
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^ permalink raw reply related
* [PATCH v3 36/41] mtd: spi-nor: micron-st: sort flash_info database
From: Michael Walle @ 2023-09-08 10:16 UTC (permalink / raw)
To: Tudor Ambarus, Pratyush Yadav, Miquel Raynal, Richard Weinberger,
Vignesh Raghavendra
Cc: linux-kernel, linux-mtd, Michael Walle
In-Reply-To: <20230807-mtd-flash-info-db-rework-v3-0-e60548861b10@kernel.org>
The flash ID is the new primary key into our database. Sort the entry by
it. Keep the most specific ones first, because there might be ID
collisions between shorter and longer ones.
Signed-off-by: Michael Walle <mwalle@kernel.org>
---
drivers/mtd/spi-nor/micron-st.c | 336 ++++++++++++++++++++--------------------
1 file changed, 168 insertions(+), 168 deletions(-)
diff --git a/drivers/mtd/spi-nor/micron-st.c b/drivers/mtd/spi-nor/micron-st.c
index 720fd2fbd0ad..4afcfc57c896 100644
--- a/drivers/mtd/spi-nor/micron-st.c
+++ b/drivers/mtd/spi-nor/micron-st.c
@@ -182,133 +182,35 @@ static const struct flash_info micron_nor_parts[] = {
static const struct flash_info st_nor_parts[] = {
{
- .id = SNOR_ID(0x20, 0xbb, 0x15),
- .name = "n25q016a",
- .size = SZ_2M,
- .no_sfdp_flags = SECT_4K | SPI_NOR_QUAD_READ,
- }, {
- .id = SNOR_ID(0x20, 0xba, 0x16),
- .name = "n25q032",
- .size = SZ_4M,
- .no_sfdp_flags = SPI_NOR_QUAD_READ,
- }, {
- .id = SNOR_ID(0x20, 0xbb, 0x16),
- .name = "n25q032a",
- .size = SZ_4M,
- .no_sfdp_flags = SPI_NOR_QUAD_READ,
- }, {
- .id = SNOR_ID(0x20, 0xba, 0x17),
- .name = "n25q064",
- .size = SZ_8M,
- .no_sfdp_flags = SECT_4K | SPI_NOR_QUAD_READ,
- }, {
- .id = SNOR_ID(0x20, 0xbb, 0x17),
- .name = "n25q064a",
- .size = SZ_8M,
- .no_sfdp_flags = SECT_4K | SPI_NOR_QUAD_READ,
- }, {
- .id = SNOR_ID(0x20, 0xbb, 0x18),
- .name = "n25q128a11",
- .size = SZ_16M,
- .flags = SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_4BIT_BP |
- SPI_NOR_BP3_SR_BIT6,
- .no_sfdp_flags = SECT_4K | SPI_NOR_QUAD_READ,
- .mfr_flags = USE_FSR,
- }, {
- .id = SNOR_ID(0x20, 0xba, 0x18),
- .name = "n25q128a13",
- .size = SZ_16M,
- .flags = SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_4BIT_BP |
- SPI_NOR_BP3_SR_BIT6,
- .no_sfdp_flags = SECT_4K | SPI_NOR_QUAD_READ,
- .mfr_flags = USE_FSR,
- }, {
- .id = SNOR_ID(0x20, 0xba, 0x19, 0x10, 0x44, 0x00),
- .name = "mt25ql256a",
- .size = SZ_32M,
- .no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ,
- .fixup_flags = SPI_NOR_4B_OPCODES,
- .mfr_flags = USE_FSR,
- }, {
- .id = SNOR_ID(0x20, 0xba, 0x19),
- .name = "n25q256a",
- .size = SZ_32M,
- .no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ,
- .mfr_flags = USE_FSR,
- }, {
- .id = SNOR_ID(0x20, 0xbb, 0x19, 0x10, 0x44, 0x00),
- .name = "mt25qu256a",
- .size = SZ_32M,
- .flags = SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_4BIT_BP |
- SPI_NOR_BP3_SR_BIT6,
- .no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ,
- .fixup_flags = SPI_NOR_4B_OPCODES,
- .mfr_flags = USE_FSR,
- }, {
- .id = SNOR_ID(0x20, 0xbb, 0x19),
- .name = "n25q256ax1",
- .size = SZ_32M,
- .no_sfdp_flags = SECT_4K | SPI_NOR_QUAD_READ,
- .mfr_flags = USE_FSR,
+ .name = "m25p05-nonjedec",
+ .sector_size = SZ_32K,
+ .size = SZ_64K,
}, {
- .id = SNOR_ID(0x20, 0xba, 0x20, 0x10, 0x44, 0x00),
- .name = "mt25ql512a",
- .size = SZ_64M,
- .no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ,
- .fixup_flags = SPI_NOR_4B_OPCODES,
- .mfr_flags = USE_FSR,
+ .name = "m25p10-nonjedec",
+ .sector_size = SZ_32K,
+ .size = SZ_128K,
}, {
- .id = SNOR_ID(0x20, 0xba, 0x20),
- .name = "n25q512ax3",
- .size = SZ_64M,
- .flags = SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_4BIT_BP |
- SPI_NOR_BP3_SR_BIT6,
- .no_sfdp_flags = SECT_4K | SPI_NOR_QUAD_READ,
- .mfr_flags = USE_FSR,
+ .name = "m25p20-nonjedec",
+ .size = SZ_256K,
}, {
- .id = SNOR_ID(0x20, 0xbb, 0x20, 0x10, 0x44, 0x00),
- .name = "mt25qu512a",
- .size = SZ_64M,
- .no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ,
- .fixup_flags = SPI_NOR_4B_OPCODES,
- .mfr_flags = USE_FSR,
+ .name = "m25p40-nonjedec",
+ .size = SZ_512K,
}, {
- .id = SNOR_ID(0x20, 0xbb, 0x20),
- .name = "n25q512a",
- .size = SZ_64M,
- .flags = SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_4BIT_BP |
- SPI_NOR_BP3_SR_BIT6,
- .no_sfdp_flags = SECT_4K | SPI_NOR_QUAD_READ,
- .mfr_flags = USE_FSR,
+ .name = "m25p80-nonjedec",
+ .size = SZ_1M,
}, {
- .id = SNOR_ID(0x20, 0xba, 0x21),
- .name = "n25q00",
- .size = SZ_128M,
- .flags = SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_4BIT_BP |
- SPI_NOR_BP3_SR_BIT6 | NO_CHIP_ERASE,
- .no_sfdp_flags = SECT_4K | SPI_NOR_QUAD_READ,
- .mfr_flags = USE_FSR,
+ .name = "m25p16-nonjedec",
+ .size = SZ_2M,
}, {
- .id = SNOR_ID(0x20, 0xbb, 0x21),
- .name = "n25q00a",
- .size = SZ_128M,
- .flags = NO_CHIP_ERASE,
- .no_sfdp_flags = SECT_4K | SPI_NOR_QUAD_READ,
- .mfr_flags = USE_FSR,
+ .name = "m25p32-nonjedec",
+ .size = SZ_4M,
}, {
- .id = SNOR_ID(0x20, 0xba, 0x22),
- .name = "mt25ql02g",
- .size = SZ_256M,
- .flags = NO_CHIP_ERASE,
- .no_sfdp_flags = SECT_4K | SPI_NOR_QUAD_READ,
- .mfr_flags = USE_FSR,
+ .name = "m25p64-nonjedec",
+ .size = SZ_8M,
}, {
- .id = SNOR_ID(0x20, 0xbb, 0x22),
- .name = "mt25qu02g",
- .size = SZ_256M,
- .flags = NO_CHIP_ERASE,
- .no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ,
- .mfr_flags = USE_FSR,
+ .name = "m25p128-nonjedec",
+ .sector_size = SZ_256K,
+ .size = SZ_16M,
}, {
.id = SNOR_ID(0x20, 0x20, 0x10),
.name = "m25p05",
@@ -348,36 +250,6 @@ static const struct flash_info st_nor_parts[] = {
.name = "m25p128",
.sector_size = SZ_256K,
.size = SZ_16M,
- }, {
- .name = "m25p05-nonjedec",
- .sector_size = SZ_32K,
- .size = SZ_64K,
- }, {
- .name = "m25p10-nonjedec",
- .sector_size = SZ_32K,
- .size = SZ_128K,
- }, {
- .name = "m25p20-nonjedec",
- .size = SZ_256K,
- }, {
- .name = "m25p40-nonjedec",
- .size = SZ_512K,
- }, {
- .name = "m25p80-nonjedec",
- .size = SZ_1M,
- }, {
- .name = "m25p16-nonjedec",
- .size = SZ_2M,
- }, {
- .name = "m25p32-nonjedec",
- .size = SZ_4M,
- }, {
- .name = "m25p64-nonjedec",
- .size = SZ_8M,
- }, {
- .name = "m25p128-nonjedec",
- .sector_size = SZ_256K,
- .size = SZ_16M,
}, {
.id = SNOR_ID(0x20, 0x40, 0x11),
.name = "m45pe10",
@@ -391,18 +263,14 @@ static const struct flash_info st_nor_parts[] = {
.name = "m45pe16",
.size = SZ_2M,
}, {
- .id = SNOR_ID(0x20, 0x80, 0x12),
- .name = "m25pe20",
- .size = SZ_256K,
+ .id = SNOR_ID(0x20, 0x63, 0x16),
+ .name = "m25px32-s1",
+ .size = SZ_4M,
+ .no_sfdp_flags = SECT_4K,
}, {
- .id = SNOR_ID(0x20, 0x80, 0x14),
- .name = "m25pe80",
+ .id = SNOR_ID(0x20, 0x71, 0x14),
+ .name = "m25px80",
.size = SZ_1M,
- }, {
- .id = SNOR_ID(0x20, 0x80, 0x15),
- .name = "m25pe16",
- .size = SZ_2M,
- .no_sfdp_flags = SECT_4K,
}, {
.id = SNOR_ID(0x20, 0x71, 0x15),
.name = "m25px16",
@@ -413,25 +281,157 @@ static const struct flash_info st_nor_parts[] = {
.name = "m25px32",
.size = SZ_4M,
.no_sfdp_flags = SECT_4K,
+ }, {
+ .id = SNOR_ID(0x20, 0x71, 0x17),
+ .name = "m25px64",
+ .size = SZ_8M,
}, {
.id = SNOR_ID(0x20, 0x73, 0x16),
.name = "m25px32-s0",
.size = SZ_4M,
.no_sfdp_flags = SECT_4K,
}, {
- .id = SNOR_ID(0x20, 0x63, 0x16),
- .name = "m25px32-s1",
- .size = SZ_4M,
+ .id = SNOR_ID(0x20, 0x80, 0x12),
+ .name = "m25pe20",
+ .size = SZ_256K,
+ }, {
+ .id = SNOR_ID(0x20, 0x80, 0x14),
+ .name = "m25pe80",
+ .size = SZ_1M,
+ }, {
+ .id = SNOR_ID(0x20, 0x80, 0x15),
+ .name = "m25pe16",
+ .size = SZ_2M,
.no_sfdp_flags = SECT_4K,
}, {
- .id = SNOR_ID(0x20, 0x71, 0x17),
- .name = "m25px64",
+ .id = SNOR_ID(0x20, 0xba, 0x16),
+ .name = "n25q032",
+ .size = SZ_4M,
+ .no_sfdp_flags = SPI_NOR_QUAD_READ,
+ }, {
+ .id = SNOR_ID(0x20, 0xba, 0x17),
+ .name = "n25q064",
.size = SZ_8M,
+ .no_sfdp_flags = SECT_4K | SPI_NOR_QUAD_READ,
}, {
- .id = SNOR_ID(0x20, 0x71, 0x14),
- .name = "m25px80",
- .size = SZ_1M,
- },
+ .id = SNOR_ID(0x20, 0xba, 0x18),
+ .name = "n25q128a13",
+ .size = SZ_16M,
+ .flags = SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_4BIT_BP |
+ SPI_NOR_BP3_SR_BIT6,
+ .no_sfdp_flags = SECT_4K | SPI_NOR_QUAD_READ,
+ .mfr_flags = USE_FSR,
+ }, {
+ .id = SNOR_ID(0x20, 0xba, 0x19, 0x10, 0x44, 0x00),
+ .name = "mt25ql256a",
+ .size = SZ_32M,
+ .no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ,
+ .fixup_flags = SPI_NOR_4B_OPCODES,
+ .mfr_flags = USE_FSR,
+ }, {
+ .id = SNOR_ID(0x20, 0xba, 0x19),
+ .name = "n25q256a",
+ .size = SZ_32M,
+ .no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ,
+ .mfr_flags = USE_FSR,
+ }, {
+ .id = SNOR_ID(0x20, 0xba, 0x20, 0x10, 0x44, 0x00),
+ .name = "mt25ql512a",
+ .size = SZ_64M,
+ .no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ,
+ .fixup_flags = SPI_NOR_4B_OPCODES,
+ .mfr_flags = USE_FSR,
+ }, {
+ .id = SNOR_ID(0x20, 0xba, 0x20),
+ .name = "n25q512ax3",
+ .size = SZ_64M,
+ .flags = SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_4BIT_BP |
+ SPI_NOR_BP3_SR_BIT6,
+ .no_sfdp_flags = SECT_4K | SPI_NOR_QUAD_READ,
+ .mfr_flags = USE_FSR,
+ }, {
+ .id = SNOR_ID(0x20, 0xba, 0x21),
+ .name = "n25q00",
+ .size = SZ_128M,
+ .flags = SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_4BIT_BP |
+ SPI_NOR_BP3_SR_BIT6 | NO_CHIP_ERASE,
+ .no_sfdp_flags = SECT_4K | SPI_NOR_QUAD_READ,
+ .mfr_flags = USE_FSR,
+ }, {
+ .id = SNOR_ID(0x20, 0xba, 0x22),
+ .name = "mt25ql02g",
+ .size = SZ_256M,
+ .flags = NO_CHIP_ERASE,
+ .no_sfdp_flags = SECT_4K | SPI_NOR_QUAD_READ,
+ .mfr_flags = USE_FSR,
+ }, {
+ .id = SNOR_ID(0x20, 0xbb, 0x15),
+ .name = "n25q016a",
+ .size = SZ_2M,
+ .no_sfdp_flags = SECT_4K | SPI_NOR_QUAD_READ,
+ }, {
+ .id = SNOR_ID(0x20, 0xbb, 0x16),
+ .name = "n25q032a",
+ .size = SZ_4M,
+ .no_sfdp_flags = SPI_NOR_QUAD_READ,
+ }, {
+ .id = SNOR_ID(0x20, 0xbb, 0x17),
+ .name = "n25q064a",
+ .size = SZ_8M,
+ .no_sfdp_flags = SECT_4K | SPI_NOR_QUAD_READ,
+ }, {
+ .id = SNOR_ID(0x20, 0xbb, 0x18),
+ .name = "n25q128a11",
+ .size = SZ_16M,
+ .flags = SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_4BIT_BP |
+ SPI_NOR_BP3_SR_BIT6,
+ .no_sfdp_flags = SECT_4K | SPI_NOR_QUAD_READ,
+ .mfr_flags = USE_FSR,
+ }, {
+ .id = SNOR_ID(0x20, 0xbb, 0x19, 0x10, 0x44, 0x00),
+ .name = "mt25qu256a",
+ .size = SZ_32M,
+ .flags = SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_4BIT_BP |
+ SPI_NOR_BP3_SR_BIT6,
+ .no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ,
+ .fixup_flags = SPI_NOR_4B_OPCODES,
+ .mfr_flags = USE_FSR,
+ }, {
+ .id = SNOR_ID(0x20, 0xbb, 0x19),
+ .name = "n25q256ax1",
+ .size = SZ_32M,
+ .no_sfdp_flags = SECT_4K | SPI_NOR_QUAD_READ,
+ .mfr_flags = USE_FSR,
+ }, {
+ .id = SNOR_ID(0x20, 0xbb, 0x20, 0x10, 0x44, 0x00),
+ .name = "mt25qu512a",
+ .size = SZ_64M,
+ .no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ,
+ .fixup_flags = SPI_NOR_4B_OPCODES,
+ .mfr_flags = USE_FSR,
+ }, {
+ .id = SNOR_ID(0x20, 0xbb, 0x20),
+ .name = "n25q512a",
+ .size = SZ_64M,
+ .flags = SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_4BIT_BP |
+ SPI_NOR_BP3_SR_BIT6,
+ .no_sfdp_flags = SECT_4K | SPI_NOR_QUAD_READ,
+ .mfr_flags = USE_FSR,
+ }, {
+ .id = SNOR_ID(0x20, 0xbb, 0x21),
+ .name = "n25q00a",
+ .size = SZ_128M,
+ .flags = NO_CHIP_ERASE,
+ .no_sfdp_flags = SECT_4K | SPI_NOR_QUAD_READ,
+ .mfr_flags = USE_FSR,
+ }, {
+ .id = SNOR_ID(0x20, 0xbb, 0x22),
+ .name = "mt25qu02g",
+ .size = SZ_256M,
+ .flags = NO_CHIP_ERASE,
+ .no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ,
+ .mfr_flags = USE_FSR,
+ }
};
/**
--
2.39.2
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^ permalink raw reply related
* Re: [PATCH] mtd: nand: qcom: Fix the node for nand unmap resource
From: Pavan Kondeti @ 2023-09-08 10:22 UTC (permalink / raw)
To: Bibek Kumar Patro
Cc: mani, miquel.raynal, richard, vigneshr, linux-mtd, linux-arm-msm,
linux-kernel, kernel, quic_charante, quic_kaushalk
In-Reply-To: <20230907092854.11408-1-quic_bibekkum@quicinc.com>
On Thu, Sep 07, 2023 at 02:58:54PM +0530, Bibek Kumar Patro wrote:
> While unmapping the nand resource in case of err_core_clk
> the dev node being passed is res_start instead of nand->dma_base
It is not not dev not but addr argument.
> (where the iova returned from map operation is stored) causing
> failure in unmap operation. Hence modifying the unmap operation
> to pass the nand->base_dma instead of res_start.
>
Pls simplify this commit description. I think, it was a simple copy/paste
mistake. I would write
"Fix addr argument to dma_unmap_resource() in the error path of probe.
The addr argument should be dma address not physical address."
> Signed-off-by: Bibek Kumar Patro <quic_bibekkum@quicinc.com>
> ---
> drivers/mtd/nand/raw/qcom_nandc.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/mtd/nand/raw/qcom_nandc.c b/drivers/mtd/nand/raw/qcom_nandc.c
> index f583022755a2..e085a0f588eb 100644
> --- a/drivers/mtd/nand/raw/qcom_nandc.c
> +++ b/drivers/mtd/nand/raw/qcom_nandc.c
> @@ -3322,7 +3322,7 @@ static int qcom_nandc_probe(struct platform_device *pdev)
> err_aon_clk:
> clk_disable_unprepare(nandc->core_clk);
> err_core_clk:
> - dma_unmap_resource(dev, res->start, resource_size(res),
> + dma_unmap_resource(dev, nandc->base_dma, resource_size(res),
> DMA_BIDIRECTIONAL, 0);
> dev_err(&pdev->dev, "DEBUG: probe failed for nandc module\n");
> return ret;
Since you are fixing a bug introduced by a previous commit, you should
add Fixes tag like below. Refer to Documentation [1].
Fixes: 7330fc505af4 ("mtd: rawnand: qcom: stop using phys_to_dma()")
[1] https://docs.kernel.org/process/submitting-patches.html#using-reported-by-tested-by-reviewed-by-suggested-by-and-fixes
Thanks,
Pavan
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^ permalink raw reply
* [PATCH v3 22/41] mtd: spi-nor: intel: convert flash_info to new format
From: Michael Walle @ 2023-09-08 10:16 UTC (permalink / raw)
To: Tudor Ambarus, Pratyush Yadav, Miquel Raynal, Richard Weinberger,
Vignesh Raghavendra
Cc: linux-kernel, linux-mtd, Michael Walle
In-Reply-To: <20230807-mtd-flash-info-db-rework-v3-0-e60548861b10@kernel.org>
The INFOx() macros are going away. Convert the flash_info database to
the new format.
Signed-off-by: Michael Walle <mwalle@kernel.org>
---
drivers/mtd/spi-nor/intel.c | 22 ++++++++++++++++------
1 file changed, 16 insertions(+), 6 deletions(-)
diff --git a/drivers/mtd/spi-nor/intel.c b/drivers/mtd/spi-nor/intel.c
index aba62759a02e..f647359fee7a 100644
--- a/drivers/mtd/spi-nor/intel.c
+++ b/drivers/mtd/spi-nor/intel.c
@@ -9,12 +9,22 @@
#include "core.h"
static const struct flash_info intel_nor_parts[] = {
- { "160s33b", INFO(0x898911, 0, 64 * 1024, 32)
- FLAGS(SPI_NOR_HAS_LOCK | SPI_NOR_SWP_IS_VOLATILE) },
- { "320s33b", INFO(0x898912, 0, 64 * 1024, 64)
- FLAGS(SPI_NOR_HAS_LOCK | SPI_NOR_SWP_IS_VOLATILE) },
- { "640s33b", INFO(0x898913, 0, 64 * 1024, 128)
- FLAGS(SPI_NOR_HAS_LOCK | SPI_NOR_SWP_IS_VOLATILE) },
+ {
+ .id = SNOR_ID(0x89, 0x89, 0x11),
+ .name = "160s33b",
+ .size = SZ_2M,
+ .flags = SPI_NOR_HAS_LOCK | SPI_NOR_SWP_IS_VOLATILE,
+ }, {
+ .id = SNOR_ID(0x89, 0x89, 0x12),
+ .name = "320s33b",
+ .size = SZ_4M,
+ .flags = SPI_NOR_HAS_LOCK | SPI_NOR_SWP_IS_VOLATILE,
+ }, {
+ .id = SNOR_ID(0x89, 0x89, 0x13),
+ .name = "640s33b",
+ .size = SZ_8M,
+ .flags = SPI_NOR_HAS_LOCK | SPI_NOR_SWP_IS_VOLATILE,
+ }
};
const struct spi_nor_manufacturer spi_nor_intel = {
--
2.39.2
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* [PATCH v3 30/41] mtd: spi-nor: xmc: convert flash_info to new format
From: Michael Walle @ 2023-09-08 10:16 UTC (permalink / raw)
To: Tudor Ambarus, Pratyush Yadav, Miquel Raynal, Richard Weinberger,
Vignesh Raghavendra
Cc: linux-kernel, linux-mtd, Michael Walle
In-Reply-To: <20230807-mtd-flash-info-db-rework-v3-0-e60548861b10@kernel.org>
The INFOx() macros are going away. Convert the flash_info database to
the new format.
Signed-off-by: Michael Walle <mwalle@kernel.org>
---
drivers/mtd/spi-nor/xmc.c | 17 +++++++++++------
1 file changed, 11 insertions(+), 6 deletions(-)
diff --git a/drivers/mtd/spi-nor/xmc.c b/drivers/mtd/spi-nor/xmc.c
index 48062ccb22fa..d5a06054b0dd 100644
--- a/drivers/mtd/spi-nor/xmc.c
+++ b/drivers/mtd/spi-nor/xmc.c
@@ -9,12 +9,17 @@
#include "core.h"
static const struct flash_info xmc_nor_parts[] = {
- { "XM25QH64A", INFO(0x207017, 0, 64 * 1024, 128)
- NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ |
- SPI_NOR_QUAD_READ) },
- { "XM25QH128A", INFO(0x207018, 0, 64 * 1024, 256)
- NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ |
- SPI_NOR_QUAD_READ) },
+ {
+ .id = SNOR_ID(0x20, 0x70, 0x17),
+ .name = "XM25QH64A",
+ .size = SZ_8M,
+ .no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ,
+ }, {
+ .id = SNOR_ID(0x20, 0x70, 0x18),
+ .name = "XM25QH128A",
+ .size = SZ_16M,
+ .no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ,
+ },
};
/* XMC (Wuhan Xinxin Semiconductor Manufacturing Corp.) */
--
2.39.2
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* [PATCH v3 21/41] mtd: spi-nor: gigadevice: convert flash_info to new format
From: Michael Walle @ 2023-09-08 10:16 UTC (permalink / raw)
To: Tudor Ambarus, Pratyush Yadav, Miquel Raynal, Richard Weinberger,
Vignesh Raghavendra
Cc: linux-kernel, linux-mtd, Michael Walle
In-Reply-To: <20230807-mtd-flash-info-db-rework-v3-0-e60548861b10@kernel.org>
The INFOx() macros are going away. Convert the flash_info database to
the new format.
Signed-off-by: Michael Walle <mwalle@kernel.org>
---
drivers/mtd/spi-nor/gigadevice.c | 81 ++++++++++++++++++++++++----------------
1 file changed, 49 insertions(+), 32 deletions(-)
diff --git a/drivers/mtd/spi-nor/gigadevice.c b/drivers/mtd/spi-nor/gigadevice.c
index 7cf142c75529..0d22cd99715b 100644
--- a/drivers/mtd/spi-nor/gigadevice.c
+++ b/drivers/mtd/spi-nor/gigadevice.c
@@ -34,38 +34,55 @@ static const struct spi_nor_fixups gd25q256_fixups = {
};
static const struct flash_info gigadevice_nor_parts[] = {
- { "gd25q16", INFO(0xc84015, 0, 64 * 1024, 32)
- FLAGS(SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
- NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ |
- SPI_NOR_QUAD_READ) },
- { "gd25q32", INFO(0xc84016, 0, 64 * 1024, 64)
- FLAGS(SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
- NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ |
- SPI_NOR_QUAD_READ) },
- { "gd25lq32", INFO(0xc86016, 0, 64 * 1024, 64)
- FLAGS(SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
- NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ |
- SPI_NOR_QUAD_READ) },
- { "gd25q64", INFO(0xc84017, 0, 64 * 1024, 128)
- FLAGS(SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
- NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ |
- SPI_NOR_QUAD_READ) },
- { "gd25lq64c", INFO(0xc86017, 0, 64 * 1024, 128)
- FLAGS(SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
- NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ |
- SPI_NOR_QUAD_READ) },
- { "gd25lq128d", INFO(0xc86018, 0, 64 * 1024, 256)
- FLAGS(SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
- NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ |
- SPI_NOR_QUAD_READ) },
- { "gd25q128", INFO(0xc84018, 0, 64 * 1024, 256)
- FLAGS(SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
- NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ |
- SPI_NOR_QUAD_READ) },
- { "gd25q256", INFO(0xc84019, 0, 64 * 1024, 0)
- FLAGS(SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_TB_SR_BIT6)
- FIXUP_FLAGS(SPI_NOR_4B_OPCODES)
- .fixups = &gd25q256_fixups },
+ {
+ .id = SNOR_ID(0xc8, 0x40, 0x15),
+ .name = "gd25q16",
+ .size = SZ_2M,
+ .flags = SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB,
+ .no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ,
+ }, {
+ .id = SNOR_ID(0xc8, 0x40, 0x16),
+ .name = "gd25q32",
+ .size = SZ_4M,
+ .flags = SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB,
+ .no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ,
+ }, {
+ .id = SNOR_ID(0xc8, 0x60, 0x16),
+ .name = "gd25lq32",
+ .size = SZ_4M,
+ .flags = SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB,
+ .no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ,
+ }, {
+ .id = SNOR_ID(0xc8, 0x40, 0x17),
+ .name = "gd25q64",
+ .size = SZ_8M,
+ .flags = SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB,
+ .no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ,
+ }, {
+ .id = SNOR_ID(0xc8, 0x60, 0x17),
+ .name = "gd25lq64c",
+ .size = SZ_8M,
+ .flags = SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB,
+ .no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ,
+ }, {
+ .id = SNOR_ID(0xc8, 0x60, 0x18),
+ .name = "gd25lq128d",
+ .size = SZ_16M,
+ .flags = SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB,
+ .no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ,
+ }, {
+ .id = SNOR_ID(0xc8, 0x40, 0x18),
+ .name = "gd25q128",
+ .size = SZ_16M,
+ .flags = SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB,
+ .no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ,
+ }, {
+ .id = SNOR_ID(0xc8, 0x40, 0x19),
+ .name = "gd25q256",
+ .flags = SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_TB_SR_BIT6,
+ .fixups = &gd25q256_fixups,
+ .fixup_flags = SPI_NOR_4B_OPCODES,
+ },
};
const struct spi_nor_manufacturer spi_nor_gigadevice = {
--
2.39.2
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^ permalink raw reply related
* [PATCH v3 25/41] mtd: spi-nor: micron-st: convert flash_info to new format
From: Michael Walle @ 2023-09-08 10:16 UTC (permalink / raw)
To: Tudor Ambarus, Pratyush Yadav, Miquel Raynal, Richard Weinberger,
Vignesh Raghavendra
Cc: linux-kernel, linux-mtd, Michael Walle
In-Reply-To: <20230807-mtd-flash-info-db-rework-v3-0-e60548861b10@kernel.org>
The INFOx() macros are going away. Convert the flash_info database to
the new format.
Signed-off-by: Michael Walle <mwalle@kernel.org>
---
drivers/mtd/spi-nor/micron-st.c | 405 ++++++++++++++++++++++++++--------------
1 file changed, 268 insertions(+), 137 deletions(-)
diff --git a/drivers/mtd/spi-nor/micron-st.c b/drivers/mtd/spi-nor/micron-st.c
index 229c951efcce..720fd2fbd0ad 100644
--- a/drivers/mtd/spi-nor/micron-st.c
+++ b/drivers/mtd/spi-nor/micron-st.c
@@ -159,148 +159,279 @@ static const struct spi_nor_fixups mt35xu512aba_fixups = {
};
static const struct flash_info micron_nor_parts[] = {
- { "mt35xu512aba", INFO(0x2c5b1a, 0, 128 * 1024, 512)
- NO_SFDP_FLAGS(SECT_4K | SPI_NOR_OCTAL_READ |
- SPI_NOR_OCTAL_DTR_READ | SPI_NOR_OCTAL_DTR_PP)
- FIXUP_FLAGS(SPI_NOR_4B_OPCODES | SPI_NOR_IO_MODE_EN_VOLATILE)
- MFR_FLAGS(USE_FSR)
- .fixups = &mt35xu512aba_fixups
- },
- { "mt35xu02g", INFO(0x2c5b1c, 0, 128 * 1024, 2048)
- NO_SFDP_FLAGS(SECT_4K | SPI_NOR_OCTAL_READ)
- FIXUP_FLAGS(SPI_NOR_4B_OPCODES)
- MFR_FLAGS(USE_FSR)
+ {
+ .id = SNOR_ID(0x2c, 0x5b, 0x1a),
+ .name = "mt35xu512aba",
+ .sector_size = SZ_128K,
+ .size = SZ_64M,
+ .no_sfdp_flags = SECT_4K | SPI_NOR_OCTAL_READ |
+ SPI_NOR_OCTAL_DTR_READ | SPI_NOR_OCTAL_DTR_PP,
+ .mfr_flags = USE_FSR,
+ .fixup_flags = SPI_NOR_4B_OPCODES | SPI_NOR_IO_MODE_EN_VOLATILE,
+ .fixups = &mt35xu512aba_fixups,
+ }, {
+ .id = SNOR_ID(0x2c, 0x5b, 0x1c),
+ .name = "mt35xu02g",
+ .sector_size = SZ_128K,
+ .size = SZ_256M,
+ .no_sfdp_flags = SECT_4K | SPI_NOR_OCTAL_READ,
+ .mfr_flags = USE_FSR,
+ .fixup_flags = SPI_NOR_4B_OPCODES,
},
};
static const struct flash_info st_nor_parts[] = {
- { "n25q016a", INFO(0x20bb15, 0, 64 * 1024, 32)
- NO_SFDP_FLAGS(SECT_4K | SPI_NOR_QUAD_READ) },
- { "n25q032", INFO(0x20ba16, 0, 64 * 1024, 64)
- NO_SFDP_FLAGS(SPI_NOR_QUAD_READ) },
- { "n25q032a", INFO(0x20bb16, 0, 64 * 1024, 64)
- NO_SFDP_FLAGS(SPI_NOR_QUAD_READ) },
- { "n25q064", INFO(0x20ba17, 0, 64 * 1024, 128)
- NO_SFDP_FLAGS(SECT_4K | SPI_NOR_QUAD_READ) },
- { "n25q064a", INFO(0x20bb17, 0, 64 * 1024, 128)
- NO_SFDP_FLAGS(SECT_4K | SPI_NOR_QUAD_READ) },
- { "n25q128a11", INFO(0x20bb18, 0, 64 * 1024, 256)
- FLAGS(SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_4BIT_BP |
- SPI_NOR_BP3_SR_BIT6)
- NO_SFDP_FLAGS(SECT_4K | SPI_NOR_QUAD_READ)
- MFR_FLAGS(USE_FSR)
- },
- { "n25q128a13", INFO(0x20ba18, 0, 64 * 1024, 256)
- FLAGS(SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_4BIT_BP |
- SPI_NOR_BP3_SR_BIT6)
- NO_SFDP_FLAGS(SECT_4K | SPI_NOR_QUAD_READ)
- MFR_FLAGS(USE_FSR)
- },
- { "mt25ql256a", INFO6(0x20ba19, 0x104400, 64 * 1024, 512)
- NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ)
- FIXUP_FLAGS(SPI_NOR_4B_OPCODES)
- MFR_FLAGS(USE_FSR)
- },
- { "n25q256a", INFO(0x20ba19, 0, 64 * 1024, 512)
- NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ |
- SPI_NOR_QUAD_READ)
- MFR_FLAGS(USE_FSR)
- },
- { "mt25qu256a", INFO6(0x20bb19, 0x104400, 64 * 1024, 512)
- FLAGS(SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_4BIT_BP |
- SPI_NOR_BP3_SR_BIT6)
- NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ)
- FIXUP_FLAGS(SPI_NOR_4B_OPCODES)
- MFR_FLAGS(USE_FSR)
- },
- { "n25q256ax1", INFO(0x20bb19, 0, 64 * 1024, 512)
- NO_SFDP_FLAGS(SECT_4K | SPI_NOR_QUAD_READ)
- MFR_FLAGS(USE_FSR)
- },
- { "mt25ql512a", INFO6(0x20ba20, 0x104400, 64 * 1024, 1024)
- NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ)
- FIXUP_FLAGS(SPI_NOR_4B_OPCODES)
- MFR_FLAGS(USE_FSR)
- },
- { "n25q512ax3", INFO(0x20ba20, 0, 64 * 1024, 1024)
- FLAGS(SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_4BIT_BP |
- SPI_NOR_BP3_SR_BIT6)
- NO_SFDP_FLAGS(SECT_4K | SPI_NOR_QUAD_READ)
- MFR_FLAGS(USE_FSR)
+ {
+ .id = SNOR_ID(0x20, 0xbb, 0x15),
+ .name = "n25q016a",
+ .size = SZ_2M,
+ .no_sfdp_flags = SECT_4K | SPI_NOR_QUAD_READ,
+ }, {
+ .id = SNOR_ID(0x20, 0xba, 0x16),
+ .name = "n25q032",
+ .size = SZ_4M,
+ .no_sfdp_flags = SPI_NOR_QUAD_READ,
+ }, {
+ .id = SNOR_ID(0x20, 0xbb, 0x16),
+ .name = "n25q032a",
+ .size = SZ_4M,
+ .no_sfdp_flags = SPI_NOR_QUAD_READ,
+ }, {
+ .id = SNOR_ID(0x20, 0xba, 0x17),
+ .name = "n25q064",
+ .size = SZ_8M,
+ .no_sfdp_flags = SECT_4K | SPI_NOR_QUAD_READ,
+ }, {
+ .id = SNOR_ID(0x20, 0xbb, 0x17),
+ .name = "n25q064a",
+ .size = SZ_8M,
+ .no_sfdp_flags = SECT_4K | SPI_NOR_QUAD_READ,
+ }, {
+ .id = SNOR_ID(0x20, 0xbb, 0x18),
+ .name = "n25q128a11",
+ .size = SZ_16M,
+ .flags = SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_4BIT_BP |
+ SPI_NOR_BP3_SR_BIT6,
+ .no_sfdp_flags = SECT_4K | SPI_NOR_QUAD_READ,
+ .mfr_flags = USE_FSR,
+ }, {
+ .id = SNOR_ID(0x20, 0xba, 0x18),
+ .name = "n25q128a13",
+ .size = SZ_16M,
+ .flags = SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_4BIT_BP |
+ SPI_NOR_BP3_SR_BIT6,
+ .no_sfdp_flags = SECT_4K | SPI_NOR_QUAD_READ,
+ .mfr_flags = USE_FSR,
+ }, {
+ .id = SNOR_ID(0x20, 0xba, 0x19, 0x10, 0x44, 0x00),
+ .name = "mt25ql256a",
+ .size = SZ_32M,
+ .no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ,
+ .fixup_flags = SPI_NOR_4B_OPCODES,
+ .mfr_flags = USE_FSR,
+ }, {
+ .id = SNOR_ID(0x20, 0xba, 0x19),
+ .name = "n25q256a",
+ .size = SZ_32M,
+ .no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ,
+ .mfr_flags = USE_FSR,
+ }, {
+ .id = SNOR_ID(0x20, 0xbb, 0x19, 0x10, 0x44, 0x00),
+ .name = "mt25qu256a",
+ .size = SZ_32M,
+ .flags = SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_4BIT_BP |
+ SPI_NOR_BP3_SR_BIT6,
+ .no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ,
+ .fixup_flags = SPI_NOR_4B_OPCODES,
+ .mfr_flags = USE_FSR,
+ }, {
+ .id = SNOR_ID(0x20, 0xbb, 0x19),
+ .name = "n25q256ax1",
+ .size = SZ_32M,
+ .no_sfdp_flags = SECT_4K | SPI_NOR_QUAD_READ,
+ .mfr_flags = USE_FSR,
+ }, {
+ .id = SNOR_ID(0x20, 0xba, 0x20, 0x10, 0x44, 0x00),
+ .name = "mt25ql512a",
+ .size = SZ_64M,
+ .no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ,
+ .fixup_flags = SPI_NOR_4B_OPCODES,
+ .mfr_flags = USE_FSR,
+ }, {
+ .id = SNOR_ID(0x20, 0xba, 0x20),
+ .name = "n25q512ax3",
+ .size = SZ_64M,
+ .flags = SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_4BIT_BP |
+ SPI_NOR_BP3_SR_BIT6,
+ .no_sfdp_flags = SECT_4K | SPI_NOR_QUAD_READ,
+ .mfr_flags = USE_FSR,
+ }, {
+ .id = SNOR_ID(0x20, 0xbb, 0x20, 0x10, 0x44, 0x00),
+ .name = "mt25qu512a",
+ .size = SZ_64M,
+ .no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ,
+ .fixup_flags = SPI_NOR_4B_OPCODES,
+ .mfr_flags = USE_FSR,
+ }, {
+ .id = SNOR_ID(0x20, 0xbb, 0x20),
+ .name = "n25q512a",
+ .size = SZ_64M,
+ .flags = SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_4BIT_BP |
+ SPI_NOR_BP3_SR_BIT6,
+ .no_sfdp_flags = SECT_4K | SPI_NOR_QUAD_READ,
+ .mfr_flags = USE_FSR,
+ }, {
+ .id = SNOR_ID(0x20, 0xba, 0x21),
+ .name = "n25q00",
+ .size = SZ_128M,
+ .flags = SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_4BIT_BP |
+ SPI_NOR_BP3_SR_BIT6 | NO_CHIP_ERASE,
+ .no_sfdp_flags = SECT_4K | SPI_NOR_QUAD_READ,
+ .mfr_flags = USE_FSR,
+ }, {
+ .id = SNOR_ID(0x20, 0xbb, 0x21),
+ .name = "n25q00a",
+ .size = SZ_128M,
+ .flags = NO_CHIP_ERASE,
+ .no_sfdp_flags = SECT_4K | SPI_NOR_QUAD_READ,
+ .mfr_flags = USE_FSR,
+ }, {
+ .id = SNOR_ID(0x20, 0xba, 0x22),
+ .name = "mt25ql02g",
+ .size = SZ_256M,
+ .flags = NO_CHIP_ERASE,
+ .no_sfdp_flags = SECT_4K | SPI_NOR_QUAD_READ,
+ .mfr_flags = USE_FSR,
+ }, {
+ .id = SNOR_ID(0x20, 0xbb, 0x22),
+ .name = "mt25qu02g",
+ .size = SZ_256M,
+ .flags = NO_CHIP_ERASE,
+ .no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ,
+ .mfr_flags = USE_FSR,
+ }, {
+ .id = SNOR_ID(0x20, 0x20, 0x10),
+ .name = "m25p05",
+ .sector_size = SZ_32K,
+ .size = SZ_64K,
+ }, {
+ .id = SNOR_ID(0x20, 0x20, 0x11),
+ .name = "m25p10",
+ .sector_size = SZ_32K,
+ .size = SZ_128K,
+ }, {
+ .id = SNOR_ID(0x20, 0x20, 0x12),
+ .name = "m25p20",
+ .size = SZ_256K,
+ }, {
+ .id = SNOR_ID(0x20, 0x20, 0x13),
+ .name = "m25p40",
+ .size = SZ_512K,
+ }, {
+ .id = SNOR_ID(0x20, 0x20, 0x14),
+ .name = "m25p80",
+ .size = SZ_1M,
+ }, {
+ .id = SNOR_ID(0x20, 0x20, 0x15),
+ .name = "m25p16",
+ .size = SZ_2M,
+ }, {
+ .id = SNOR_ID(0x20, 0x20, 0x16),
+ .name = "m25p32",
+ .size = SZ_4M,
+ }, {
+ .id = SNOR_ID(0x20, 0x20, 0x17),
+ .name = "m25p64",
+ .size = SZ_8M,
+ }, {
+ .id = SNOR_ID(0x20, 0x20, 0x18),
+ .name = "m25p128",
+ .sector_size = SZ_256K,
+ .size = SZ_16M,
+ }, {
+ .name = "m25p05-nonjedec",
+ .sector_size = SZ_32K,
+ .size = SZ_64K,
+ }, {
+ .name = "m25p10-nonjedec",
+ .sector_size = SZ_32K,
+ .size = SZ_128K,
+ }, {
+ .name = "m25p20-nonjedec",
+ .size = SZ_256K,
+ }, {
+ .name = "m25p40-nonjedec",
+ .size = SZ_512K,
+ }, {
+ .name = "m25p80-nonjedec",
+ .size = SZ_1M,
+ }, {
+ .name = "m25p16-nonjedec",
+ .size = SZ_2M,
+ }, {
+ .name = "m25p32-nonjedec",
+ .size = SZ_4M,
+ }, {
+ .name = "m25p64-nonjedec",
+ .size = SZ_8M,
+ }, {
+ .name = "m25p128-nonjedec",
+ .sector_size = SZ_256K,
+ .size = SZ_16M,
+ }, {
+ .id = SNOR_ID(0x20, 0x40, 0x11),
+ .name = "m45pe10",
+ .size = SZ_128K,
+ }, {
+ .id = SNOR_ID(0x20, 0x40, 0x14),
+ .name = "m45pe80",
+ .size = SZ_1M,
+ }, {
+ .id = SNOR_ID(0x20, 0x40, 0x15),
+ .name = "m45pe16",
+ .size = SZ_2M,
+ }, {
+ .id = SNOR_ID(0x20, 0x80, 0x12),
+ .name = "m25pe20",
+ .size = SZ_256K,
+ }, {
+ .id = SNOR_ID(0x20, 0x80, 0x14),
+ .name = "m25pe80",
+ .size = SZ_1M,
+ }, {
+ .id = SNOR_ID(0x20, 0x80, 0x15),
+ .name = "m25pe16",
+ .size = SZ_2M,
+ .no_sfdp_flags = SECT_4K,
+ }, {
+ .id = SNOR_ID(0x20, 0x71, 0x15),
+ .name = "m25px16",
+ .size = SZ_2M,
+ .no_sfdp_flags = SECT_4K,
+ }, {
+ .id = SNOR_ID(0x20, 0x71, 0x16),
+ .name = "m25px32",
+ .size = SZ_4M,
+ .no_sfdp_flags = SECT_4K,
+ }, {
+ .id = SNOR_ID(0x20, 0x73, 0x16),
+ .name = "m25px32-s0",
+ .size = SZ_4M,
+ .no_sfdp_flags = SECT_4K,
+ }, {
+ .id = SNOR_ID(0x20, 0x63, 0x16),
+ .name = "m25px32-s1",
+ .size = SZ_4M,
+ .no_sfdp_flags = SECT_4K,
+ }, {
+ .id = SNOR_ID(0x20, 0x71, 0x17),
+ .name = "m25px64",
+ .size = SZ_8M,
+ }, {
+ .id = SNOR_ID(0x20, 0x71, 0x14),
+ .name = "m25px80",
+ .size = SZ_1M,
},
- { "mt25qu512a", INFO6(0x20bb20, 0x104400, 64 * 1024, 1024)
- NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ)
- FIXUP_FLAGS(SPI_NOR_4B_OPCODES)
- MFR_FLAGS(USE_FSR)
- },
- { "n25q512a", INFO(0x20bb20, 0, 64 * 1024, 1024)
- FLAGS(SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_4BIT_BP |
- SPI_NOR_BP3_SR_BIT6)
- NO_SFDP_FLAGS(SECT_4K | SPI_NOR_QUAD_READ)
- MFR_FLAGS(USE_FSR)
- },
- { "n25q00", INFO(0x20ba21, 0, 64 * 1024, 2048)
- FLAGS(SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_4BIT_BP |
- SPI_NOR_BP3_SR_BIT6 | NO_CHIP_ERASE)
- NO_SFDP_FLAGS(SECT_4K | SPI_NOR_QUAD_READ)
- MFR_FLAGS(USE_FSR)
- },
- { "n25q00a", INFO(0x20bb21, 0, 64 * 1024, 2048)
- FLAGS(NO_CHIP_ERASE)
- NO_SFDP_FLAGS(SECT_4K | SPI_NOR_QUAD_READ)
- MFR_FLAGS(USE_FSR)
- },
- { "mt25ql02g", INFO(0x20ba22, 0, 64 * 1024, 4096)
- FLAGS(NO_CHIP_ERASE)
- NO_SFDP_FLAGS(SECT_4K | SPI_NOR_QUAD_READ)
- MFR_FLAGS(USE_FSR)
- },
- { "mt25qu02g", INFO(0x20bb22, 0, 64 * 1024, 4096)
- FLAGS(NO_CHIP_ERASE)
- NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ |
- SPI_NOR_QUAD_READ)
- MFR_FLAGS(USE_FSR)
- },
-
- { "m25p05", INFO(0x202010, 0, 32 * 1024, 2) },
- { "m25p10", INFO(0x202011, 0, 32 * 1024, 4) },
- { "m25p20", INFO(0x202012, 0, 64 * 1024, 4) },
- { "m25p40", INFO(0x202013, 0, 64 * 1024, 8) },
- { "m25p80", INFO(0x202014, 0, 64 * 1024, 16) },
- { "m25p16", INFO(0x202015, 0, 64 * 1024, 32) },
- { "m25p32", INFO(0x202016, 0, 64 * 1024, 64) },
- { "m25p64", INFO(0x202017, 0, 64 * 1024, 128) },
- { "m25p128", INFO(0x202018, 0, 256 * 1024, 64) },
-
- { "m25p05-nonjedec", INFO0( 32 * 1024, 2) },
- { "m25p10-nonjedec", INFO0( 32 * 1024, 4) },
- { "m25p20-nonjedec", INFO0( 64 * 1024, 4) },
- { "m25p40-nonjedec", INFO0( 64 * 1024, 8) },
- { "m25p80-nonjedec", INFO0( 64 * 1024, 16) },
- { "m25p16-nonjedec", INFO0( 64 * 1024, 32) },
- { "m25p32-nonjedec", INFO0( 64 * 1024, 64) },
- { "m25p64-nonjedec", INFO0( 64 * 1024, 128) },
- { "m25p128-nonjedec", INFO0(256 * 1024, 64) },
-
- { "m45pe10", INFO(0x204011, 0, 64 * 1024, 2) },
- { "m45pe80", INFO(0x204014, 0, 64 * 1024, 16) },
- { "m45pe16", INFO(0x204015, 0, 64 * 1024, 32) },
-
- { "m25pe20", INFO(0x208012, 0, 64 * 1024, 4) },
- { "m25pe80", INFO(0x208014, 0, 64 * 1024, 16) },
- { "m25pe16", INFO(0x208015, 0, 64 * 1024, 32)
- NO_SFDP_FLAGS(SECT_4K) },
-
- { "m25px16", INFO(0x207115, 0, 64 * 1024, 32)
- NO_SFDP_FLAGS(SECT_4K) },
- { "m25px32", INFO(0x207116, 0, 64 * 1024, 64)
- NO_SFDP_FLAGS(SECT_4K) },
- { "m25px32-s0", INFO(0x207316, 0, 64 * 1024, 64)
- NO_SFDP_FLAGS(SECT_4K) },
- { "m25px32-s1", INFO(0x206316, 0, 64 * 1024, 64)
- NO_SFDP_FLAGS(SECT_4K) },
- { "m25px64", INFO(0x207117, 0, 64 * 1024, 128) },
- { "m25px80", INFO(0x207114, 0, 64 * 1024, 16) },
};
/**
--
2.39.2
______________________________________________________
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^ permalink raw reply related
* [PATCH v3 31/41] mtd: spi-nor: atmel: sort flash_info database
From: Michael Walle @ 2023-09-08 10:16 UTC (permalink / raw)
To: Tudor Ambarus, Pratyush Yadav, Miquel Raynal, Richard Weinberger,
Vignesh Raghavendra
Cc: linux-kernel, linux-mtd, Michael Walle
In-Reply-To: <20230807-mtd-flash-info-db-rework-v3-0-e60548861b10@kernel.org>
The flash ID is the new primary key into our database. Sort the entry by
it. Keep the most specific ones first, because there might be ID
collisions between shorter and longer ones.
Signed-off-by: Michael Walle <mwalle@kernel.org>
Reviewed-by: Tudor Ambarus <tudor.ambarus@linaro.org>
---
drivers/mtd/spi-nor/atmel.c | 82 ++++++++++++++++++++++-----------------------
1 file changed, 41 insertions(+), 41 deletions(-)
diff --git a/drivers/mtd/spi-nor/atmel.c b/drivers/mtd/spi-nor/atmel.c
index ccc985c48ae3..18e904962d0e 100644
--- a/drivers/mtd/spi-nor/atmel.c
+++ b/drivers/mtd/spi-nor/atmel.c
@@ -164,20 +164,20 @@ static const struct spi_nor_fixups atmel_nor_global_protection_fixups = {
static const struct flash_info atmel_nor_parts[] = {
{
- .id = SNOR_ID(0x1f, 0x66, 0x01),
- .name = "at25fs010",
- .sector_size = SZ_32K,
- .size = SZ_128K,
- .flags = SPI_NOR_HAS_LOCK,
+ .id = SNOR_ID(0x1f, 0x04, 0x00),
+ .name = "at26f004",
+ .size = SZ_512K,
.no_sfdp_flags = SECT_4K,
- .fixups = &at25fs_nor_fixups
}, {
- .id = SNOR_ID(0x1f, 0x66, 0x04),
- .name = "at25fs040",
- .size = SZ_512K,
- .flags = SPI_NOR_HAS_LOCK,
+ .id = SNOR_ID(0x1f, 0x25, 0x00),
+ .name = "at45db081d",
+ .size = SZ_1M,
.no_sfdp_flags = SECT_4K,
- .fixups = &at25fs_nor_fixups
+ }, {
+ .id = SNOR_ID(0x1f, 0x42, 0x16),
+ .name = "at25sl321",
+ .size = SZ_4M,
+ .no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ,
}, {
.id = SNOR_ID(0x1f, 0x44, 0x01),
.name = "at25df041a",
@@ -186,62 +186,62 @@ static const struct flash_info atmel_nor_parts[] = {
.no_sfdp_flags = SECT_4K,
.fixups = &atmel_nor_global_protection_fixups,
}, {
- .id = SNOR_ID(0x1f, 0x47, 0x00),
- .name = "at25df321",
- .size = SZ_4M,
+ .id = SNOR_ID(0x1f, 0x45, 0x01),
+ .name = "at26df081a",
+ .size = SZ_1M,
.flags = SPI_NOR_HAS_LOCK | SPI_NOR_SWP_IS_VOLATILE,
.no_sfdp_flags = SECT_4K,
.fixups = &atmel_nor_global_protection_fixups
}, {
- .id = SNOR_ID(0x1f, 0x47, 0x01),
- .name = "at25df321a",
- .size = SZ_4M,
+ .id = SNOR_ID(0x1f, 0x46, 0x01),
+ .name = "at26df161a",
+ .size = SZ_2M,
.flags = SPI_NOR_HAS_LOCK | SPI_NOR_SWP_IS_VOLATILE,
.no_sfdp_flags = SECT_4K,
.fixups = &atmel_nor_global_protection_fixups
}, {
- .id = SNOR_ID(0x1f, 0x48, 0x00),
- .name = "at25df641",
- .size = SZ_8M,
+ .id = SNOR_ID(0x1f, 0x47, 0x00),
+ .name = "at25df321",
+ .size = SZ_4M,
.flags = SPI_NOR_HAS_LOCK | SPI_NOR_SWP_IS_VOLATILE,
.no_sfdp_flags = SECT_4K,
.fixups = &atmel_nor_global_protection_fixups
}, {
- .id = SNOR_ID(0x1f, 0x42, 0x16),
- .name = "at25sl321",
+ .id = SNOR_ID(0x1f, 0x47, 0x00),
+ .name = "at26df321",
.size = SZ_4M,
- .no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ,
- }, {
- .id = SNOR_ID(0x1f, 0x04, 0x00),
- .name = "at26f004",
- .size = SZ_512K,
- .no_sfdp_flags = SECT_4K,
- }, {
- .id = SNOR_ID(0x1f, 0x45, 0x01),
- .name = "at26df081a",
- .size = SZ_1M,
.flags = SPI_NOR_HAS_LOCK | SPI_NOR_SWP_IS_VOLATILE,
.no_sfdp_flags = SECT_4K,
.fixups = &atmel_nor_global_protection_fixups
}, {
- .id = SNOR_ID(0x1f, 0x46, 0x01),
- .name = "at26df161a",
- .size = SZ_2M,
+ .id = SNOR_ID(0x1f, 0x47, 0x01),
+ .name = "at25df321a",
+ .size = SZ_4M,
.flags = SPI_NOR_HAS_LOCK | SPI_NOR_SWP_IS_VOLATILE,
.no_sfdp_flags = SECT_4K,
.fixups = &atmel_nor_global_protection_fixups
}, {
- .id = SNOR_ID(0x1f, 0x47, 0x00),
- .name = "at26df321",
- .size = SZ_4M,
+ .id = SNOR_ID(0x1f, 0x48, 0x00),
+ .name = "at25df641",
+ .size = SZ_8M,
.flags = SPI_NOR_HAS_LOCK | SPI_NOR_SWP_IS_VOLATILE,
.no_sfdp_flags = SECT_4K,
.fixups = &atmel_nor_global_protection_fixups
}, {
- .id = SNOR_ID(0x1f, 0x25, 0x00),
- .name = "at45db081d",
- .size = SZ_1M,
+ .id = SNOR_ID(0x1f, 0x66, 0x01),
+ .name = "at25fs010",
+ .sector_size = SZ_32K,
+ .size = SZ_128K,
+ .flags = SPI_NOR_HAS_LOCK,
+ .no_sfdp_flags = SECT_4K,
+ .fixups = &at25fs_nor_fixups
+ }, {
+ .id = SNOR_ID(0x1f, 0x66, 0x04),
+ .name = "at25fs040",
+ .size = SZ_512K,
+ .flags = SPI_NOR_HAS_LOCK,
.no_sfdp_flags = SECT_4K,
+ .fixups = &at25fs_nor_fixups
},
};
--
2.39.2
______________________________________________________
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^ permalink raw reply related
* [PATCH v3 26/41] mtd: spi-nor: spansion: convert flash_info to new format
From: Michael Walle @ 2023-09-08 10:16 UTC (permalink / raw)
To: Tudor Ambarus, Pratyush Yadav, Miquel Raynal, Richard Weinberger,
Vignesh Raghavendra
Cc: linux-kernel, linux-mtd, Michael Walle
In-Reply-To: <20230807-mtd-flash-info-db-rework-v3-0-e60548861b10@kernel.org>
The INFOx() macros are going away. Convert the flash_info database to
the new format.
Signed-off-by: Michael Walle <mwalle@kernel.org>
---
drivers/mtd/spi-nor/spansion.c | 370 +++++++++++++++++++++++++++--------------
1 file changed, 241 insertions(+), 129 deletions(-)
diff --git a/drivers/mtd/spi-nor/spansion.c b/drivers/mtd/spi-nor/spansion.c
index 1a1d2368c462..5953df6aff93 100644
--- a/drivers/mtd/spi-nor/spansion.c
+++ b/drivers/mtd/spi-nor/spansion.c
@@ -756,140 +756,252 @@ static const struct spi_nor_fixups s25fs_s_nor_fixups = {
};
static const struct flash_info spansion_nor_parts[] = {
- { "s25sl032p", INFO(0x010215, 0x4d00, 64 * 1024, 64)
- NO_SFDP_FLAGS(SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
- { "s25sl064p", INFO(0x010216, 0x4d00, 64 * 1024, 128)
- NO_SFDP_FLAGS(SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
- { "s25fl128s0", INFO6(0x012018, 0x4d0080, 256 * 1024, 64)
- NO_SFDP_FLAGS(SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ)
- MFR_FLAGS(USE_CLSR)
- },
- { "s25fl128s1", INFO6(0x012018, 0x4d0180, 64 * 1024, 256)
- NO_SFDP_FLAGS(SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ)
- MFR_FLAGS(USE_CLSR)
- },
- { "s25fl256s0", INFO6(0x010219, 0x4d0080, 256 * 1024, 128)
- NO_SFDP_FLAGS(SPI_NOR_SKIP_SFDP | SPI_NOR_DUAL_READ |
- SPI_NOR_QUAD_READ)
- MFR_FLAGS(USE_CLSR)
- },
- { "s25fl256s1", INFO6(0x010219, 0x4d0180, 64 * 1024, 512)
- NO_SFDP_FLAGS(SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ)
- MFR_FLAGS(USE_CLSR)
- },
- { "s25fl512s", INFO6(0x010220, 0x4d0080, 256 * 1024, 256)
- FLAGS(SPI_NOR_HAS_LOCK)
- NO_SFDP_FLAGS(SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ)
- MFR_FLAGS(USE_CLSR)
- },
- { "s25fs128s1", INFO6(0x012018, 0x4d0181, 64 * 1024, 256)
- NO_SFDP_FLAGS(SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ)
- MFR_FLAGS(USE_CLSR)
- .fixups = &s25fs_s_nor_fixups, },
- { "s25fs256s0", INFO6(0x010219, 0x4d0081, 256 * 1024, 128)
- NO_SFDP_FLAGS(SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ)
- MFR_FLAGS(USE_CLSR)
- },
- { "s25fs256s1", INFO6(0x010219, 0x4d0181, 64 * 1024, 512)
- NO_SFDP_FLAGS(SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ)
- MFR_FLAGS(USE_CLSR)
- },
- { "s25fs512s", INFO6(0x010220, 0x4d0081, 256 * 1024, 256)
- NO_SFDP_FLAGS(SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ)
- MFR_FLAGS(USE_CLSR)
- .fixups = &s25fs_s_nor_fixups, },
- { "s25sl12800", INFO(0x012018, 0x0300, 256 * 1024, 64) },
- { "s25sl12801", INFO(0x012018, 0x0301, 64 * 1024, 256) },
- { "s25fl129p0", INFO(0x012018, 0x4d00, 256 * 1024, 64)
- NO_SFDP_FLAGS(SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ)
- MFR_FLAGS(USE_CLSR)
- },
- { "s25fl129p1", INFO(0x012018, 0x4d01, 64 * 1024, 256)
- NO_SFDP_FLAGS(SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ)
- MFR_FLAGS(USE_CLSR)
- },
- { "s25sl004a", INFO(0x010212, 0, 64 * 1024, 8) },
- { "s25sl008a", INFO(0x010213, 0, 64 * 1024, 16) },
- { "s25sl016a", INFO(0x010214, 0, 64 * 1024, 32) },
- { "s25sl032a", INFO(0x010215, 0, 64 * 1024, 64) },
- { "s25sl064a", INFO(0x010216, 0, 64 * 1024, 128) },
- { "s25fl004k", INFO(0xef4013, 0, 64 * 1024, 8)
- NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ |
- SPI_NOR_QUAD_READ) },
- { "s25fl008k", INFO(0xef4014, 0, 64 * 1024, 16)
- NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ |
- SPI_NOR_QUAD_READ) },
- { "s25fl016k", INFO(0xef4015, 0, 64 * 1024, 32)
- NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ |
- SPI_NOR_QUAD_READ) },
- { "s25fl064k", INFO(0xef4017, 0, 64 * 1024, 128)
- NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ |
- SPI_NOR_QUAD_READ) },
- { "s25fl116k", INFO(0x014015, 0, 64 * 1024, 32)
- NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ |
- SPI_NOR_QUAD_READ) },
- { "s25fl132k", INFO(0x014016, 0, 64 * 1024, 64)
- NO_SFDP_FLAGS(SECT_4K) },
- { "s25fl164k", INFO(0x014017, 0, 64 * 1024, 128)
- NO_SFDP_FLAGS(SECT_4K) },
- { "s25fl204k", INFO(0x014013, 0, 64 * 1024, 8)
- NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ) },
- { "s25fl208k", INFO(0x014014, 0, 64 * 1024, 16)
- NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ) },
- { "s25fl064l", INFO(0x016017, 0, 64 * 1024, 128)
- NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ)
- FIXUP_FLAGS(SPI_NOR_4B_OPCODES) },
- { "s25fl128l", INFO(0x016018, 0, 64 * 1024, 256)
- NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ)
- FIXUP_FLAGS(SPI_NOR_4B_OPCODES) },
- { "s25fl256l", INFO(0x016019, 0, 64 * 1024, 512)
- NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ)
- FIXUP_FLAGS(SPI_NOR_4B_OPCODES) },
- { "s25fs256t", INFO6(0x342b19, 0x0f0890, 0, 0)
- MFR_FLAGS(USE_CLPEF)
- .fixups = &s25fs256t_fixups },
- { "s25hl512t", INFO6(0x342a1a, 0x0f0390, 0, 0)
- MFR_FLAGS(USE_CLPEF)
- .fixups = &s25hx_t_fixups },
- { "s25hl01gt", INFO6(0x342a1b, 0x0f0390, 0, 0)
- MFR_FLAGS(USE_CLPEF)
- .fixups = &s25hx_t_fixups },
- { "s25hl02gt", INFO6(0x342a1c, 0x0f0090, 0, 0)
- MFR_FLAGS(USE_CLPEF)
- FLAGS(NO_CHIP_ERASE)
- .fixups = &s25hx_t_fixups },
- { "s25hs512t", INFO6(0x342b1a, 0x0f0390, 0, 0)
- MFR_FLAGS(USE_CLPEF)
- .fixups = &s25hx_t_fixups },
- { "s25hs01gt", INFO6(0x342b1b, 0x0f0390, 0, 0)
- MFR_FLAGS(USE_CLPEF)
- .fixups = &s25hx_t_fixups },
- { "s25hs02gt", INFO6(0x342b1c, 0x0f0090, 0, 0)
- MFR_FLAGS(USE_CLPEF)
- FLAGS(NO_CHIP_ERASE)
- .fixups = &s25hx_t_fixups },
- { "cy15x104q", INFO6(0x042cc2, 0x7f7f7f, 512 * 1024, 1)
- FLAGS(SPI_NOR_NO_ERASE) },
- { "s28hl512t", INFO(0x345a1a, 0, 0, 0)
- MFR_FLAGS(USE_CLPEF)
+ {
+ .id = SNOR_ID(0x01, 0x02, 0x15, 0x4d, 0x00),
+ .name = "s25sl032p",
+ .size = SZ_4M,
+ .no_sfdp_flags = SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ,
+ }, {
+ .id = SNOR_ID(0x01, 0x02, 0x16, 0x4d, 0x00),
+ .name = "s25sl064p",
+ .size = SZ_8M,
+ .no_sfdp_flags = SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ,
+ }, {
+ .id = SNOR_ID(0x01, 0x20, 0x18, 0x4d, 0x00, 0x80),
+ .name = "s25fl128s0",
+ .size = SZ_16M,
+ .sector_size = SZ_256K,
+ .no_sfdp_flags = SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ,
+ .mfr_flags = USE_CLSR,
+ }, {
+ .id = SNOR_ID(0x01, 0x20, 0x18, 0x4d, 0x01, 0x80),
+ .name = "s25fl128s1",
+ .size = SZ_16M,
+ .no_sfdp_flags = SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ,
+ .mfr_flags = USE_CLSR,
+ }, {
+ .id = SNOR_ID(0x01, 0x02, 0x19, 0x4d, 0x00, 0x80),
+ .name = "s25fl256s0",
+ .size = SZ_32M,
+ .sector_size = SZ_256K,
+ .no_sfdp_flags = SPI_NOR_SKIP_SFDP | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ,
+ .mfr_flags = USE_CLSR,
+ }, {
+ .id = SNOR_ID(0x01, 0x02, 0x19, 0x4d, 0x01, 0x80),
+ .name = "s25fl256s1",
+ .size = SZ_32M,
+ .no_sfdp_flags = SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ,
+ .mfr_flags = USE_CLSR,
+ }, {
+ .id = SNOR_ID(0x01, 0x02, 0x20, 0x4d, 0x00, 0x80),
+ .name = "s25fl512s",
+ .size = SZ_64M,
+ .sector_size = SZ_256K,
+ .flags = SPI_NOR_HAS_LOCK,
+ .no_sfdp_flags = SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ,
+ .mfr_flags = USE_CLSR,
+ }, {
+ .id = SNOR_ID(0x01, 0x20, 0x18, 0x4d, 0x01, 0x81),
+ .name = "s25fs128s1",
+ .size = SZ_16M,
+ .no_sfdp_flags = SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ,
+ .mfr_flags = USE_CLSR,
+ .fixups = &s25fs_s_nor_fixups,
+ }, {
+ .id = SNOR_ID(0x01, 0x02, 0x19, 0x4d, 0x00, 0x81),
+ .name = "s25fs256s0",
+ .size = SZ_32M,
+ .sector_size = SZ_256K,
+ .no_sfdp_flags = SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ,
+ .mfr_flags = USE_CLSR,
+ }, {
+ .id = SNOR_ID(0x01, 0x02, 0x19, 0x4d, 0x01, 0x81),
+ .name = "s25fs256s1",
+ .size = SZ_32M,
+ .no_sfdp_flags = SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ,
+ .mfr_flags = USE_CLSR,
+ }, {
+ .id = SNOR_ID(0x01, 0x02, 0x20, 0x4d, 0x00, 0x81),
+ .name = "s25fs512s",
+ .size = SZ_64M,
+ .sector_size = SZ_256K,
+ .no_sfdp_flags = SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ,
+ .mfr_flags = USE_CLSR,
+ .fixups = &s25fs_s_nor_fixups,
+ }, {
+ .id = SNOR_ID(0x01, 0x20, 0x18, 0x03, 0x00),
+ .name = "s25sl12800",
+ .size = SZ_16M,
+ .sector_size = SZ_256K,
+ }, {
+ .id = SNOR_ID(0x01, 0x20, 0x18, 0x03, 0x01),
+ .name = "s25sl12801",
+ .size = SZ_16M,
+ }, {
+ .id = SNOR_ID(0x01, 0x20, 0x18, 0x4d, 0x00),
+ .name = "s25fl129p0",
+ .size = SZ_16M,
+ .sector_size = SZ_256K,
+ .no_sfdp_flags = SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ,
+ .mfr_flags = USE_CLSR,
+ }, {
+ .id = SNOR_ID(0x01, 0x20, 0x18, 0x4d, 0x01),
+ .name = "s25fl129p1",
+ .size = SZ_16M,
+ .no_sfdp_flags = SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ,
+ .mfr_flags = USE_CLSR,
+ }, {
+ .id = SNOR_ID(0x01, 0x02, 0x12),
+ .name = "s25sl004a",
+ .size = SZ_512K,
+ }, {
+ .id = SNOR_ID(0x01, 0x02, 0x13),
+ .name = "s25sl008a",
+ .size = SZ_1M,
+ }, {
+ .id = SNOR_ID(0x01, 0x02, 0x14),
+ .name = "s25sl016a",
+ .size = SZ_2M,
+ }, {
+ .id = SNOR_ID(0x01, 0x02, 0x15),
+ .name = "s25sl032a",
+ .size = SZ_4M,
+ }, {
+ .id = SNOR_ID(0x01, 0x02, 0x16),
+ .name = "s25sl064a",
+ .size = SZ_8M,
+ }, {
+ .id = SNOR_ID(0xef, 0x40, 0x13),
+ .name = "s25fl004k",
+ .size = SZ_512K,
+ .no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ,
+ }, {
+ .id = SNOR_ID(0xef, 0x40, 0x14),
+ .name = "s25fl008k",
+ .size = SZ_1M,
+ .no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ,
+ }, {
+ .id = SNOR_ID(0xef, 0x40, 0x15),
+ .name = "s25fl016k",
+ .size = SZ_2M,
+ .no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ,
+ }, {
+ .id = SNOR_ID(0xef, 0x40, 0x17),
+ .name = "s25fl064k",
+ .size = SZ_8M,
+ .no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ,
+ }, {
+ .id = SNOR_ID(0x01, 0x40, 0x15),
+ .name = "s25fl116k",
+ .size = SZ_2M,
+ .no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ,
+ }, {
+ .id = SNOR_ID(0x01, 0x40, 0x16),
+ .name = "s25fl132k",
+ .size = SZ_4M,
+ .no_sfdp_flags = SECT_4K,
+ }, {
+ .id = SNOR_ID(0x01, 0x40, 0x17),
+ .name = "s25fl164k",
+ .size = SZ_8M,
+ .no_sfdp_flags = SECT_4K,
+ }, {
+ .id = SNOR_ID(0x01, 0x40, 0x13),
+ .name = "s25fl204k",
+ .size = SZ_512K,
+ .no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ,
+ }, {
+ .id = SNOR_ID(0x01, 0x40, 0x14),
+ .name = "s25fl208k",
+ .size = SZ_1M,
+ .no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ,
+ }, {
+ .id = SNOR_ID(0x01, 0x60, 0x17),
+ .name = "s25fl064l",
+ .size = SZ_8M,
+ .no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ,
+ .fixup_flags = SPI_NOR_4B_OPCODES,
+ }, {
+ .id = SNOR_ID(0x01, 0x60, 0x18),
+ .name = "s25fl128l",
+ .size = SZ_16M,
+ .no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ,
+ .fixup_flags = SPI_NOR_4B_OPCODES,
+ }, {
+ .id = SNOR_ID(0x01, 0x60, 0x19),
+ .name = "s25fl256l",
+ .size = SZ_32M,
+ .no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ,
+ .fixup_flags = SPI_NOR_4B_OPCODES,
+ }, {
+ .id = SNOR_ID(0x34, 0x2b, 0x19, 0x0f, 0x08, 0x90),
+ .name = "s25fs256t",
+ .mfr_flags = USE_CLPEF,
+ .fixups = &s25fs256t_fixups
+ }, {
+ .id = SNOR_ID(0x34, 0x2a, 0x1a, 0x0f, 0x03, 0x90),
+ .name = "s25hl512t",
+ .mfr_flags = USE_CLPEF,
+ .fixups = &s25hx_t_fixups
+ }, {
+ .id = SNOR_ID(0x34, 0x2a, 0x1b, 0x0f, 0x03, 0x90),
+ .name = "s25hl01gt",
+ .mfr_flags = USE_CLPEF,
+ .fixups = &s25hx_t_fixups
+ }, {
+ .id = SNOR_ID(0x34, 0x2a, 0x1c, 0x0f, 0x00, 0x90),
+ .name = "s25hl02gt",
+ .mfr_flags = USE_CLPEF,
+ .flags = NO_CHIP_ERASE,
+ .fixups = &s25hx_t_fixups
+ }, {
+ .id = SNOR_ID(0x34, 0x2b, 0x1a, 0x0f, 0x03, 0x90),
+ .name = "s25hs512t",
+ .mfr_flags = USE_CLPEF,
+ .fixups = &s25hx_t_fixups
+ }, {
+ .id = SNOR_ID(0x34, 0x2b, 0x1b, 0x0f, 0x03, 0x90),
+ .name = "s25hs01gt",
+ .mfr_flags = USE_CLPEF,
+ .fixups = &s25hx_t_fixups
+ }, {
+ .id = SNOR_ID(0x34, 0x2b, 0x1c, 0x0f, 0x00, 0x90),
+ .name = "s25hs02gt",
+ .mfr_flags = USE_CLPEF,
+ .flags = NO_CHIP_ERASE,
+ .fixups = &s25hx_t_fixups
+ }, {
+ .id = SNOR_ID(0x04, 0x2c, 0xc2, 0x7f, 0x7f, 0x7f),
+ .name = "cy15x104q",
+ .size = SZ_512K,
+ .sector_size = SZ_512K,
+ .flags = SPI_NOR_NO_ERASE,
+ }, {
+ .id = SNOR_ID(0x34, 0x5a, 0x1a),
+ .name = "s28hl512t",
+ .mfr_flags = USE_CLPEF,
.fixups = &s28hx_t_fixups,
- },
- { "s28hl01gt", INFO(0x345a1b, 0, 0, 0)
- MFR_FLAGS(USE_CLPEF)
+ }, {
+ .id = SNOR_ID(0x34, 0x5a, 0x1b),
+ .name = "s28hl01gt",
+ .mfr_flags = USE_CLPEF,
.fixups = &s28hx_t_fixups,
- },
- { "s28hs512t", INFO(0x345b1a, 0, 0, 0)
- MFR_FLAGS(USE_CLPEF)
+ }, {
+ .id = SNOR_ID(0x34, 0x5b, 0x1a),
+ .name = "s28hs512t",
+ .mfr_flags = USE_CLPEF,
.fixups = &s28hx_t_fixups,
- },
- { "s28hs01gt", INFO(0x345b1b, 0, 0, 0)
- MFR_FLAGS(USE_CLPEF)
+ }, {
+ .id = SNOR_ID(0x34, 0x5b, 0x1b),
+ .name = "s28hs01gt",
+ .mfr_flags = USE_CLPEF,
.fixups = &s28hx_t_fixups,
- },
- { "s28hs02gt", INFO(0x345b1c, 0, 0, 0)
- MFR_FLAGS(USE_CLPEF)
+ }, {
+ .id = SNOR_ID(0x34, 0x5b, 0x1c),
+ .name = "s28hs02gt",
+ .mfr_flags = USE_CLPEF,
.fixups = &s28hx_t_fixups,
- },
+ }
};
/**
--
2.39.2
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^ permalink raw reply related
* [PATCH v3 23/41] mtd: spi-nor: issi: convert flash_info to new format
From: Michael Walle @ 2023-09-08 10:16 UTC (permalink / raw)
To: Tudor Ambarus, Pratyush Yadav, Miquel Raynal, Richard Weinberger,
Vignesh Raghavendra
Cc: linux-kernel, linux-mtd, Michael Walle
In-Reply-To: <20230807-mtd-flash-info-db-rework-v3-0-e60548861b10@kernel.org>
The INFOx() macros are going away. Convert the flash_info database to
the new format.
Signed-off-by: Michael Walle <mwalle@kernel.org>
---
drivers/mtd/spi-nor/issi.c | 114 +++++++++++++++++++++++++++++++--------------
1 file changed, 78 insertions(+), 36 deletions(-)
diff --git a/drivers/mtd/spi-nor/issi.c b/drivers/mtd/spi-nor/issi.c
index d31401bcab64..9478f1e61626 100644
--- a/drivers/mtd/spi-nor/issi.c
+++ b/drivers/mtd/spi-nor/issi.c
@@ -47,44 +47,86 @@ static const struct spi_nor_fixups pm25lv_nor_fixups = {
};
static const struct flash_info issi_nor_parts[] = {
- { "is25cd512", INFO(0x7f9d20, 0, 32 * 1024, 2)
- NO_SFDP_FLAGS(SECT_4K) },
- { "is25lq040b", INFO(0x9d4013, 0, 64 * 1024, 8)
- NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
- { "is25lp016d", INFO(0x9d6015, 0, 64 * 1024, 32)
- NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
- { "is25lp080d", INFO(0x9d6014, 0, 64 * 1024, 16)
- NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
- { "is25lp032", INFO(0x9d6016, 0, 64 * 1024, 64)
- NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ) },
- { "is25lp064", INFO(0x9d6017, 0, 64 * 1024, 128)
- NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ) },
- { "is25lp128", INFO(0x9d6018, 0, 64 * 1024, 256)
- NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ) },
- { "is25lp256", INFO(0x9d6019, 0, 64 * 1024, 0)
- FIXUP_FLAGS(SPI_NOR_4B_OPCODES)
- .fixups = &is25lp256_fixups },
- { "is25wp032", INFO(0x9d7016, 0, 64 * 1024, 64)
- NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
- { "is25wp064", INFO(0x9d7017, 0, 64 * 1024, 128)
- NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
- { "is25wp128", INFO(0x9d7018, 0, 64 * 1024, 256)
- NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
- { "is25wp256", INFO(0x9d7019, 0, 0, 0)
- FIXUP_FLAGS(SPI_NOR_4B_OPCODES)
- FLAGS(SPI_NOR_QUAD_PP)
- .fixups = &is25lp256_fixups },
-
- { "pm25lv512", INFO0(32 * 1024, 2)
- NO_SFDP_FLAGS(SECT_4K)
+ {
+ .id = SNOR_ID(0x7f, 0x9d, 0x20),
+ .name = "is25cd512",
+ .sector_size = SZ_32K,
+ .size = SZ_64K,
+ .no_sfdp_flags = SECT_4K,
+ }, {
+ .id = SNOR_ID(0x9d, 0x40, 0x13),
+ .name = "is25lq040b",
+ .size = SZ_512K,
+ .no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ,
+ }, {
+ .id = SNOR_ID(0x9d, 0x60, 0x15),
+ .name = "is25lp016d",
+ .size = SZ_2M,
+ .no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ,
+ }, {
+ .id = SNOR_ID(0x9d, 0x60, 0x14),
+ .name = "is25lp080d",
+ .size = SZ_1M,
+ .no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ,
+ }, {
+ .id = SNOR_ID(0x9d, 0x60, 0x16),
+ .name = "is25lp032",
+ .size = SZ_4M,
+ .no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ,
+ }, {
+ .id = SNOR_ID(0x9d, 0x60, 0x17),
+ .name = "is25lp064",
+ .size = SZ_8M,
+ .no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ,
+ }, {
+ .id = SNOR_ID(0x9d, 0x60, 0x18),
+ .name = "is25lp128",
+ .size = SZ_16M,
+ .no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ,
+ }, {
+ .id = SNOR_ID(0x9d, 0x60, 0x19),
+ .name = "is25lp256",
+ .fixups = &is25lp256_fixups,
+ .fixup_flags = SPI_NOR_4B_OPCODES,
+ }, {
+ .id = SNOR_ID(0x9d, 0x70, 0x16),
+ .name = "is25wp032",
+ .size = SZ_4M,
+ .no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ,
+ }, {
+ .id = SNOR_ID(0x9d, 0x70, 0x17),
+ .size = SZ_8M,
+ .name = "is25wp064",
+ .no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ,
+ }, {
+ .id = SNOR_ID(0x9d, 0x70, 0x18),
+ .name = "is25wp128",
+ .size = SZ_16M,
+ .no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ,
+ }, {
+ .id = SNOR_ID(0x9d, 0x70, 0x19),
+ .name = "is25wp256",
+ .flags = SPI_NOR_QUAD_PP,
+ .fixups = &is25lp256_fixups,
+ .fixup_flags = SPI_NOR_4B_OPCODES,
+ }, {
+ .name = "pm25lv512",
+ .sector_size = SZ_32K,
+ .size = SZ_64K,
+ .no_sfdp_flags = SECT_4K,
.fixups = &pm25lv_nor_fixups
- },
- { "pm25lv010", INFO0(32 * 1024, 4)
- NO_SFDP_FLAGS(SECT_4K)
+ }, {
+ .name = "pm25lv010",
+ .sector_size = SZ_32K,
+ .size = SZ_128K,
+ .no_sfdp_flags = SECT_4K,
.fixups = &pm25lv_nor_fixups
- },
- { "pm25lq032", INFO(0x7f9d46, 0, 64 * 1024, 64)
- NO_SFDP_FLAGS(SECT_4K) },
+ }, {
+ .id = SNOR_ID(0x7f, 0x9d, 0x46),
+ .name = "pm25lq032",
+ .size = SZ_4M,
+ .no_sfdp_flags = SECT_4K,
+ }
};
static void issi_nor_default_init(struct spi_nor *nor)
--
2.39.2
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^ permalink raw reply related
* Re: [PATCH] flashcp: Add write last option.
From: David Oberhollenzer @ 2023-09-08 11:55 UTC (permalink / raw)
To: Piotr Esden-Tempski, linux-mtd
In-Reply-To: <BF77DED8-F817-4BDE-A668-4F8AD46A2836@esden.net>
Applied to mtd-utils.git master.
Thanks,
David
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^ permalink raw reply
* Re: [PATCH v2 3/3] mtd: rawnand: Support for sequential cache reads
From: Martin Hundebøll @ 2023-09-08 12:25 UTC (permalink / raw)
To: Miquel Raynal, Richard Weinberger, Vignesh Raghavendra,
Tudor Ambarus, Pratyush Yadav, Michael Walle, linux-mtd
Cc: Julien Su, Jaime Liao, Alvin Zhou, Thomas Petazzoni, JaimeLiao,
Sean Nyekjær
In-Reply-To: <20230112093637.987838-4-miquel.raynal@bootlin.com>
Hi Miquel et al.
On Thu, 2023-01-12 at 10:36 +0100, Miquel Raynal wrote:
> From: JaimeLiao <jaimeliao.tw@gmail.com>
>
> Add support for sequential cache reads for controllers using the
> generic
> core helpers for their fast read/write helpers.
>
> Sequential reads may reduce the overhead when accessing physically
> continuous data by loading in cache the next page while the previous
> page gets sent out on the NAND bus.
>
> The ONFI specification provides the following additional commands to
> handle sequential cached reads:
>
> * 0x31 - READ CACHE SEQUENTIAL:
> Requires the NAND chip to load the next page into cache while
> keeping
> the current cache available for host reads.
> * 0x3F - READ CACHE END:
> Tells the NAND chip this is the end of the sequential cache read,
> the
> current cache shall remain accessible for the host but no more
> internal cache loading operation is required.
>
> On the bus, a multi page read operation is currently handled like
> this:
>
> 00 -- ADDR1 -- 30 -- WAIT_RDY (tR+tRR) -- DATA1_IN
> 00 -- ADDR2 -- 30 -- WAIT_RDY (tR+tRR) -- DATA2_IN
> 00 -- ADDR3 -- 30 -- WAIT_RDY (tR+tRR) -- DATA3_IN
>
> Sequential cached reads may instead be achieved with:
>
> 00 -- ADDR1 -- 30 -- WAIT_RDY (tR) -- \
> 31 -- WAIT_RDY (tRCBSY+tRR) -- DATA1_IN \
> 31 -- WAIT_RDY (tRCBSY+tRR) -- DATA2_IN \
> 3F -- WAIT_RDY (tRCBSY+tRR) -- DATA3_IN
>
> Below are the read speed test results with regular reads and
> sequential cached reads, on NXP i.MX6 VAR-SOM-SOLO in mapping mode
> with
> a NAND chip characterized with the following timings:
> * tR: 20 µs
> * tRCBSY: 5 µs
> * tRR: 20 ns
> and the following geometry:
> * device size: 2 MiB
> * eraseblock size: 128 kiB
> * page size: 2 kiB
>
> ============= Normal read @ 33MHz =================
> mtd_speedtest: eraseblock read speed is 15633 KiB/s
> mtd_speedtest: page read speed is 15515 KiB/s
> mtd_speedtest: 2 page read speed is 15398 KiB/s
> ===================================================
>
> ========= Sequential cache read @ 33MHz ===========
> mtd_speedtest: eraseblock read speed is 18285 KiB/s
> mtd_speedtest: page read speed is 15875 KiB/s
> mtd_speedtest: 2 page read speed is 16253 KiB/s
> ===================================================
>
> We observe an overall speed improvement of about 5% when reading
> 2 pages, up to 15% when reading an entire block. This is due to the
> ~14us gain on each additional page read (tR - (tRCBSY + tRR)).
>
> Co-developed-by: Miquel Raynal <miquel.raynal@bootlin.com>
> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
> Signed-off-by: JaimeLiao <jaimeliao.tw@gmail.com>
This patch broke our imx6ull system after doing a kernel upgrade:
[ 2.921886] ubi0: default fastmap pool size: 100
[ 2.926612] ubi0: default fastmap WL pool size: 50
[ 2.931421] ubi0: attaching mtd1
[ 3.515799] ubi0: scanning is finished
[ 3.525237] ubi0 error: vtbl_check: bad CRC at record 0: 0x88cdfb6,
not 0xffffffff
[ 3.532937] Volume table record 0 dump:
[ 3.536783] reserved_pebs -1
[ 3.539932] alignment -1
[ 3.543101] data_pad -1
[ 3.546251] vol_type 255
[ 3.549485] upd_marker 255
[ 3.552746] name_len 65535
[ 3.556155] 1st 5 characters of name:
[ 3.560429] crc 0xffffffff
[ 3.564294] ubi0 error: vtbl_check: bad CRC at record 0: 0x88cdfb6,
not 0xffffffff
[ 3.571892] Volume table record 0 dump:
[ 3.575754] reserved_pebs -1
[ 3.578906] alignment -1
[ 3.582049] data_pad -1
[ 3.585216] vol_type 255
[ 3.588452] upd_marker 255
[ 3.591687] name_len 65535
[ 3.595108] 1st 5 characters of name:
[ 3.599384] crc 0xffffffff
[ 3.603285] ubi0 error: ubi_read_volume_table: both volume tables
are corrupted
[ 3.611460] ubi0 error: ubi_attach_mtd_dev: failed to attach mtd1,
error -22
[ 3.618760] UBI error: cannot attach mtd1
[ 3.622831] UBI: block: can't open volume on ubi0_4, err=-19
[ 3.628505] UBI: block: can't open volume on ubi0_6, err=-19
[ 3.634196] UBI: block: can't open volume on ubi0_7, err=-19
It fails consistently at every attach operation. As mentioned above,
this is on an i.MX6ULL and a Toshiba NAND chip:
[ 0.530121] nand: device found, Manufacturer ID: 0x98, Chip ID: 0xdc
[ 0.530173] nand: Toshiba NAND 512MiB 3,3V 8-bit
[ 0.530194] nand: 512 MiB, SLC, erase size: 256 KiB, page size:
4096, OOB size: 128
I'm happy to perform experiments to fix this.
// Martin
> ---
> drivers/mtd/nand/raw/nand_base.c | 119
> +++++++++++++++++++++++++++++--
> include/linux/mtd/rawnand.h | 9 +++
> 2 files changed, 124 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/mtd/nand/raw/nand_base.c
> b/drivers/mtd/nand/raw/nand_base.c
> index 34395d5d3a47..0b1fd6bbb36b 100644
> --- a/drivers/mtd/nand/raw/nand_base.c
> +++ b/drivers/mtd/nand/raw/nand_base.c
> @@ -1208,6 +1208,73 @@ static int nand_lp_exec_read_page_op(struct
> nand_chip *chip, unsigned int page,
> return nand_exec_op(chip, &op);
> }
>
> +static int nand_lp_exec_cont_read_page_op(struct nand_chip *chip,
> unsigned int page,
> + unsigned int
> offset_in_page, void *buf,
> + unsigned int len, bool
> check_only)
> +{
> + const struct nand_interface_config *conf =
> + nand_get_interface_config(chip);
> + u8 addrs[5];
> + struct nand_op_instr start_instrs[] = {
> + NAND_OP_CMD(NAND_CMD_READ0, 0),
> + NAND_OP_ADDR(4, addrs, 0),
> + NAND_OP_CMD(NAND_CMD_READSTART,
> NAND_COMMON_TIMING_NS(conf, tWB_max)),
> + NAND_OP_WAIT_RDY(NAND_COMMON_TIMING_MS(conf, tR_max),
> 0),
> + NAND_OP_CMD(NAND_CMD_READCACHESEQ,
> NAND_COMMON_TIMING_NS(conf, tWB_max)),
> + NAND_OP_WAIT_RDY(NAND_COMMON_TIMING_MS(conf, tR_max),
> + NAND_COMMON_TIMING_NS(conf,
> tRR_min)),
> + NAND_OP_DATA_IN(len, buf, 0),
> + };
> + struct nand_op_instr cont_instrs[] = {
> + NAND_OP_CMD(page == chip->cont_read.last_page ?
> + NAND_CMD_READCACHEEND :
> NAND_CMD_READCACHESEQ,
> + NAND_COMMON_TIMING_NS(conf, tWB_max)),
> + NAND_OP_WAIT_RDY(NAND_COMMON_TIMING_MS(conf, tR_max),
> + NAND_COMMON_TIMING_NS(conf,
> tRR_min)),
> + NAND_OP_DATA_IN(len, buf, 0),
> + };
> + struct nand_operation start_op = NAND_OPERATION(chip->cur_cs,
> start_instrs);
> + struct nand_operation cont_op = NAND_OPERATION(chip->cur_cs,
> cont_instrs);
> + int ret;
> +
> + if (!len) {
> + start_op.ninstrs--;
> + cont_op.ninstrs--;
> + }
> +
> + ret = nand_fill_column_cycles(chip, addrs, offset_in_page);
> + if (ret < 0)
> + return ret;
> +
> + addrs[2] = page;
> + addrs[3] = page >> 8;
> +
> + if (chip->options & NAND_ROW_ADDR_3) {
> + addrs[4] = page >> 16;
> + start_instrs[1].ctx.addr.naddrs++;
> + }
> +
> + /* Check if cache reads are supported */
> + if (check_only) {
> + if (nand_check_op(chip, &start_op) ||
> nand_check_op(chip, &cont_op))
> + return -EOPNOTSUPP;
> +
> + return 0;
> + }
> +
> + if (page == chip->cont_read.first_page)
> + return nand_exec_op(chip, &start_op);
> + else
> + return nand_exec_op(chip, &cont_op);
> +}
> +
> +static bool rawnand_cont_read_ongoing(struct nand_chip *chip,
> unsigned int page)
> +{
> + return chip->cont_read.ongoing &&
> + page >= chip->cont_read.first_page &&
> + page <= chip->cont_read.last_page;
> +}
> +
> /**
> * nand_read_page_op - Do a READ PAGE operation
> * @chip: The NAND chip
> @@ -1233,10 +1300,16 @@ int nand_read_page_op(struct nand_chip *chip,
> unsigned int page,
> return -EINVAL;
>
> if (nand_has_exec_op(chip)) {
> - if (mtd->writesize > 512)
> - return nand_lp_exec_read_page_op(chip, page,
> -
> offset_in_page, buf,
> - len);
> + if (mtd->writesize > 512) {
> + if (rawnand_cont_read_ongoing(chip, page))
> + return
> nand_lp_exec_cont_read_page_op(chip, page,
> +
> offset_in_page,
> +
> buf, len, false);
> + else
> + return
> nand_lp_exec_read_page_op(chip, page,
> +
> offset_in_page, buf,
> +
> len);
> + }
>
> return nand_sp_exec_read_page_op(chip, page,
> offset_in_page,
> buf, len);
> @@ -3353,6 +3426,27 @@ static uint8_t *nand_transfer_oob(struct
> nand_chip *chip, uint8_t *oob,
> return NULL;
> }
>
> +static void rawnand_enable_cont_reads(struct nand_chip *chip,
> unsigned int page,
> + u32 readlen, int col)
> +{
> + struct mtd_info *mtd = nand_to_mtd(chip);
> +
> + if (!chip->controller->supported_op.cont_read)
> + return;
> +
> + if ((col && col + readlen < (3 * mtd->writesize)) ||
> + (!col && readlen < (2 * mtd->writesize))) {
> + chip->cont_read.ongoing = false;
> + return;
> + }
> +
> + chip->cont_read.ongoing = true;
> + chip->cont_read.first_page = page;
> + if (col)
> + chip->cont_read.first_page++;
> + chip->cont_read.last_page = page + ((readlen >> chip-
> >page_shift) & chip->pagemask);
> +}
> +
> /**
> * nand_setup_read_retry - [INTERN] Set the READ RETRY mode
> * @chip: NAND chip object
> @@ -3426,6 +3520,8 @@ static int nand_do_read_ops(struct nand_chip
> *chip, loff_t from,
> oob = ops->oobbuf;
> oob_required = oob ? 1 : 0;
>
> + rawnand_enable_cont_reads(chip, page, readlen, col);
> +
> while (1) {
> struct mtd_ecc_stats ecc_stats = mtd->ecc_stats;
>
> @@ -5009,12 +5105,27 @@ static void
> rawnand_early_check_supported_ops(struct nand_chip *chip)
> rawnand_check_data_only_read_support(chip);
> }
>
> +static void rawnand_check_cont_read_support(struct nand_chip *chip)
> +{
> + struct mtd_info *mtd = nand_to_mtd(chip);
> +
> + if (chip->read_retries)
> + return;
> +
> + if (!nand_lp_exec_cont_read_page_op(chip, 0, 0, NULL,
> + mtd->writesize, true))
> + chip->controller->supported_op.cont_read = 1;
> +}
> +
> static void rawnand_late_check_supported_ops(struct nand_chip *chip)
> {
> /* The supported_op fields should not be set by individual
> drivers */
> + WARN_ON_ONCE(chip->controller->supported_op.cont_read);
>
> if (!nand_has_exec_op(chip))
> return;
> +
> + rawnand_check_cont_read_support(chip);
> }
>
> /*
> diff --git a/include/linux/mtd/rawnand.h
> b/include/linux/mtd/rawnand.h
> index 28c5dce782dd..1b0936fe3c6e 100644
> --- a/include/linux/mtd/rawnand.h
> +++ b/include/linux/mtd/rawnand.h
> @@ -67,6 +67,8 @@ struct gpio_desc;
>
> /* Extended commands for large page devices */
> #define NAND_CMD_READSTART 0x30
> +#define NAND_CMD_READCACHESEQ 0x31
> +#define NAND_CMD_READCACHEEND 0x3f
> #define NAND_CMD_RNDOUTSTART 0xE0
> #define NAND_CMD_CACHEDPROG 0x15
>
> @@ -1099,12 +1101,14 @@ struct nand_controller_ops {
> * @supported_op.data_only_read: The controller supports reading
> more data from
> * the bus without restarting an entire read
> operation nor
> * changing the column.
> + * @supported_op.cont_read: The controller supports sequential cache
> reads.
> */
> struct nand_controller {
> struct mutex lock;
> const struct nand_controller_ops *ops;
> struct {
> unsigned int data_only_read: 1;
> + unsigned int cont_read: 1;
> } supported_op;
> };
>
> @@ -1308,6 +1312,11 @@ struct nand_chip {
> int read_retries;
> struct nand_secure_region *secure_regions;
> u8 nr_secure_regions;
> + struct {
> + bool ongoing;
> + unsigned int first_page;
> + unsigned int last_page;
> + } cont_read;
>
> /* Externals */
> struct nand_controller *controller;
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^ permalink raw reply
* [PATCH] mtd: spi-nor: atmel: add at25ff321a entry
From: nicolas.ferre @ 2023-09-08 15:14 UTC (permalink / raw)
To: Tudor Ambarus, miquel.raynal, linux-mtd
Cc: linux-arm-kernel, linux-kernel, Nicolas Ferre
From: Nicolas Ferre <nicolas.ferre@microchip.com>
Add the at25ff321a 4MB SPI flash which is able to provide
SFDP informations.
Datasheet: https://www.renesas.com/us/en/document/dst/at25ff321a-datasheet
Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
---
Hi,
This flash is present on the MikoE flash 10 Click board and was tested on
sama7g5-ek at spi frequency of 80 MHz:
Here is the test I ran:
root@sama7g5ek-sd:~# dd if=/dev/urandom of=./spi_test bs=1M count=3
3+0 records in
3+0 records out
3145728 bytes (3.1 MB, 3.0 MiB) copied, 0.932896 s, 3.4 MB/s
root@sama7g5ek-sd:~# mtd_debug write /dev/mtd0 0 3145728 spi_test
Copied 3145728 bytes from spi_test to address 0x00000000 in flash
root@sama7g5ek-sd:~# mtd_debug erase /dev/mtd0 0 3145728
Erased 3145728 bytes from address 0x00000000 in flash
root@sama7g5ek-sd:~# mtd_debug read /dev/mtd0 0 3145728 spi_read
Copied 3145728 bytes from address 0x00000000 in flash to spi_read
root@sama7g5ek-sd:~# hexdump spi_read
0000000 ffff ffff ffff ffff ffff ffff ffff ffff
*
0300000
root@sama7g5ek-sd:~# mtd_debug write /dev/mtd0 0 3145728 spi_test
Copied 3145728 bytes from spi_test to address 0x00000000 in flash
root@sama7g5ek-sd:~# mtd_debug read /dev/mtd0 0 3145728 spi_read
Copied 3145728 bytes from address 0x00000000 in flash to spi_read
root@sama7g5ek-sd:~# sha1sum spi_test spi_read
06d5459972d51a2ff4270e612270c6519e797a0b spi_test
06d5459972d51a2ff4270e612270c6519e797a0b spi_read
Here are the data from sysfs:
root@sama7g5ek-sd:~# cat /sys/bus/spi/devices/spi0.0/spi-nor/partname
at25ff321a
root@sama7g5ek-sd:~# cat /sys/bus/spi/devices/spi0.0/spi-nor/jedec_id
1f4708
root@sama7g5ek-sd:~# cat /sys/bus/spi/devices/spi0.0/spi-nor/manufacturer
atmel
root@sama7g5ek-sd:~# hexdump -C /sys/bus/spi/devices/spi0.0/spi-nor/sfdp
00000000 53 46 44 50 06 01 00 ff 00 06 01 10 10 00 00 ff |SFDP............|
00000010 e5 20 e1 ff ff ff ff 01 40 eb 08 6b 08 3b 00 ff |. ......@..k.;..|
00000020 ee ff ff ff ff ff 00 ff ff ff 00 ff 0c 20 0f 52 |............. .R|
00000030 10 d8 00 ff 50 2a 2a 01 82 ff 9c d2 64 c1 08 46 |....P**.....d..F|
00000040 7a 75 7a 75 f7 c4 d5 5c 00 06 51 ff 88 30 00 00 |zuzu...\..Q..0..|
00000050
root@sama7g5ek-sd:~# md5sum /sys/bus/spi/devices/spi0.0/spi-nor/sfdp
d540f07cbfb7c9c19654c453b561b311 /sys/bus/spi/devices/spi0.0/spi-nor/sfdp
Best regards,
Nicolas
drivers/mtd/spi-nor/atmel.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/drivers/mtd/spi-nor/atmel.c b/drivers/mtd/spi-nor/atmel.c
index 58968c1e7d2f..c94d52951481 100644
--- a/drivers/mtd/spi-nor/atmel.c
+++ b/drivers/mtd/spi-nor/atmel.c
@@ -184,6 +184,10 @@ static const struct flash_info atmel_nor_parts[] = {
FLAGS(SPI_NOR_HAS_LOCK | SPI_NOR_SWP_IS_VOLATILE)
NO_SFDP_FLAGS(SECT_4K)
.fixups = &atmel_nor_global_protection_fixups },
+ { "at25ff321a", INFO(0x1f4708, 0, 64 * 1024, 64)
+ FLAGS(SPI_NOR_HAS_LOCK | SPI_NOR_SWP_IS_VOLATILE)
+ PARSE_SFDP
+ .fixups = &atmel_nor_global_protection_fixups },
{ "at25df641", INFO(0x1f4800, 0, 64 * 1024, 128)
FLAGS(SPI_NOR_HAS_LOCK | SPI_NOR_SWP_IS_VOLATILE)
NO_SFDP_FLAGS(SECT_4K)
--
2.39.2
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^ permalink raw reply related
* Re: [PATCH] mtd: nand: qcom: Fix the node for nand unmap resource
From: Manivannan Sadhasivam @ 2023-09-09 6:03 UTC (permalink / raw)
To: Bibek Kumar Patro
Cc: miquel.raynal, richard, vigneshr, linux-mtd, linux-arm-msm,
linux-kernel, kernel, quic_charante, quic_kaushalk
In-Reply-To: <20230907092854.11408-1-quic_bibekkum@quicinc.com>
On Thu, Sep 07, 2023 at 02:58:54PM +0530, Bibek Kumar Patro wrote:
> While unmapping the nand resource in case of err_core_clk
> the dev node being passed is res_start instead of nand->dma_base
> (where the iova returned from map operation is stored) causing
> failure in unmap operation. Hence modifying the unmap operation
> to pass the nand->base_dma instead of res_start.
>
> Signed-off-by: Bibek Kumar Patro <quic_bibekkum@quicinc.com>
> ---
> drivers/mtd/nand/raw/qcom_nandc.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/mtd/nand/raw/qcom_nandc.c b/drivers/mtd/nand/raw/qcom_nandc.c
> index f583022755a2..e085a0f588eb 100644
> --- a/drivers/mtd/nand/raw/qcom_nandc.c
> +++ b/drivers/mtd/nand/raw/qcom_nandc.c
> @@ -3322,7 +3322,7 @@ static int qcom_nandc_probe(struct platform_device *pdev)
> err_aon_clk:
> clk_disable_unprepare(nandc->core_clk);
> err_core_clk:
> - dma_unmap_resource(dev, res->start, resource_size(res),
> + dma_unmap_resource(dev, nandc->base_dma, resource_size(res),
> DMA_BIDIRECTIONAL, 0);
> dev_err(&pdev->dev, "DEBUG: probe failed for nandc module\n");
This error indicates that you are sending the patch against downstream tree.
That's not appropriate. Please send your patches against mainline/mtd-next
instead and also validate properly.
- Mani
> return ret;
> --
> 2.17.1
>
--
மணிவண்ணன் சதாசிவம்
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^ permalink raw reply
* [PATCH 00/10] drm/i915/spi: spi access for discrete graphics
From: Alexander Usyskin @ 2023-09-10 12:39 UTC (permalink / raw)
To: Miquel Raynal, Richard Weinberger, Vignesh Raghavendra,
Jani Nikula, Joonas Lahtinen, Rodrigo Vivi
Cc: Alexander Usyskin, Vitaly Lubart, linux-mtd, intel-gfx
Add driver for access to the discrete graphics card
internal SPI device.
Expose device on auxiliary bus and provide driver to register
this device with MTD framework.
This series is intended to be upstreamed through drm tree.
Signed-off-by: Alexander Usyskin <alexander.usyskin@intel.com>
Alexander Usyskin (3):
drm/i915/spi: align 64bit read and write
drm/i915/spi: wake card on operations
drm/i915/spi: add support for access mode
Jani Nikula (1):
drm/i915/spi: add spi device for discrete graphics
Tomas Winkler (6):
drm/i915/spi: add intel_spi_region map
drm/i915/spi: add driver for on-die spi device
drm/i915/spi: implement region enumeration
drm/i915/spi: implement spi access functions
drm/i915/spi: spi register with mtd
drm/i915/spi: mtd: implement access handlers
drivers/gpu/drm/i915/Kconfig | 1 +
drivers/gpu/drm/i915/Makefile | 6 +
drivers/gpu/drm/i915/i915_driver.c | 7 +
drivers/gpu/drm/i915/i915_drv.h | 4 +
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/spi/intel_spi.c | 101 +++
drivers/gpu/drm/i915/spi/intel_spi.h | 33 +
drivers/gpu/drm/i915/spi/intel_spi_drv.c | 865 +++++++++++++++++++++++
8 files changed, 1018 insertions(+)
create mode 100644 drivers/gpu/drm/i915/spi/intel_spi.c
create mode 100644 drivers/gpu/drm/i915/spi/intel_spi.h
create mode 100644 drivers/gpu/drm/i915/spi/intel_spi_drv.c
--
2.34.1
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^ permalink raw reply
* [PATCH 04/10] drm/i915/spi: implement region enumeration
From: Alexander Usyskin @ 2023-09-10 12:39 UTC (permalink / raw)
To: Miquel Raynal, Richard Weinberger, Vignesh Raghavendra,
Jani Nikula, Joonas Lahtinen, Rodrigo Vivi
Cc: Alexander Usyskin, Vitaly Lubart, linux-mtd, intel-gfx,
Tomas Winkler, Lucas De Marchi
In-Reply-To: <20230910123949.1251964-1-alexander.usyskin@intel.com>
From: Tomas Winkler <tomas.winkler@intel.com>
In i915-spi, there is no access to the spi controller,
the information is extracted form the descriptor region.
CC: Rodrigo Vivi <rodrigo.vivi@intel.com>
CC: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Tomas Winkler <tomas.winkler@intel.com>
Signed-off-by: Alexander Usyskin <alexander.usyskin@intel.com>
---
drivers/gpu/drm/i915/spi/intel_spi_drv.c | 193 ++++++++++++++++++++++-
1 file changed, 192 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/spi/intel_spi_drv.c b/drivers/gpu/drm/i915/spi/intel_spi_drv.c
index 15c77b4b38bb..f32ea05f4f64 100644
--- a/drivers/gpu/drm/i915/spi/intel_spi_drv.c
+++ b/drivers/gpu/drm/i915/spi/intel_spi_drv.c
@@ -2,11 +2,12 @@
/*
* Copyright(c) 2019-2022, Intel Corporation. All rights reserved.
*/
+
#include <linux/module.h>
#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/string.h>
-#include <linux/ioport.h>
+#include <linux/io.h>
#include <linux/device.h>
#include <linux/slab.h>
#include "spi/intel_spi.h"
@@ -16,14 +17,197 @@ struct i915_spi {
void __iomem *base;
size_t size;
unsigned int nregions;
+ u32 access_map;
struct {
const char *name;
u8 id;
u64 offset;
u64 size;
+ unsigned int is_readable:1;
+ unsigned int is_writable:1;
} regions[];
};
+#define SPI_TRIGGER_REG 0x00000000
+#define SPI_VALSIG_REG 0x00000010
+#define SPI_ADDRESS_REG 0x00000040
+#define SPI_REGION_ID_REG 0x00000044
+/*
+ * [15:0]-Erase size = 0x0010 4K 0x0080 32K 0x0100 64K
+ * [23:16]-Reserved
+ * [31:24]-Erase SPI RegionID
+ */
+#define SPI_ERASE_REG 0x00000048
+#define SPI_ACCESS_ERROR_REG 0x00000070
+#define SPI_ADDRESS_ERROR_REG 0x00000074
+
+/* Flash Valid Signature */
+#define SPI_FLVALSIG 0x0FF0A55A
+
+#define SPI_MAP_ADDR_MASK 0x000000FF
+#define SPI_MAP_ADDR_SHIFT 0x00000004
+
+#define REGION_ID_DESCRIPTOR 0
+/* Flash Region Base Address */
+#define FRBA 0x40
+/* Flash Region __n - Flash Descriptor Record */
+#define FLREG(__n) (FRBA + ((__n) * 4))
+/* Flash Map 1 Register */
+#define FLMAP1_REG 0x18
+#define FLMSTR4_OFFSET 0x00C
+
+#define SPI_ACCESS_ERROR_PCIE_MASK 0x7
+
+static inline void spi_set_region_id(struct i915_spi *spi, u8 region)
+{
+ iowrite32((u32)region, spi->base + SPI_REGION_ID_REG);
+}
+
+static inline u32 spi_error(struct i915_spi *spi)
+{
+ u32 reg = ioread32(spi->base + SPI_ACCESS_ERROR_REG) &
+ SPI_ACCESS_ERROR_PCIE_MASK;
+
+ /* reset error bits */
+ if (reg)
+ iowrite32(reg, spi->base + SPI_ACCESS_ERROR_REG);
+
+ return reg;
+}
+
+static inline u32 spi_read32(struct i915_spi *spi, u32 address)
+{
+ void __iomem *base = spi->base;
+
+ iowrite32(address, base + SPI_ADDRESS_REG);
+
+ return ioread32(base + SPI_TRIGGER_REG);
+}
+
+static int spi_get_access_map(struct i915_spi *spi)
+{
+ u32 flmap1;
+ u32 fmba;
+ u32 fmstr4;
+ u32 fmstr4_addr;
+
+ spi_set_region_id(spi, REGION_ID_DESCRIPTOR);
+
+ flmap1 = spi_read32(spi, FLMAP1_REG);
+ if (spi_error(spi))
+ return -EIO;
+ /* Get Flash Master Baser Address (FMBA) */
+ fmba = ((flmap1 & SPI_MAP_ADDR_MASK) << SPI_MAP_ADDR_SHIFT);
+ fmstr4_addr = fmba + FLMSTR4_OFFSET;
+
+ fmstr4 = spi_read32(spi, fmstr4_addr);
+ if (spi_error(spi))
+ return -EIO;
+
+ spi->access_map = fmstr4;
+ return 0;
+}
+
+static bool spi_region_readable(struct i915_spi *spi, u8 region)
+{
+ if (region < 12)
+ return spi->access_map & (1 << (region + 8)); /* [19:8] */
+ else
+ return spi->access_map & (1 << (region - 12)); /* [3:0] */
+}
+
+static bool spi_region_writeable(struct i915_spi *spi, u8 region)
+{
+ if (region < 12)
+ return spi->access_map & (1 << (region + 20)); /* [31:20] */
+ else
+ return spi->access_map & (1 << (region - 8)); /* [7:4] */
+}
+
+static int i915_spi_is_valid(struct i915_spi *spi)
+{
+ u32 is_valid;
+
+ spi_set_region_id(spi, REGION_ID_DESCRIPTOR);
+
+ is_valid = spi_read32(spi, SPI_VALSIG_REG);
+ if (spi_error(spi))
+ return -EIO;
+
+ if (is_valid != SPI_FLVALSIG)
+ return -ENODEV;
+
+ return 0;
+}
+
+static int i915_spi_init(struct i915_spi *spi, struct device *device)
+{
+ int ret;
+ unsigned int i, n;
+
+ /* clean error register, previous errors are ignored */
+ spi_error(spi);
+
+ ret = i915_spi_is_valid(spi);
+ if (ret) {
+ dev_err(device, "The SPI is not valid %d\n", ret);
+ return ret;
+ }
+
+ if (spi_get_access_map(spi))
+ return -EIO;
+
+ for (i = 0, n = 0; i < spi->nregions; i++) {
+ u32 address, base, limit, region;
+ u8 id = spi->regions[i].id;
+
+ address = FLREG(id);
+ region = spi_read32(spi, address);
+
+ base = (region & 0x0000FFFF) << 12;
+ limit = (((region & 0xFFFF0000) >> 16) << 12) | 0xFFF;
+
+ dev_dbg(device, "[%d] %s: region: 0x%08X base: 0x%08x limit: 0x%08x\n",
+ id, spi->regions[i].name, region, base, limit);
+
+ if (base >= limit || (i > 0 && limit == 0)) {
+ dev_dbg(device, "[%d] %s: disabled\n",
+ id, spi->regions[i].name);
+ spi->regions[i].is_readable = 0;
+ continue;
+ }
+
+ if (spi->size < limit)
+ spi->size = limit;
+
+ spi->regions[i].offset = base;
+ spi->regions[i].size = limit - base + 1;
+ /* No write access to descriptor; mask it out*/
+ spi->regions[i].is_writable = spi_region_writeable(spi, id);
+
+ spi->regions[i].is_readable = spi_region_readable(spi, id);
+ dev_dbg(device, "Registered, %s id=%d offset=%lld size=%lld rd=%d wr=%d\n",
+ spi->regions[i].name,
+ spi->regions[i].id,
+ spi->regions[i].offset,
+ spi->regions[i].size,
+ spi->regions[i].is_readable,
+ spi->regions[i].is_writable);
+
+ if (spi->regions[i].is_readable)
+ n++;
+ }
+
+ dev_dbg(device, "Registered %d regions\n", n);
+
+ /* Need to add 1 to the amount of memory
+ * so it is reported as an even block
+ */
+ spi->size += 1;
+
+ return n;
+}
+
static void i915_spi_release(struct kref *kref)
{
struct i915_spi *spi = container_of(kref, struct i915_spi, refcnt);
@@ -91,6 +275,13 @@ static int i915_spi_probe(struct auxiliary_device *aux_dev,
goto err;
}
+ ret = i915_spi_init(spi, device);
+ if (ret < 0) {
+ dev_err(device, "cannot initialize spi\n");
+ ret = -ENODEV;
+ goto err;
+ }
+
dev_set_drvdata(&aux_dev->dev, spi);
dev_dbg(device, "i915-spi is bound\n");
--
2.34.1
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^ permalink raw reply related
* [PATCH 05/10] drm/i915/spi: implement spi access functions
From: Alexander Usyskin @ 2023-09-10 12:39 UTC (permalink / raw)
To: Miquel Raynal, Richard Weinberger, Vignesh Raghavendra,
Jani Nikula, Joonas Lahtinen, Rodrigo Vivi
Cc: Alexander Usyskin, Vitaly Lubart, linux-mtd, intel-gfx,
Tomas Winkler, Lucas De Marchi
In-Reply-To: <20230910123949.1251964-1-alexander.usyskin@intel.com>
From: Tomas Winkler <tomas.winkler@intel.com>
Implement spi_read() spi_erase() spi_write() functions.
CC: Lucas De Marchi <lucas.demarchi@intel.com>
CC: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Tomas Winkler <tomas.winkler@intel.com>
Signed-off-by: Alexander Usyskin <alexander.usyskin@intel.com>
Signed-off-by: Vitaly Lubart <vitaly.lubart@intel.com>
---
drivers/gpu/drm/i915/spi/intel_spi_drv.c | 199 +++++++++++++++++++++++
1 file changed, 199 insertions(+)
diff --git a/drivers/gpu/drm/i915/spi/intel_spi_drv.c b/drivers/gpu/drm/i915/spi/intel_spi_drv.c
index f32ea05f4f64..e3b78128ba76 100644
--- a/drivers/gpu/drm/i915/spi/intel_spi_drv.c
+++ b/drivers/gpu/drm/i915/spi/intel_spi_drv.c
@@ -10,6 +10,9 @@
#include <linux/io.h>
#include <linux/device.h>
#include <linux/slab.h>
+#include <linux/sizes.h>
+#include <linux/io-64-nonatomic-lo-hi.h>
+#include <linux/delay.h>
#include "spi/intel_spi.h"
struct i915_spi {
@@ -84,6 +87,33 @@ static inline u32 spi_read32(struct i915_spi *spi, u32 address)
return ioread32(base + SPI_TRIGGER_REG);
}
+static inline u64 spi_read64(struct i915_spi *spi, u32 address)
+{
+ void __iomem *base = spi->base;
+
+ iowrite32(address, base + SPI_ADDRESS_REG);
+
+ return readq(base + SPI_TRIGGER_REG);
+}
+
+static void spi_write32(struct i915_spi *spi, u32 address, u32 data)
+{
+ void __iomem *base = spi->base;
+
+ iowrite32(address, base + SPI_ADDRESS_REG);
+
+ iowrite32(data, base + SPI_TRIGGER_REG);
+}
+
+static void spi_write64(struct i915_spi *spi, u32 address, u64 data)
+{
+ void __iomem *base = spi->base;
+
+ iowrite32(address, base + SPI_ADDRESS_REG);
+
+ writeq(data, base + SPI_TRIGGER_REG);
+}
+
static int spi_get_access_map(struct i915_spi *spi)
{
u32 flmap1;
@@ -140,6 +170,175 @@ static int i915_spi_is_valid(struct i915_spi *spi)
return 0;
}
+__maybe_unused
+static unsigned int spi_get_region(const struct i915_spi *spi, loff_t from)
+{
+ unsigned int i;
+
+ for (i = 0; i < spi->nregions; i++) {
+ if ((spi->regions[i].offset + spi->regions[i].size - 1) > from &&
+ spi->regions[i].offset <= from &&
+ spi->regions[i].size != 0)
+ break;
+ }
+
+ return i;
+}
+
+static ssize_t spi_rewrite_partial(struct i915_spi *spi, loff_t to,
+ loff_t offset, size_t len, const u32 *newdata)
+{
+ u32 data = spi_read32(spi, to);
+
+ if (spi_error(spi))
+ return -EIO;
+
+ memcpy((u8 *)&data + offset, newdata, len);
+
+ spi_write32(spi, to, data);
+ if (spi_error(spi))
+ return -EIO;
+
+ return len;
+}
+
+__maybe_unused
+static ssize_t spi_write(struct i915_spi *spi, u8 region,
+ loff_t to, size_t len, const unsigned char *buf)
+{
+ size_t i;
+ size_t len8;
+ size_t len4;
+ size_t to4;
+ size_t to_shift;
+ size_t len_s = len;
+ ssize_t ret;
+
+ spi_set_region_id(spi, region);
+
+ to4 = ALIGN_DOWN(to, sizeof(u32));
+ to_shift = min(sizeof(u32) - ((size_t)to - to4), len);
+ if (to - to4) {
+ ret = spi_rewrite_partial(spi, to4, to - to4, to_shift,
+ (uint32_t *)&buf[0]);
+ if (ret < 0)
+ return ret;
+
+ buf += to_shift;
+ to += to_shift;
+ len_s -= to_shift;
+ }
+
+ len8 = ALIGN_DOWN(len_s, sizeof(u64));
+ for (i = 0; i < len8; i += sizeof(u64)) {
+ u64 data;
+
+ memcpy(&data, &buf[i], sizeof(u64));
+ spi_write64(spi, to + i, data);
+ if (spi_error(spi))
+ return -EIO;
+ }
+
+ len4 = len_s - len8;
+ if (len4 >= sizeof(u32)) {
+ u32 data;
+
+ memcpy(&data, &buf[i], sizeof(u32));
+ spi_write32(spi, to + i, data);
+ if (spi_error(spi))
+ return -EIO;
+ i += sizeof(u32);
+ len4 -= sizeof(u32);
+ }
+
+ if (len4 > 0) {
+ ret = spi_rewrite_partial(spi, to + i, 0, len4,
+ (uint32_t *)&buf[i]);
+ if (ret < 0)
+ return ret;
+ }
+
+ return len;
+}
+
+__maybe_unused
+static ssize_t spi_read(struct i915_spi *spi, u8 region,
+ loff_t from, size_t len, unsigned char *buf)
+{
+ size_t i;
+ size_t len8;
+ size_t len4;
+ size_t from4;
+ size_t from_shift;
+ size_t len_s = len;
+
+ spi_set_region_id(spi, region);
+
+ from4 = ALIGN_DOWN(from, sizeof(u32));
+ from_shift = min(sizeof(u32) - ((size_t)from - from4), len);
+
+ if (from - from4) {
+ u32 data = spi_read32(spi, from4);
+
+ if (spi_error(spi))
+ return -EIO;
+ memcpy(&buf[0], (u8 *)&data + (from - from4), from_shift);
+ len_s -= from_shift;
+ buf += from_shift;
+ from += from_shift;
+ }
+
+ len8 = ALIGN_DOWN(len_s, sizeof(u64));
+ for (i = 0; i < len8; i += sizeof(u64)) {
+ u64 data = spi_read64(spi, from + i);
+
+ if (spi_error(spi))
+ return -EIO;
+
+ memcpy(&buf[i], &data, sizeof(data));
+ }
+
+ len4 = len_s - len8;
+ if (len4 >= sizeof(u32)) {
+ u32 data = spi_read32(spi, from + i);
+
+ if (spi_error(spi))
+ return -EIO;
+ memcpy(&buf[i], &data, sizeof(data));
+ i += sizeof(u32);
+ len4 -= sizeof(u32);
+ }
+
+ if (len4 > 0) {
+ u32 data = spi_read32(spi, from + i);
+
+ if (spi_error(spi))
+ return -EIO;
+ memcpy(&buf[i], &data, len4);
+ }
+
+ return len;
+}
+
+__maybe_unused
+static ssize_t
+spi_erase(struct i915_spi *spi, u8 region, loff_t from, u64 len, u64 *fail_addr)
+{
+ u64 i;
+ const u32 block = 0x10;
+ void __iomem *base = spi->base;
+
+ for (i = 0; i < len; i += SZ_4K) {
+ iowrite32(from + i, base + SPI_ADDRESS_REG);
+ iowrite32(region << 24 | block, base + SPI_ERASE_REG);
+ /* Since the writes are via sguint
+ * we cannot do back to back erases.
+ */
+ msleep(50);
+ }
+ return len;
+}
+
static int i915_spi_init(struct i915_spi *spi, struct device *device)
{
int ret;
--
2.34.1
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^ permalink raw reply related
* [PATCH 02/10] drm/i915/spi: add intel_spi_region map
From: Alexander Usyskin @ 2023-09-10 12:39 UTC (permalink / raw)
To: Miquel Raynal, Richard Weinberger, Vignesh Raghavendra,
Jani Nikula, Joonas Lahtinen, Rodrigo Vivi
Cc: Alexander Usyskin, Vitaly Lubart, linux-mtd, intel-gfx,
Tomas Winkler, Lucas De Marchi
In-Reply-To: <20230910123949.1251964-1-alexander.usyskin@intel.com>
From: Tomas Winkler <tomas.winkler@intel.com>
Add the dGFX spi region map and convey it via auxiliary device
to the spi child device.
CC: Rodrigo Vivi <rodrigo.vivi@intel.com>
CC: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Alexander Usyskin <alexander.usyskin@intel.com>
Signed-off-by: Tomas Winkler <tomas.winkler@intel.com>
---
drivers/gpu/drm/i915/spi/intel_spi.c | 8 ++++++++
drivers/gpu/drm/i915/spi/intel_spi.h | 6 ++++++
2 files changed, 14 insertions(+)
diff --git a/drivers/gpu/drm/i915/spi/intel_spi.c b/drivers/gpu/drm/i915/spi/intel_spi.c
index 9eb5ab6bc4b9..c697ca226e34 100644
--- a/drivers/gpu/drm/i915/spi/intel_spi.c
+++ b/drivers/gpu/drm/i915/spi/intel_spi.c
@@ -10,6 +10,13 @@
#define GEN12_GUNIT_SPI_SIZE 0x80
+static const struct i915_spi_region regions[I915_SPI_REGIONS] = {
+ [0] = { .name = "DESCRIPTOR", },
+ [2] = { .name = "GSC", },
+ [11] = { .name = "OptionROM", },
+ [12] = { .name = "DAM", },
+};
+
static void i915_spi_release_dev(struct device *dev)
{
}
@@ -29,6 +36,7 @@ void intel_spi_init(struct intel_spi *spi, struct drm_i915_private *dev_priv)
spi->bar.end = spi->bar.start + GEN12_GUNIT_SPI_SIZE - 1;
spi->bar.flags = IORESOURCE_MEM;
spi->bar.desc = IORES_DESC_NONE;
+ spi->regions = regions;
aux_dev->name = "spi";
aux_dev->id = (pci_domain_nr(pdev->bus) << 16) |
diff --git a/drivers/gpu/drm/i915/spi/intel_spi.h b/drivers/gpu/drm/i915/spi/intel_spi.h
index a58bf79dcbc9..1ecf1a8581b4 100644
--- a/drivers/gpu/drm/i915/spi/intel_spi.h
+++ b/drivers/gpu/drm/i915/spi/intel_spi.h
@@ -10,10 +10,16 @@
struct drm_i915_private;
+#define I915_SPI_REGIONS 13
+struct i915_spi_region {
+ const char *name;
+};
+
struct intel_spi {
struct auxiliary_device aux_dev;
struct drm_i915_private *i915;
struct resource bar;
+ const struct i915_spi_region *regions;
};
#define auxiliary_dev_to_intel_spi_dev(auxiliary_dev) \
--
2.34.1
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^ permalink raw reply related
* [PATCH 01/10] drm/i915/spi: add spi device for discrete graphics
From: Alexander Usyskin @ 2023-09-10 12:39 UTC (permalink / raw)
To: Miquel Raynal, Richard Weinberger, Vignesh Raghavendra,
Jani Nikula, Joonas Lahtinen, Rodrigo Vivi
Cc: Alexander Usyskin, Vitaly Lubart, linux-mtd, intel-gfx,
Jani Nikula, Lucas De Marchi, Tomas Winkler
In-Reply-To: <20230910123949.1251964-1-alexander.usyskin@intel.com>
From: Jani Nikula <jani.nikula@intel.com>
Enable access to internal spi on DGFX devices via a child device.
The spi child device is exposed via auxiliary bus.
CC: Rodrigo Vivi <rodrigo.vivi@intel.com>
CC: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Tomas Winkler <tomas.winkler@intel.com>
Signed-off-by: Alexander Usyskin <alexander.usyskin@intel.com>
---
drivers/gpu/drm/i915/Makefile | 3 ++
drivers/gpu/drm/i915/i915_driver.c | 7 +++
drivers/gpu/drm/i915/i915_drv.h | 4 ++
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/spi/intel_spi.c | 68 ++++++++++++++++++++++++++++
drivers/gpu/drm/i915/spi/intel_spi.h | 26 +++++++++++
6 files changed, 109 insertions(+)
create mode 100644 drivers/gpu/drm/i915/spi/intel_spi.c
create mode 100644 drivers/gpu/drm/i915/spi/intel_spi.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 79f65eff6bb2..f16870ad2615 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -222,6 +222,9 @@ i915-y += \
# graphics system controller (GSC) support
i915-y += gt/intel_gsc.o
+# graphics spi device (DGFX) support
+i915-y += spi/intel_spi.o
+
# graphics hardware monitoring (HWMON) support
i915-$(CONFIG_HWMON) += i915_hwmon.o
diff --git a/drivers/gpu/drm/i915/i915_driver.c b/drivers/gpu/drm/i915/i915_driver.c
index f8dbee7a5af7..aeeb34a8dde2 100644
--- a/drivers/gpu/drm/i915/i915_driver.c
+++ b/drivers/gpu/drm/i915/i915_driver.c
@@ -80,6 +80,8 @@
#include "soc/intel_dram.h"
#include "soc/intel_gmch.h"
+#include "spi/intel_spi.h"
+
#include "i915_debugfs.h"
#include "i915_driver.h"
#include "i915_drm_client.h"
@@ -666,6 +668,8 @@ static void i915_driver_unregister(struct drm_i915_private *dev_priv)
i915_hwmon_unregister(dev_priv);
+ intel_spi_fini(&dev_priv->spi);
+
i915_perf_unregister(dev_priv);
i915_pmu_unregister(dev_priv);
@@ -1133,6 +1137,9 @@ static int i915_drm_suspend_late(struct drm_device *dev, bool hibernation)
i915_gem_suspend_late(dev_priv);
+
+ intel_spi_init(&dev_priv->spi, dev_priv);
+
for_each_gt(gt, dev_priv, i)
intel_uncore_suspend(gt->uncore);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 87ffc477c3b1..abc601200cb4 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -51,6 +51,8 @@
#include "soc/intel_pch.h"
+#include "spi/intel_spi.h"
+
#include "i915_drm_client.h"
#include "i915_gem.h"
#include "i915_gpu_error.h"
@@ -315,6 +317,8 @@ struct drm_i915_private {
struct i915_perf perf;
+ struct intel_spi spi;
+
struct i915_hwmon *hwmon;
/* Abstract the submission mechanism (legacy ringbuffer or execlists) away */
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index e00e4d569ba9..0f8b01495b77 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -930,6 +930,7 @@
#define DG2_GSC_HECI2_BASE 0x00374000
#define MTL_GSC_HECI1_BASE 0x00116000
#define MTL_GSC_HECI2_BASE 0x00117000
+#define GEN12_GUNIT_SPI_BASE 0x00102040
#define HECI_H_CSR(base) _MMIO((base) + 0x4)
#define HECI_H_CSR_IE REG_BIT(0)
diff --git a/drivers/gpu/drm/i915/spi/intel_spi.c b/drivers/gpu/drm/i915/spi/intel_spi.c
new file mode 100644
index 000000000000..9eb5ab6bc4b9
--- /dev/null
+++ b/drivers/gpu/drm/i915/spi/intel_spi.c
@@ -0,0 +1,68 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright(c) 2019-2022, Intel Corporation. All rights reserved.
+ */
+
+#include <linux/irq.h>
+#include "i915_reg.h"
+#include "i915_drv.h"
+#include "spi/intel_spi.h"
+
+#define GEN12_GUNIT_SPI_SIZE 0x80
+
+static void i915_spi_release_dev(struct device *dev)
+{
+}
+
+void intel_spi_init(struct intel_spi *spi, struct drm_i915_private *dev_priv)
+{
+ struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
+ struct auxiliary_device *aux_dev = &spi->aux_dev;
+ int ret;
+
+ /* Only the DGFX devices have internal SPI */
+ if (!IS_DGFX(dev_priv))
+ return;
+
+ spi->bar.parent = &pdev->resource[0];
+ spi->bar.start = GEN12_GUNIT_SPI_BASE + pdev->resource[0].start;
+ spi->bar.end = spi->bar.start + GEN12_GUNIT_SPI_SIZE - 1;
+ spi->bar.flags = IORESOURCE_MEM;
+ spi->bar.desc = IORES_DESC_NONE;
+
+ aux_dev->name = "spi";
+ aux_dev->id = (pci_domain_nr(pdev->bus) << 16) |
+ PCI_DEVID(pdev->bus->number, pdev->devfn);
+ aux_dev->dev.parent = &pdev->dev;
+ aux_dev->dev.release = i915_spi_release_dev;
+
+ ret = auxiliary_device_init(aux_dev);
+ if (ret) {
+ dev_err(&pdev->dev, "i915-spi aux init failed %d\n", ret);
+ return;
+ }
+
+ ret = auxiliary_device_add(aux_dev);
+ if (ret) {
+ dev_err(&pdev->dev, "i915-spi aux add failed %d\n", ret);
+ auxiliary_device_uninit(aux_dev);
+ return;
+ }
+
+ spi->i915 = dev_priv;
+}
+
+void intel_spi_fini(struct intel_spi *spi)
+{
+ struct pci_dev *pdev;
+
+ if (!spi->i915)
+ return;
+
+ pdev = to_pci_dev(spi->i915->drm.dev);
+
+ dev_dbg(&pdev->dev, "removing i915-spi cell\n");
+
+ auxiliary_device_delete(&spi->aux_dev);
+ auxiliary_device_uninit(&spi->aux_dev);
+}
diff --git a/drivers/gpu/drm/i915/spi/intel_spi.h b/drivers/gpu/drm/i915/spi/intel_spi.h
new file mode 100644
index 000000000000..a58bf79dcbc9
--- /dev/null
+++ b/drivers/gpu/drm/i915/spi/intel_spi.h
@@ -0,0 +1,26 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright(c) 2019-2022, Intel Corporation. All rights reserved.
+ */
+
+#ifndef __INTEL_SPI_DEV_H__
+#define __INTEL_SPI_DEV_H__
+
+#include <linux/auxiliary_bus.h>
+
+struct drm_i915_private;
+
+struct intel_spi {
+ struct auxiliary_device aux_dev;
+ struct drm_i915_private *i915;
+ struct resource bar;
+};
+
+#define auxiliary_dev_to_intel_spi_dev(auxiliary_dev) \
+ container_of(auxiliary_dev, struct intel_spi, aux_dev)
+
+void intel_spi_init(struct intel_spi *spi, struct drm_i915_private *i915);
+
+void intel_spi_fini(struct intel_spi *spi);
+
+#endif /* __INTEL_SPI_DEV_H__ */
--
2.34.1
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^ permalink raw reply related
* [PATCH 03/10] drm/i915/spi: add driver for on-die spi device
From: Alexander Usyskin @ 2023-09-10 12:39 UTC (permalink / raw)
To: Miquel Raynal, Richard Weinberger, Vignesh Raghavendra,
Jani Nikula, Joonas Lahtinen, Rodrigo Vivi
Cc: Alexander Usyskin, Vitaly Lubart, linux-mtd, intel-gfx,
Tomas Winkler, Lucas De Marchi
In-Reply-To: <20230910123949.1251964-1-alexander.usyskin@intel.com>
From: Tomas Winkler <tomas.winkler@intel.com>
Add auxiliary driver for i915 on-die spi device.
CC: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Tomas Winkler <tomas.winkler@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Alexander Usyskin <alexander.usyskin@intel.com>
---
drivers/gpu/drm/i915/Kconfig | 1 +
drivers/gpu/drm/i915/Makefile | 3 +
drivers/gpu/drm/i915/spi/intel_spi_drv.c | 141 +++++++++++++++++++++++
3 files changed, 145 insertions(+)
create mode 100644 drivers/gpu/drm/i915/spi/intel_spi_drv.c
diff --git a/drivers/gpu/drm/i915/Kconfig b/drivers/gpu/drm/i915/Kconfig
index ce397a8797f7..c13d25658d87 100644
--- a/drivers/gpu/drm/i915/Kconfig
+++ b/drivers/gpu/drm/i915/Kconfig
@@ -39,6 +39,7 @@ config DRM_I915
select DRM_TTM
select DRM_BUDDY
select AUXILIARY_BUS
+ select MTD
help
Choose this option if you have a system that has "Intel Graphics
Media Accelerator" or "HD Graphics" integrated graphics,
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index f16870ad2615..544e39448c3c 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -393,6 +393,9 @@ ifdef CONFIG_DRM_I915_WERROR
cmd_checkdoc = $(srctree)/scripts/kernel-doc -none -Werror $<
endif
+obj-m += i915_spi.o
+i915_spi-y := spi/intel_spi_drv.o
+
# header test
# exclude some broken headers from the test coverage
diff --git a/drivers/gpu/drm/i915/spi/intel_spi_drv.c b/drivers/gpu/drm/i915/spi/intel_spi_drv.c
new file mode 100644
index 000000000000..15c77b4b38bb
--- /dev/null
+++ b/drivers/gpu/drm/i915/spi/intel_spi_drv.c
@@ -0,0 +1,141 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright(c) 2019-2022, Intel Corporation. All rights reserved.
+ */
+#include <linux/module.h>
+#include <linux/types.h>
+#include <linux/kernel.h>
+#include <linux/string.h>
+#include <linux/ioport.h>
+#include <linux/device.h>
+#include <linux/slab.h>
+#include "spi/intel_spi.h"
+
+struct i915_spi {
+ struct kref refcnt;
+ void __iomem *base;
+ size_t size;
+ unsigned int nregions;
+ struct {
+ const char *name;
+ u8 id;
+ u64 offset;
+ u64 size;
+ } regions[];
+};
+
+static void i915_spi_release(struct kref *kref)
+{
+ struct i915_spi *spi = container_of(kref, struct i915_spi, refcnt);
+ int i;
+
+ pr_debug("freeing spi memory\n");
+ for (i = 0; i < spi->nregions; i++)
+ kfree(spi->regions[i].name);
+ kfree(spi);
+}
+
+static int i915_spi_probe(struct auxiliary_device *aux_dev,
+ const struct auxiliary_device_id *aux_dev_id)
+{
+ struct intel_spi *ispi = auxiliary_dev_to_intel_spi_dev(aux_dev);
+ struct device *device;
+ struct i915_spi *spi;
+ unsigned int nregions;
+ unsigned int i, n;
+ size_t size;
+ char *name;
+ size_t name_size;
+ int ret;
+
+ device = &aux_dev->dev;
+
+ /* count available regions */
+ for (nregions = 0, i = 0; i < I915_SPI_REGIONS; i++) {
+ if (ispi->regions[i].name)
+ nregions++;
+ }
+
+ if (!nregions) {
+ dev_err(device, "no regions defined\n");
+ return -ENODEV;
+ }
+
+ size = sizeof(*spi) + sizeof(spi->regions[0]) * nregions;
+ spi = kzalloc(size, GFP_KERNEL);
+ if (!spi)
+ return -ENOMEM;
+
+ kref_init(&spi->refcnt);
+
+ spi->nregions = nregions;
+ for (n = 0, i = 0; i < I915_SPI_REGIONS; i++) {
+ if (ispi->regions[i].name) {
+ name_size = strlen(dev_name(&aux_dev->dev)) +
+ strlen(ispi->regions[i].name) + 2; /* for point */
+ name = kzalloc(name_size, GFP_KERNEL);
+ if (!name)
+ continue;
+ snprintf(name, name_size, "%s.%s",
+ dev_name(&aux_dev->dev), ispi->regions[i].name);
+ spi->regions[n].name = name;
+ spi->regions[n].id = i;
+ n++;
+ }
+ }
+
+ spi->base = devm_ioremap_resource(device, &ispi->bar);
+ if (IS_ERR(spi->base)) {
+ dev_err(device, "mmio not mapped\n");
+ ret = PTR_ERR(spi->base);
+ goto err;
+ }
+
+ dev_set_drvdata(&aux_dev->dev, spi);
+
+ dev_dbg(device, "i915-spi is bound\n");
+
+ return 0;
+
+err:
+ kref_put(&spi->refcnt, i915_spi_release);
+ return ret;
+}
+
+static void i915_spi_remove(struct auxiliary_device *aux_dev)
+{
+ struct i915_spi *spi = dev_get_drvdata(&aux_dev->dev);
+
+ if (!spi)
+ return;
+
+ dev_set_drvdata(&aux_dev->dev, NULL);
+
+ kref_put(&spi->refcnt, i915_spi_release);
+}
+
+static const struct auxiliary_device_id i915_spi_id_table[] = {
+ {
+ .name = "i915.spi",
+ },
+ {
+ /* sentinel */
+ }
+};
+MODULE_DEVICE_TABLE(auxiliary, i915_spi_id_table);
+
+static struct auxiliary_driver i915_spi_driver = {
+ .probe = i915_spi_probe,
+ .remove = i915_spi_remove,
+ .driver = {
+ /* auxiliary_driver_register() sets .name to be the modname */
+ },
+ .id_table = i915_spi_id_table
+};
+
+module_auxiliary_driver(i915_spi_driver);
+
+MODULE_ALIAS("auxiliary:i915.spi");
+MODULE_LICENSE("Dual MIT/GPL");
+MODULE_AUTHOR("Intel Corporation");
+MODULE_DESCRIPTION("Intel DGFX SPI driver");
--
2.34.1
______________________________________________________
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http://lists.infradead.org/mailman/listinfo/linux-mtd/
^ permalink raw reply related
* [PATCH 06/10] drm/i915/spi: spi register with mtd
From: Alexander Usyskin @ 2023-09-10 12:39 UTC (permalink / raw)
To: Miquel Raynal, Richard Weinberger, Vignesh Raghavendra,
Jani Nikula, Joonas Lahtinen, Rodrigo Vivi
Cc: Alexander Usyskin, Vitaly Lubart, linux-mtd, intel-gfx,
Tomas Winkler, Lucas De Marchi
In-Reply-To: <20230910123949.1251964-1-alexander.usyskin@intel.com>
From: Tomas Winkler <tomas.winkler@intel.com>
Register the on-die spi device with the mtd subsystem.
Refcount spi object on _get and _put mtd callbacks.
CC: Rodrigo Vivi <rodrigo.vivi@intel.com>
CC: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Tomas Winkler <tomas.winkler@intel.com>
Signed-off-by: Alexander Usyskin <alexander.usyskin@intel.com>
---
drivers/gpu/drm/i915/spi/intel_spi_drv.c | 118 +++++++++++++++++++++++
1 file changed, 118 insertions(+)
diff --git a/drivers/gpu/drm/i915/spi/intel_spi_drv.c b/drivers/gpu/drm/i915/spi/intel_spi_drv.c
index e3b78128ba76..355f9ad71602 100644
--- a/drivers/gpu/drm/i915/spi/intel_spi_drv.c
+++ b/drivers/gpu/drm/i915/spi/intel_spi_drv.c
@@ -15,8 +15,13 @@
#include <linux/delay.h>
#include "spi/intel_spi.h"
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/partitions.h>
+
struct i915_spi {
struct kref refcnt;
+ struct mtd_info mtd;
+ struct mutex lock; /* region access lock */
void __iomem *base;
size_t size;
unsigned int nregions;
@@ -407,6 +412,29 @@ static int i915_spi_init(struct i915_spi *spi, struct device *device)
return n;
}
+static int i915_spi_erase(struct mtd_info *mtd, struct erase_info *info)
+{
+ dev_err(&mtd->dev, "erasing %lld %lld\n", info->addr, info->len);
+
+ return 0;
+}
+
+static int i915_spi_read(struct mtd_info *mtd, loff_t from, size_t len,
+ size_t *retlen, u_char *buf)
+{
+ dev_err(&mtd->dev, "read %lld %zd\n", from, len);
+
+ return 0;
+}
+
+static int i915_spi_write(struct mtd_info *mtd, loff_t to, size_t len,
+ size_t *retlen, const u_char *buf)
+{
+ dev_err(&mtd->dev, "writing %lld %zd\n", to, len);
+
+ return 0;
+}
+
static void i915_spi_release(struct kref *kref)
{
struct i915_spi *spi = container_of(kref, struct i915_spi, refcnt);
@@ -415,9 +443,90 @@ static void i915_spi_release(struct kref *kref)
pr_debug("freeing spi memory\n");
for (i = 0; i < spi->nregions; i++)
kfree(spi->regions[i].name);
+ mutex_destroy(&spi->lock);
kfree(spi);
}
+static int i915_spi_get_device(struct mtd_info *mtd)
+{
+ struct mtd_info *master;
+ struct i915_spi *spi;
+
+ if (!mtd)
+ return -ENODEV;
+
+ master = mtd_get_master(mtd);
+ spi = master->priv;
+ if (WARN_ON(!spi))
+ return -EINVAL;
+ pr_debug("get spi %s %d\n", mtd->name, kref_read(&spi->refcnt));
+ kref_get(&spi->refcnt);
+
+ return 0;
+}
+
+static void i915_spi_put_device(struct mtd_info *mtd)
+{
+ struct mtd_info *master;
+ struct i915_spi *spi;
+
+ if (!mtd)
+ return;
+
+ master = mtd_get_master(mtd);
+ spi = master->priv;
+ if (WARN_ON(!spi))
+ return;
+ pr_debug("put spi %s %d\n", mtd->name, kref_read(&spi->refcnt));
+ kref_put(&spi->refcnt, i915_spi_release);
+}
+
+static int i915_spi_init_mtd(struct i915_spi *spi, struct device *device,
+ unsigned int nparts)
+{
+ unsigned int i;
+ unsigned int n;
+ struct mtd_partition *parts = NULL;
+ int ret;
+
+ dev_dbg(device, "registering with mtd\n");
+
+ spi->mtd.owner = THIS_MODULE;
+ spi->mtd.dev.parent = device;
+ spi->mtd.flags = MTD_CAP_NORFLASH | MTD_WRITEABLE;
+ spi->mtd.type = MTD_DATAFLASH;
+ spi->mtd.priv = spi;
+ spi->mtd._write = i915_spi_write;
+ spi->mtd._read = i915_spi_read;
+ spi->mtd._erase = i915_spi_erase;
+ spi->mtd._get_device = i915_spi_get_device;
+ spi->mtd._put_device = i915_spi_put_device;
+ spi->mtd.writesize = SZ_1; /* 1 byte granularity */
+ spi->mtd.erasesize = SZ_4K; /* 4K bytes granularity */
+ spi->mtd.size = spi->size;
+
+ parts = kcalloc(spi->nregions, sizeof(*parts), GFP_KERNEL);
+ if (!parts)
+ return -ENOMEM;
+
+ for (i = 0, n = 0; i < spi->nregions && n < nparts; i++) {
+ if (!spi->regions[i].is_readable)
+ continue;
+ parts[n].name = spi->regions[i].name;
+ parts[n].offset = spi->regions[i].offset;
+ parts[n].size = spi->regions[i].size;
+ if (!spi->regions[i].is_writable)
+ parts[n].mask_flags = MTD_WRITEABLE;
+ n++;
+ }
+
+ ret = mtd_device_register(&spi->mtd, parts, n);
+
+ kfree(parts);
+
+ return ret;
+}
+
static int i915_spi_probe(struct auxiliary_device *aux_dev,
const struct auxiliary_device_id *aux_dev_id)
{
@@ -449,6 +558,7 @@ static int i915_spi_probe(struct auxiliary_device *aux_dev,
if (!spi)
return -ENOMEM;
+ mutex_init(&spi->lock);
kref_init(&spi->refcnt);
spi->nregions = nregions;
@@ -481,6 +591,12 @@ static int i915_spi_probe(struct auxiliary_device *aux_dev,
goto err;
}
+ ret = i915_spi_init_mtd(spi, device, ret);
+ if (ret) {
+ dev_err(device, "i915-spi failed init mtd %d\n", ret);
+ goto err;
+ }
+
dev_set_drvdata(&aux_dev->dev, spi);
dev_dbg(device, "i915-spi is bound\n");
@@ -499,6 +615,8 @@ static void i915_spi_remove(struct auxiliary_device *aux_dev)
if (!spi)
return;
+ mtd_device_unregister(&spi->mtd);
+
dev_set_drvdata(&aux_dev->dev, NULL);
kref_put(&spi->refcnt, i915_spi_release);
--
2.34.1
______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/
^ permalink raw reply related
* [PATCH 07/10] drm/i915/spi: mtd: implement access handlers
From: Alexander Usyskin @ 2023-09-10 12:39 UTC (permalink / raw)
To: Miquel Raynal, Richard Weinberger, Vignesh Raghavendra,
Jani Nikula, Joonas Lahtinen, Rodrigo Vivi
Cc: Alexander Usyskin, Vitaly Lubart, linux-mtd, intel-gfx,
Tomas Winkler, Lucas De Marchi
In-Reply-To: <20230910123949.1251964-1-alexander.usyskin@intel.com>
From: Tomas Winkler <tomas.winkler@intel.com>
Implement mtd read, erase, and write handlers.
For erase operation address and size should be 4K aligned.
For write operation address and size has to be 4bytes aligned.
CC: Rodrigo Vivi <rodrigo.vivi@intel.com>
CC: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Tomas Winkler <tomas.winkler@intel.com>
Signed-off-by: Vitaly Lubart <vitaly.lubart@intel.com>
Signed-off-by: Alexander Usyskin <alexander.usyskin@intel.com>
---
drivers/gpu/drm/i915/spi/intel_spi_drv.c | 152 +++++++++++++++++++++--
1 file changed, 144 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/spi/intel_spi_drv.c b/drivers/gpu/drm/i915/spi/intel_spi_drv.c
index 355f9ad71602..39369a0c64a0 100644
--- a/drivers/gpu/drm/i915/spi/intel_spi_drv.c
+++ b/drivers/gpu/drm/i915/spi/intel_spi_drv.c
@@ -175,7 +175,6 @@ static int i915_spi_is_valid(struct i915_spi *spi)
return 0;
}
-__maybe_unused
static unsigned int spi_get_region(const struct i915_spi *spi, loff_t from)
{
unsigned int i;
@@ -207,7 +206,6 @@ static ssize_t spi_rewrite_partial(struct i915_spi *spi, loff_t to,
return len;
}
-__maybe_unused
static ssize_t spi_write(struct i915_spi *spi, u8 region,
loff_t to, size_t len, const unsigned char *buf)
{
@@ -266,7 +264,6 @@ static ssize_t spi_write(struct i915_spi *spi, u8 region,
return len;
}
-__maybe_unused
static ssize_t spi_read(struct i915_spi *spi, u8 region,
loff_t from, size_t len, unsigned char *buf)
{
@@ -325,7 +322,6 @@ static ssize_t spi_read(struct i915_spi *spi, u8 region,
return len;
}
-__maybe_unused
static ssize_t
spi_erase(struct i915_spi *spi, u8 region, loff_t from, u64 len, u64 *fail_addr)
{
@@ -414,24 +410,164 @@ static int i915_spi_init(struct i915_spi *spi, struct device *device)
static int i915_spi_erase(struct mtd_info *mtd, struct erase_info *info)
{
- dev_err(&mtd->dev, "erasing %lld %lld\n", info->addr, info->len);
+ struct i915_spi *spi;
+ unsigned int idx;
+ u8 region;
+ u64 addr;
+ ssize_t bytes;
+ loff_t from;
+ size_t len;
+ size_t total_len;
+ int ret = 0;
+
+ if (!mtd || !info)
+ return -EINVAL;
- return 0;
+ spi = mtd->priv;
+ if (WARN_ON(!spi))
+ return -EINVAL;
+
+ if (!IS_ALIGNED(info->addr, SZ_4K) || !IS_ALIGNED(info->len, SZ_4K)) {
+ dev_err(&mtd->dev, "unaligned erase %llx %llx\n",
+ info->addr, info->len);
+ info->fail_addr = MTD_FAIL_ADDR_UNKNOWN;
+ return -EINVAL;
+ }
+
+ total_len = info->len;
+ addr = info->addr;
+
+ mutex_lock(&spi->lock);
+
+ while (total_len > 0) {
+ if (!IS_ALIGNED(addr, SZ_4K) || !IS_ALIGNED(total_len, SZ_4K)) {
+ dev_err(&mtd->dev, "unaligned erase %llx %zx\n", addr, total_len);
+ info->fail_addr = addr;
+ ret = -ERANGE;
+ goto out;
+ }
+
+ idx = spi_get_region(spi, addr);
+ if (idx >= spi->nregions) {
+ dev_err(&mtd->dev, "out of range");
+ info->fail_addr = MTD_FAIL_ADDR_UNKNOWN;
+ ret = -ERANGE;
+ goto out;
+ }
+
+ from = addr - spi->regions[idx].offset;
+ region = spi->regions[idx].id;
+ len = total_len;
+ if (len > spi->regions[idx].size - from)
+ len = spi->regions[idx].size - from;
+
+ dev_dbg(&mtd->dev, "erasing region[%d] %s from %llx len %zx\n",
+ region, spi->regions[idx].name, from, len);
+
+ bytes = spi_erase(spi, region, from, len, &info->fail_addr);
+ if (bytes < 0) {
+ dev_dbg(&mtd->dev, "erase failed with %zd\n", bytes);
+ info->fail_addr += spi->regions[idx].offset;
+ ret = bytes;
+ goto out;
+ }
+
+ addr += len;
+ total_len -= len;
+ }
+
+out:
+ mutex_unlock(&spi->lock);
+ return ret;
}
static int i915_spi_read(struct mtd_info *mtd, loff_t from, size_t len,
size_t *retlen, u_char *buf)
{
- dev_err(&mtd->dev, "read %lld %zd\n", from, len);
+ struct i915_spi *spi;
+ ssize_t ret;
+ unsigned int idx;
+ u8 region;
+
+ if (!mtd)
+ return -EINVAL;
+
+ spi = mtd->priv;
+ if (WARN_ON(!spi))
+ return -EINVAL;
+
+ idx = spi_get_region(spi, from);
+ dev_dbg(&mtd->dev, "reading region[%d] %s from %lld len %zd\n",
+ spi->regions[idx].id, spi->regions[idx].name, from, len);
+
+ if (idx >= spi->nregions) {
+ dev_err(&mtd->dev, "out of ragnge");
+ return -ERANGE;
+ }
+
+ from -= spi->regions[idx].offset;
+ region = spi->regions[idx].id;
+ if (len > spi->regions[idx].size - from)
+ len = spi->regions[idx].size - from;
+
+ mutex_lock(&spi->lock);
+
+ ret = spi_read(spi, region, from, len, buf);
+ if (ret < 0) {
+ dev_dbg(&mtd->dev, "read failed with %zd\n", ret);
+ mutex_unlock(&spi->lock);
+ return ret;
+ }
+
+ *retlen = ret;
+
+ mutex_unlock(&spi->lock);
return 0;
}
static int i915_spi_write(struct mtd_info *mtd, loff_t to, size_t len,
size_t *retlen, const u_char *buf)
{
- dev_err(&mtd->dev, "writing %lld %zd\n", to, len);
+ struct i915_spi *spi;
+ ssize_t ret;
+ unsigned int idx;
+ u8 region;
+
+ if (!mtd)
+ return -EINVAL;
+
+ spi = mtd->priv;
+ if (WARN_ON(!spi))
+ return -EINVAL;
+
+ idx = spi_get_region(spi, to);
+
+ dev_dbg(&mtd->dev, "writing region[%d] %s to %lld len %zd\n",
+ spi->regions[idx].id, spi->regions[idx].name, to, len);
+
+ if (idx >= spi->nregions) {
+ dev_err(&mtd->dev, "out of range");
+ return -ERANGE;
+ }
+
+ to -= spi->regions[idx].offset;
+ region = spi->regions[idx].id;
+ if (len > spi->regions[idx].size - to)
+ len = spi->regions[idx].size - to;
+
+ mutex_lock(&spi->lock);
+
+ ret = spi_write(spi, region, to, len, buf);
+ if (ret < 0) {
+ dev_dbg(&mtd->dev, "write failed with %zd\n", ret);
+ mutex_unlock(&spi->lock);
+ return ret;
+ }
+
+ *retlen = ret;
+ mutex_unlock(&spi->lock);
return 0;
}
--
2.34.1
______________________________________________________
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http://lists.infradead.org/mailman/listinfo/linux-mtd/
^ permalink raw reply related
* [PATCH 08/10] drm/i915/spi: align 64bit read and write
From: Alexander Usyskin @ 2023-09-10 12:39 UTC (permalink / raw)
To: Miquel Raynal, Richard Weinberger, Vignesh Raghavendra,
Jani Nikula, Joonas Lahtinen, Rodrigo Vivi
Cc: Alexander Usyskin, Vitaly Lubart, linux-mtd, intel-gfx
In-Reply-To: <20230910123949.1251964-1-alexander.usyskin@intel.com>
GSC SPI HW errors on quad access overlapping 1K border.
Align 64bit read and write to avoid readq/writeq over 1K border.
Signed-off-by: Alexander Usyskin <alexander.usyskin@intel.com>
---
drivers/gpu/drm/i915/spi/intel_spi_drv.c | 36 ++++++++++++++++++++++++
1 file changed, 36 insertions(+)
diff --git a/drivers/gpu/drm/i915/spi/intel_spi_drv.c b/drivers/gpu/drm/i915/spi/intel_spi_drv.c
index 39369a0c64a0..22b804ebadc0 100644
--- a/drivers/gpu/drm/i915/spi/intel_spi_drv.c
+++ b/drivers/gpu/drm/i915/spi/intel_spi_drv.c
@@ -14,6 +14,7 @@
#include <linux/io-64-nonatomic-lo-hi.h>
#include <linux/delay.h>
#include "spi/intel_spi.h"
+#include "i915_reg_defs.h"
#include <linux/mtd/mtd.h>
#include <linux/mtd/partitions.h>
@@ -232,6 +233,24 @@ static ssize_t spi_write(struct i915_spi *spi, u8 region,
len_s -= to_shift;
}
+ if (!IS_ALIGNED(to, sizeof(u64)) &&
+ ((to ^ (to + len_s)) & REG_GENMASK(31, 10))) {
+ /*
+ * Workaround reads/writes across 1k-aligned addresses
+ * (start u32 before 1k, end u32 after)
+ * as this fails on hardware.
+ */
+ u32 data;
+
+ memcpy(&data, &buf[0], sizeof(u32));
+ spi_write32(spi, to, data);
+ if (spi_error(spi))
+ return -EIO;
+ buf += sizeof(u32);
+ to += sizeof(u32);
+ len_s -= sizeof(u32);
+ }
+
len8 = ALIGN_DOWN(len_s, sizeof(u64));
for (i = 0; i < len8; i += sizeof(u64)) {
u64 data;
@@ -290,6 +309,23 @@ static ssize_t spi_read(struct i915_spi *spi, u8 region,
from += from_shift;
}
+ if (!IS_ALIGNED(from, sizeof(u64)) &&
+ ((from ^ (from + len_s)) & REG_GENMASK(31, 10))) {
+ /*
+ * Workaround reads/writes across 1k-aligned addresses
+ * (start u32 before 1k, end u32 after)
+ * as this fails on hardware.
+ */
+ u32 data = spi_read32(spi, from);
+
+ if (spi_error(spi))
+ return -EIO;
+ memcpy(&buf[0], &data, sizeof(data));
+ len_s -= sizeof(u32);
+ buf += sizeof(u32);
+ from += sizeof(u32);
+ }
+
len8 = ALIGN_DOWN(len_s, sizeof(u64));
for (i = 0; i < len8; i += sizeof(u64)) {
u64 data = spi_read64(spi, from + i);
--
2.34.1
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^ permalink raw reply related
* [PATCH 09/10] drm/i915/spi: wake card on operations
From: Alexander Usyskin @ 2023-09-10 12:39 UTC (permalink / raw)
To: Miquel Raynal, Richard Weinberger, Vignesh Raghavendra,
Jani Nikula, Joonas Lahtinen, Rodrigo Vivi
Cc: Alexander Usyskin, Vitaly Lubart, linux-mtd, intel-gfx,
Lucas De Marchi
In-Reply-To: <20230910123949.1251964-1-alexander.usyskin@intel.com>
Enable runtime PM in spi driver to notify i915 that
whole card should be kept awake while spi operations are
performed through this driver.
CC: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Alexander Usyskin <alexander.usyskin@intel.com>
---
drivers/gpu/drm/i915/spi/intel_spi_drv.c | 44 ++++++++++++++++++++++++
1 file changed, 44 insertions(+)
diff --git a/drivers/gpu/drm/i915/spi/intel_spi_drv.c b/drivers/gpu/drm/i915/spi/intel_spi_drv.c
index 22b804ebadc0..6b514b137fd0 100644
--- a/drivers/gpu/drm/i915/spi/intel_spi_drv.c
+++ b/drivers/gpu/drm/i915/spi/intel_spi_drv.c
@@ -13,12 +13,15 @@
#include <linux/sizes.h>
#include <linux/io-64-nonatomic-lo-hi.h>
#include <linux/delay.h>
+#include <linux/pm_runtime.h>
#include "spi/intel_spi.h"
#include "i915_reg_defs.h"
#include <linux/mtd/mtd.h>
#include <linux/mtd/partitions.h>
+#define I915_SPI_RPM_TIMEOUT 500
+
struct i915_spi {
struct kref refcnt;
struct mtd_info mtd;
@@ -473,6 +476,12 @@ static int i915_spi_erase(struct mtd_info *mtd, struct erase_info *info)
total_len = info->len;
addr = info->addr;
+ ret = pm_runtime_resume_and_get(mtd->dev.parent);
+ if (ret < 0) {
+ dev_err(&mtd->dev, "rpm: get failed %d\n", ret);
+ return ret;
+ }
+
mutex_lock(&spi->lock);
while (total_len > 0) {
@@ -514,6 +523,8 @@ static int i915_spi_erase(struct mtd_info *mtd, struct erase_info *info)
out:
mutex_unlock(&spi->lock);
+ pm_runtime_mark_last_busy(mtd->dev.parent);
+ pm_runtime_put_autosuspend(mtd->dev.parent);
return ret;
}
@@ -547,6 +558,12 @@ static int i915_spi_read(struct mtd_info *mtd, loff_t from, size_t len,
if (len > spi->regions[idx].size - from)
len = spi->regions[idx].size - from;
+ ret = pm_runtime_resume_and_get(mtd->dev.parent);
+ if (ret < 0) {
+ dev_err(&mtd->dev, "rpm: get failed %zd\n", ret);
+ return ret;
+ }
+
mutex_lock(&spi->lock);
ret = spi_read(spi, region, from, len, buf);
@@ -559,6 +576,8 @@ static int i915_spi_read(struct mtd_info *mtd, loff_t from, size_t len,
*retlen = ret;
mutex_unlock(&spi->lock);
+ pm_runtime_mark_last_busy(mtd->dev.parent);
+ pm_runtime_put_autosuspend(mtd->dev.parent);
return 0;
}
@@ -592,6 +611,12 @@ static int i915_spi_write(struct mtd_info *mtd, loff_t to, size_t len,
if (len > spi->regions[idx].size - to)
len = spi->regions[idx].size - to;
+ ret = pm_runtime_resume_and_get(mtd->dev.parent);
+ if (ret < 0) {
+ dev_err(&mtd->dev, "rpm: get failed %zd\n", ret);
+ return ret;
+ }
+
mutex_lock(&spi->lock);
ret = spi_write(spi, region, to, len, buf);
@@ -604,6 +629,8 @@ static int i915_spi_write(struct mtd_info *mtd, loff_t to, size_t len,
*retlen = ret;
mutex_unlock(&spi->lock);
+ pm_runtime_mark_last_busy(mtd->dev.parent);
+ pm_runtime_put_autosuspend(mtd->dev.parent);
return 0;
}
@@ -749,6 +776,17 @@ static int i915_spi_probe(struct auxiliary_device *aux_dev,
}
}
+ pm_runtime_enable(device);
+
+ pm_runtime_set_autosuspend_delay(device, I915_SPI_RPM_TIMEOUT);
+ pm_runtime_use_autosuspend(device);
+
+ ret = pm_runtime_resume_and_get(device);
+ if (ret < 0) {
+ dev_err(device, "rpm: get failed %d\n", ret);
+ goto err_norpm;
+ }
+
spi->base = devm_ioremap_resource(device, &ispi->bar);
if (IS_ERR(spi->base)) {
dev_err(device, "mmio not mapped\n");
@@ -773,9 +811,13 @@ static int i915_spi_probe(struct auxiliary_device *aux_dev,
dev_dbg(device, "i915-spi is bound\n");
+ pm_runtime_put(device);
return 0;
err:
+ pm_runtime_put(device);
+err_norpm:
+ pm_runtime_disable(device);
kref_put(&spi->refcnt, i915_spi_release);
return ret;
}
@@ -787,6 +829,8 @@ static void i915_spi_remove(struct auxiliary_device *aux_dev)
if (!spi)
return;
+ pm_runtime_disable(&aux_dev->dev);
+
mtd_device_unregister(&spi->mtd);
dev_set_drvdata(&aux_dev->dev, NULL);
--
2.34.1
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