From: keith.busch@intel.com (Keith Busch)
Subject: RDY bit clarification
Date: Sun, 14 Jan 2018 19:12:54 -0700 [thread overview]
Message-ID: <20180115021254.GF13580@localhost.localdomain> (raw)
In-Reply-To: <CADLzrv_83V8i_bSeUbKA2FDf0Gtm4NCEa7fP-=vxVDk9=qBs8A@mail.gmail.com>
On Mon, Jan 15, 2018@07:36:27AM +0530, muthu crazy wrote:
> My concern is Reading RDY bit will trigger a MemRD PCIe transcation
> which will add a delay for every command.
> So it will affect the overall performance.
Maybe I misunderstood what you're referring to. Are you looking at
nvmet_check_ctrl_status? The controller status is implemented in
software there and doesn't do MMIO to read it.
prev parent reply other threads:[~2018-01-15 2:12 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-01-14 3:56 RDY bit clarification muthu crazy
2018-01-15 1:57 ` Keith Busch
2018-01-15 2:06 ` muthu crazy
2018-01-15 2:12 ` Keith Busch [this message]
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