Re: [RFC v2 PATCH 03/10] net: ti: prueth: Adds PRUETH HW and SW configuration

[Basharath Hussain Khaja <basharath@couthit.com>]

> On Fri, Jan 24, 2025 at 05:53:46PM +0530, Basharath Hussain Khaja wrote:
>> From: Roger Quadros <rogerq@ti.com>
>> 
>> Updates for MII_RT hardware peripheral configuration such as RX and TX
>> configuration for PRU0 and PRU1, frame sizes, and MUX config.
>> 
>> Updates for PRU-ICSS firmware register configuration and DRAM, SRAM and
>> OCMC memory initialization, which will be used in the runtime for packet
>> reception and transmission.
>> 
>> DUAL-EMAC memory allocation for software queues and its supporting
>> components such as the buffer descriptors and queue discriptors. These
> 
> nit: descriptors
> 

Sure. We will change in the next version.

>> software queues are placed in OCMC memory and are shared with CPU by
>> PRU-ICSS for packet receive and transmit.
>> 
>> All declarations and macros are being used from common header file
>> for various protocols.
>> 
>> Signed-off-by: Roger Quadros <rogerq@ti.com>
>> Signed-off-by: Andrew F. Davis <afd@ti.com>
>> Signed-off-by: Parvathi Pudi <parvathi@couthit.com>
>> Signed-off-by: Basharath Hussain Khaja <basharath@couthit.com>
> 
> ...
> 
>> diff --git a/drivers/net/ethernet/ti/icssm/icssm_prueth.c
>> b/drivers/net/ethernet/ti/icssm/icssm_prueth.c
> 
> ...
> 
>> +static void icssm_prueth_mii_init(struct prueth *prueth)
>> +{
>> +	struct regmap *mii_rt;
>> +	u32 rxcfg_reg, rxcfg;
>> +	u32 txcfg_reg, txcfg;
>> +
>> +	mii_rt = prueth->mii_rt;
>> +
>> +	rxcfg = PRUSS_MII_RT_RXCFG_RX_ENABLE |
>> +		PRUSS_MII_RT_RXCFG_RX_DATA_RDY_MODE_DIS |
>> +		PRUSS_MII_RT_RXCFG_RX_L2_EN |
>> +		PRUSS_MII_RT_RXCFG_RX_CUT_PREAMBLE |
>> +		PRUSS_MII_RT_RXCFG_RX_L2_EOF_SCLR_DIS;
>> +
>> +	/* Configuration of Port 0 Rx */
>> +	rxcfg_reg = PRUSS_MII_RT_RXCFG0;
>> +
>> +	regmap_write(mii_rt, rxcfg_reg, rxcfg);
>> +
>> +	/* Configuration of Port 1 Rx */
>> +	rxcfg_reg = PRUSS_MII_RT_RXCFG1;
>> +
>> +	rxcfg |= PRUSS_MII_RT_RXCFG_RX_MUX_SEL;
>> +
>> +	regmap_write(mii_rt, rxcfg_reg, rxcfg);
>> +
>> +	txcfg = PRUSS_MII_RT_TXCFG_TX_ENABLE |
>> +		PRUSS_MII_RT_TXCFG_TX_AUTO_PREAMBLE |
>> +		PRUSS_MII_RT_TXCFG_TX_32_MODE_EN |
>> +		(TX_START_DELAY << PRUSS_MII_RT_TXCFG_TX_START_DELAY_SHIFT) |
>> +		(TX_CLK_DELAY_100M << PRUSS_MII_RT_TXCFG_TX_CLK_DELAY_SHIFT);
>> +
>> +	/* Configuration of Port 0 Tx */
>> +	txcfg_reg = PRUSS_MII_RT_TXCFG0;
>> +
>> +	regmap_write(mii_rt, txcfg_reg, txcfg);
>> +
>> +	txcfg	|= PRUSS_MII_RT_TXCFG_TX_MUX_SEL;
> 
> nit: a space seems more appropriate than a tab before '|='
> 

Sure. We will remove extra spaces in the next version.

>> +
>> +	/* Configuration of Port 1 Tx */
>> +	txcfg_reg = PRUSS_MII_RT_TXCFG1;
>> +
>> +	regmap_write(mii_rt, txcfg_reg, txcfg);
>> +
>> +	txcfg_reg = PRUSS_MII_RT_RX_FRMS0;
>> +
>> +	/* Min frame length should be set to 64 to allow receive of standard
>> +	 * Ethernet frames such as PTP, LLDP that will not have the tag/rct.
>> +	 * Actual size written to register is size - 1 per TRM. This also
>> +	 * includes CRC/FCS.
>> +	 */
>> +	txcfg = (((PRUSS_MII_RT_RX_FRMS_MIN_FRM - 1) <<
>> +			PRUSS_MII_RT_RX_FRMS_MIN_FRM_SHIFT) &
>> +			PRUSS_MII_RT_RX_FRMS_MIN_FRM_MASK);
>> +
>> +	/* For EMAC, set Max frame size to 1528 i.e size with VLAN.
>> +	 * Actual size written to register is size - 1 as per TRM.
>> +	 * Since driver support run time change of protocol, driver
>> +	 * must overwrite the values based on Ethernet type.
>> +	 */
>> +	txcfg |= (((PRUSS_MII_RT_RX_FRMS_MAX_SUPPORT_EMAC - 1) <<
>> +			   PRUSS_MII_RT_RX_FRMS_MAX_FRM_SHIFT)	&
>> +			   PRUSS_MII_RT_RX_FRMS_MAX_FRM_MASK);
>> +
>> +	regmap_write(mii_rt, txcfg_reg, txcfg);
>> +
>> +	txcfg_reg = PRUSS_MII_RT_RX_FRMS1;
>> +
>> +	regmap_write(mii_rt, txcfg_reg, txcfg);
>> +}
> 
> ...
> 
>> @@ -377,6 +705,70 @@ static int icssm_prueth_probe(struct platform_device *pdev)
>>  		}
>>  	}
>>  
>> +	pruss = pruss_get(prueth->pru0 ? prueth->pru0 : prueth->pru1);
>> +	if (IS_ERR(pruss)) {
>> +		ret = PTR_ERR(pruss);
>> +		dev_err(dev, "unable to get pruss handle\n");
>> +		goto put_pru;
>> +	}
>> +	prueth->pruss = pruss;
>> +
>> +	ret = pruss_cfg_ocp_master_ports(prueth->pruss, 1);
>> +	if (ret) {
>> +		dev_err(dev, "couldn't enabled ocp master port: %d\n", ret);
>> +		goto put_pruss;
>> +	}
> 
> FTR, I applied this patch set on top of the patch at the link below
> so that pruss_cfg_ocp_master_ports() is present.
> 
> - [PATCH v2 1/1] soc: ti: PRUSS OCP configuration
>  https://lore.kernel.org/all/20250108125937.10604-2-basharath@couthit.com/
> 
>  ...
> 
>> diff --git a/drivers/net/ethernet/ti/icssm/icssm_prueth.h
>> b/drivers/net/ethernet/ti/icssm/icssm_prueth.h
> 
> ...
> 
>> +/**
>> + * struct prueth_queue - Information about a queue in memory
> 
> struct prueth_queue_info
> 

We will address this in the next version.

>> + * @buffer_offset: buffer offset in OCMC RAM
>> + * @queue_desc_offset: queue descriptor offset in Shared RAM
>> + * @buffer_desc_offset: buffer descriptors offset in Shared RAM
>> + * @buffer_desc_end: end address of buffer descriptors in Shared RAM
>> + */
>> +struct prueth_queue_info {
>> +	u16 buffer_offset;
>> +	u16 queue_desc_offset;
>> +	u16 buffer_desc_offset;
>> +	u16 buffer_desc_end;
>> +} __packed;
> 
> ...

Thanks & Best Regards,
Basharath