From: Marc Zyngier <marc.zyngier@arm.com>
To: Benoit Cousson <bcousson@baylibre.com>,
Tony Lindgren <tony@atomide.com>, Nishanth Menon <nm@ti.com>,
Santosh Shilimkar <ssantosh@kernel.org>,
Jason Cooper <jason@lakedaemon.net>,
Thomas Gleixner <tglx@linutronix.de>,
Rob Herring <robh+dt@kernel.org>,
Mark Rutland <mark.rutland@arm.com>
Cc: linux-arm-kernel@lists.infradead.org, linux-omap@vger.kernel.org
Subject: [PATCH v6 3/7] DT: update ti,irq-crossbar binding
Date: Wed, 11 Mar 2015 15:43:45 +0000 [thread overview]
Message-ID: <1426088629-15377-4-git-send-email-marc.zyngier@arm.com> (raw)
In-Reply-To: <1426088629-15377-1-git-send-email-marc.zyngier@arm.com>
Make it look like a real interrupt controller.
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
---
.../devicetree/bindings/arm/omap/crossbar.txt | 18 +++++-------------
1 file changed, 5 insertions(+), 13 deletions(-)
diff --git a/Documentation/devicetree/bindings/arm/omap/crossbar.txt b/Documentation/devicetree/bindings/arm/omap/crossbar.txt
index 4139db3..a9b28d7 100644
--- a/Documentation/devicetree/bindings/arm/omap/crossbar.txt
+++ b/Documentation/devicetree/bindings/arm/omap/crossbar.txt
@@ -9,7 +9,9 @@ inputs.
Required properties:
- compatible : Should be "ti,irq-crossbar"
- reg: Base address and the size of the crossbar registers.
-- ti,max-irqs: Total number of irqs available at the interrupt controller.
+- interrupt-controller: indicates that this block is an interrupt controller.
+- interrupt-parent: the interrupt controller this block is connected to.
+- ti,max-irqs: Total number of irqs available at the parent interrupt controller.
- ti,max-crossbar-sources: Maximum number of crossbar sources that can be routed.
- ti,reg-size: Size of a individual register in bytes. Every individual
register is assumed to be of same size. Valid sizes are 1, 2, 4.
@@ -27,13 +29,13 @@ Optional properties:
when the interrupt controller irq is unused (when not provided, default is 0)
Examples:
- crossbar_mpu: @4a020000 {
+ crossbar_mpu: crossbar@4a002a48 {
compatible = "ti,irq-crossbar";
reg = <0x4a002a48 0x130>;
ti,max-irqs = <160>;
ti,max-crossbar-sources = <400>;
ti,reg-size = <2>;
- ti,irqs-reserved = <0 1 2 3 5 6 131 132 139 140>;
+ ti,irqs-reserved = <0 1 2 3 5 6 131 132>;
ti,irqs-skip = <10 133 139 140>;
};
@@ -44,10 +46,6 @@ Documentation/devicetree/bindings/arm/gic.txt for further details.
An interrupt consumer on an SoC using crossbar will use:
interrupts = <GIC_SPI request_number interrupt_level>
-When the request number is between 0 to that described by
-"ti,max-crossbar-sources", it is assumed to be a crossbar mapping. If the
-request_number is greater than "ti,max-crossbar-sources", then it is mapped as a
-quirky hardware mapping direct to GIC.
Example:
device_x@0x4a023000 {
@@ -55,9 +53,3 @@ Example:
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
...
};
-
- device_y@0x4a033000 {
- /* Direct mapped GIC SPI 1 used */
- interrupts = <GIC_SPI DIRECT_IRQ(1) IRQ_TYPE_LEVEL_HIGH>;
- ...
- };
--
2.1.4
next prev parent reply other threads:[~2015-03-11 15:44 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-03-11 15:43 [PATCH v6 0/7] irqchip: Move OMAP{4,5}/DRA7 to use stacked domains Marc Zyngier
2015-03-11 15:43 ` [PATCH v6 1/7] genirq: Add irqchip_set_wake_parent Marc Zyngier
2015-03-11 15:43 ` [PATCH v6 2/7] irqchip: crossbar: convert dra7 crossbar to stacked domains Marc Zyngier
2015-03-11 15:43 ` Marc Zyngier [this message]
2015-03-11 15:43 ` [PATCH v6 4/7] irqchip: GIC: get rid of routable domain Marc Zyngier
2015-03-11 15:43 ` [PATCH v6 5/7] DT: arm,gic: kill arm,routable-irqs Marc Zyngier
2015-03-11 15:43 ` [PATCH v6 6/7] DT: omap4/5: add binding for the wake-up generator Marc Zyngier
2015-03-11 15:43 ` [PATCH v6 7/7] ARM: omap: convert wakeupgen to stacked domains Marc Zyngier
2015-03-13 15:40 ` [PATCH v6 0/7] irqchip: Move OMAP{4,5}/DRA7 to use " Tony Lindgren
2015-03-13 17:25 ` Jason Cooper
2015-03-13 17:38 ` Tony Lindgren
2015-03-13 17:49 ` Marc Zyngier
2015-03-15 1:22 ` Jason Cooper
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