Re: [PATCHv7 3/7] omap3: voltage: fix channel configuration

[Kevin Hilman <khilman@ti.com>]

Tero Kristo <t-kristo@ti.com> writes:

> On Fri, 2011-12-02 at 15:55 -0800, Kevin Hilman wrote:
>> Tero Kristo <t-kristo@ti.com> writes:
>> 
>> > OMAP3 uses the default settings for VDD1 channel, otherwise the settings will
>> > overlap with VDD2 and attempting to modify VDD1 voltage will actually change
>> > VDD2 voltage.
>> >
>> > Signed-off-by: Tero Kristo <t-kristo@ti.com>
>> 
>> I've forgotten a bit how this was supposed to work (again), Can you
>> elaborate more on how this fails?
>
> There is a diagram in the OMAP TRM for setting the bits in this
> register, however the racen fix part appears to be needed only for
> omap4. I can drop this part of the fix from the series if you want for
> the next version, alternatively I can split this patch into two.

A separate patch, with a descriptive changelog would be preferred.

> The idea for this part of the fix is anyway that the channel
> configuration is more complex in omap4, we define volt_reg and cmd_reg
> addresses for each omap4_X_pmic, however we only want to enable racen
> bit only if cmd and volt register addresses are the same. 

This part still doesn't make sense to me.

If the volt register address (RA_VOL in OMAP4 terms) and command
register address (RA_CMD) are the same, then RACEN shouldn't matter,
since either way the commands go the same address.   

My understanding of RACEN is that it is only for the case where RA_VOL
and RA_CMD are different, so you can select between them.

The current code assumes that if you pass in command register address
you plan to use it.  If it isn't being used (RACEN == 0) then the PMIC
setup should probably not pass in a separate command register address.

What am I missing (or mis-reading in the TRM) here?

Kevin