Re: [parisc-linux] ccio-dma 64bit debug_init info

Re: [parisc-linux] ccio-dma 64bit debug_init info

[Joel Soete]

[-- Attachment #1: Type: text/plain, Size: 18931 bytes --]

Hello Grant,

Sorry for delay but I encountered some config pb with my isp imp config :-(

>
> On Tue, May 17, 2005 at 06:29:18PM +0200, Joel Soete wrote:
> > > > ccio-dma.c: failed to claim CCIO bus address space (ffffffff00000000,ffffffffffffffff)
> ...
> > > It would be interesting to know why it's asking for that range.
> > > Where are the values of that range coming from?
>
> > 32bit kernel:
> ...
> > ccio_init_resource(res=10712c68, name=GSC Bus [8/], ioaddr=fff88078)
> > ccio_init_resource() res->start f1000000
> > ccio_init_resource() res->end f17fffff
> > ccio_init_resource() res->end + 1  f1800000
> > ccio_init_resource() claimed CCIO bus address space (f1000000, f17fffff)
> > ccio_init_resource(res=10712c84, name=GSC Bus [8/], ioaddr=fff88060)
> > ccio_init_resource() res->start fc000000
> > ccio_init_resource() res->end fff7ffff
> > ccio_init_resource() res->end + 1  fff80000
> > ccio_init_resource() claimed CCIO bus address space (fc000000, fff7ffff)
> ...
>
> Ah...I forgot that U2/Uturn have two sets of range registers.
> One per GSC bus....
>
No pb ;-)

> BTW, PDC sets all of this address stuff up AFAIK.
>
Any idea where is the doc about this feature?

> ...
> > ccio_init_resource(res=1071245c, name=GSC Bus [10/], ioaddr=fff8a078)
> > ccio_init_resource() res->start f1800000
> > ccio_init_resource() res->end f1ffffff
> > ccio_init_resource() res->end + 1  f2000000
> > ccio_init_resource() claimed CCIO bus address space (f1800000, f1ffffff)
> > ccio_init_resource(res=10712478, name=GSC Bus [10/], ioaddr=fff8a060)
> > ccio_init_resource() res->start 00000000
> > ccio_init_resource() res->end ffffffff
> > ccio_init_resource() res->end + 1  00000000
> > Lasi version 0 at 0xffd00000 found.
> > ...
>
> This last one seems to be disabled.
Ah ok (any idea why? hw failure?)

> That's what this code in ccio_init_resource() is testing for:
> 	if (res->end + 1 == res->start)
>                 return;
>
> /me puts on his fortune teller hat and looks in his crystal ball:
> 	"Joel will be submitting a patch shortly...You must add a comment
> 	explaining WTF this test is doing..."
>
Ok ;-)

>
> > 64bit kernel:
> ...
> > ccio_init_resource(res=00000000109e3858, name=GSC Bus [8/], ioaddr=fffffffffff88078)
> > ccio_init_resource() res->start fffffffff1000000
> > ccio_init_resource() res->end fffffffff17fffff
> > ccio_init_resource() res->end + 1  fffffffff1800000
> > ccio_init_resource() claimed CCIO bus address space (fffffffff1000000,
> fffffffff17fffff)
> > ccio_init_resource(res=00000000109e3890, name=GSC Bus [8/], ioaddr=fffffffffff88060)
> > ccio_init_resource() res->start fffffffffc000000
> > ccio_init_resource() res->end fffffffffff7ffff
> > ccio_init_resource() res->end + 1  fffffffffff80000
> > ccio_init_resource() claimed CCIO bus address space (fffffffffc000000,
> fffffffffff7ffff)
>
> No problem with the first one.
>
(as far as i understand, yes )

> ...
> > ccio_init_resource(res=00000000109e5858, name=GSC Bus [10/], ioaddr=fffffffffff8a078)
> > ccio_init_resource() res->start fffffffff1800000
> > ccio_init_resource() res->end fffffffff1ffffff
> > ccio_init_resource() res->end + 1  fffffffff2000000
> > ccio_init_resource() claimed CCIO bus address space (fffffffff1800000,
> fffffffff1ffffff)
> > ccio_init_resource(res=00000000109e5890, name=GSC Bus [10/], ioaddr=fffffffffff8a060)
> > ccio_init_resource() res->start ffffffff00000000
> > ccio_init_resource() res->end ffffffffffffffff
> > ccio_init_resource() res->end + 1  0000000000000000
>
> This fails because io_io_low/high registers in reality are only 16 bits.
> The upper 16 bits are hardcoded to 1's.
> The conversion of res->start to 64-bit is wrong for this one case:
> 	res->start = (unsigned long)(signed) __raw_readl(ioaddr) << 16;
>
> __raw_readl(ioaddr) returns 0xffff0000.
> 0xffff0000 << 16 should be 0 but it's not since this is 64-bit.
> That line should read something like:
> 	res->start = (unsigned long) ((signed) __raw_readl(ioaddr) << 16);
>
cool ;-)

> And please add a comment here too that parenthesis *do* matter.
> Then it should fail the same test that I point out above....
>
> > ccio_init_resource() failed to claim CCIO bus address space (ffffffff00000000,
> > ffffffffffffffff)
>
> ...and we wouldn't even try to acquire this range.
>
> > ccio_init_resource() claimed CCIO bus address space (ffffffff00000000,
> ffffffffffffffff)
> > Lasi version 0 at 0xffffffffffd00000 found.
> >
> > even thought I have no doc to now what would means:
> >         res->start = (unsigned long)(signed) READ_U32(ioaddr) << 16;
(==
> > 0x0 in 32bits)
> >         res->end = (unsigned long)(signed) (READ_U32(ioaddr + 4) << 16)
> -
> > 1; (== 0xffffffff in 32bits too)
> >
> > but seems that test:
> >         if (res->end + 1 == res->start)
> > is a stuff which not love 64bit :-(
>
> You almost got it right.
>
so here is a first patch:
--- drivers/parisc/ccio-dma.c.orig      2005-05-20 08:47:17.000000000 +0200
+++ drivers/parisc/ccio-dma.c.orig1     2005-05-20 12:15:35.000000000 +0200
@@ -1328,13 +1328,12 @@
        ioc->pdir_base = (u64 *)__get_free_pages(GFP_KERNEL,
                                                 get_order(ioc->pdir_size));
        if(NULL == ioc->pdir_base) {
-               panic("%s:%s() could not allocate I/O Page Table\n", __FILE__,
-                     __FUNCTION__);
+               panic("%s() could not allocate I/O Page Table\n", __FUNCTION__);
        }
        memset(ioc->pdir_base, 0, ioc->pdir_size);

        BUG_ON((((unsigned long)ioc->pdir_base) & PAGE_MASK) != (unsigned
long)ioc->pdir_base);
-       DBG_INIT(" base %p", ioc->pdir_base);
+       DBG_INIT(" base %p\n", ioc->pdir_base);

        /* resource map size dictated by pdir_size */
        ioc->res_size = (ioc->pdir_size / sizeof(u64)) >> 3;
@@ -1343,8 +1342,7 @@
        ioc->res_map = (u8 *)__get_free_pages(GFP_KERNEL,
                                              get_order(ioc->res_size));
        if(NULL == ioc->res_map) {
-               panic("%s:%s() could not allocate resource map\n", __FILE__,
-                     __FUNCTION__);
+               panic("%s() could not allocate resource map\n", __FUNCTION__);
        }
        memset(ioc->res_map, 0, ioc->res_size);

@@ -1394,15 +1392,21 @@

        res->parent = NULL;
        res->flags = IORESOURCE_MEM;
-       res->start = (unsigned long)(signed) __raw_readl(ioaddr) << 16;
-       res->end = (unsigned long)(signed) (__raw_readl(ioaddr + 4) << 16)
- 1;
+       /*
+        * bracing ((signed) ...) are required for 64bit kernel
+        */
+       res->start = (unsigned long)((signed) READ_U32(ioaddr) << 16);
+       res->end = (unsigned long)((signed) (READ_U32(ioaddr + 4) << 16)
- 1);
        res->name = name;
+       /*
+        * Check if the set of range registers is disable
+        */
        if (res->end + 1 == res->start)
                return;
        result = request_resource(&iomem_resource, res);
        if (result < 0) {
-               printk(KERN_ERR "%s: failed to claim CCIO bus address space
(%08lx,%08lx)\n",
-                      __FILE__, res->start, res->end);
+               printk(KERN_ERR "%s() failed to claim CCIO bus address space
(%08lx,%08lx)\n",
+                       __FUNCTION__, res->start, res->end);
        }
 }
====<>====

Some additional stuff:
--- drivers/parisc/ccio-dma.c.orig      2005-05-20 08:47:17.000000000 +0200
+++ drivers/parisc/ccio-dma.c.orig1     2005-05-20 12:15:35.000000000 +0200
@@ -1328,13 +1328,12 @@
        ioc->pdir_base = (u64 *)__get_free_pages(GFP_KERNEL,
                                                 get_order(ioc->pdir_size));
        if(NULL == ioc->pdir_base) {
-               panic("%s:%s() could not allocate I/O Page Table\n", __FILE__,
-                     __FUNCTION__);
+               panic("%s() could not allocate I/O Page Table\n", __FUNCTION__);
        }
        memset(ioc->pdir_base, 0, ioc->pdir_size);

        BUG_ON((((unsigned long)ioc->pdir_base) & PAGE_MASK) != (unsigned
long)i
oc->pdir_base);
-       DBG_INIT(" base %p", ioc->pdir_base);
+       DBG_INIT(" base %p\n", ioc->pdir_base);

        /* resource map size dictated by pdir_size */
        ioc->res_size = (ioc->pdir_size / sizeof(u64)) >> 3;
@@ -1343,8 +1342,7 @@
        ioc->res_map = (u8 *)__get_free_pages(GFP_KERNEL,
                                              get_order(ioc->res_size));
        if(NULL == ioc->res_map) {
-               panic("%s:%s() could not allocate resource map\n", __FILE__,
-                     __FUNCTION__);
+               panic("%s() could not allocate resource map\n", __FUNCTION__);
        }
        memset(ioc->res_map, 0, ioc->res_size);

@@ -1394,15 +1392,21 @@

        res->parent = NULL;
        res->flags = IORESOURCE_MEM;
-       res->start = (unsigned long)(signed) __raw_readl(ioaddr) << 16;
-       res->end = (unsigned long)(signed) (__raw_readl(ioaddr + 4) << 16)
- 1;
+       /*
+        * bracing ((signed) ...) are required for 64bit kernel
+        */
+       res->start = (unsigned long)((signed) READ_U32(ioaddr) << 16);
+       res->end = (unsigned long)((signed) (READ_U32(ioaddr + 4) << 16)
- 1);
        res->name = name;
+       /*
+        * Check if the set of range registers is disable
+        */
        if (res->end + 1 == res->start)
                return;
        result = request_resource(&iomem_resource, res);
        if (result < 0) {
-               printk(KERN_ERR "%s: failed to claim CCIO bus address space
(%08
lx,%08lx)\n",
-                      __FILE__, res->start, res->end);
+               printk(KERN_ERR "%s() failed to claim CCIO bus address space
(%0
8lx,%08lx)\n",
+                       __FUNCTION__, res->start, res->end);
        }
 }

jso@iatst001:~/work$ more ccio-dma.c.diff
--- drivers/parisc/ccio-dma.c.orig      2005-05-20 08:47:17.000000000 +0200
+++ drivers/parisc/ccio-dma.c.orig1     2005-05-20 12:15:35.000000000 +0200
@@ -1328,13 +1328,12 @@
        ioc->pdir_base = (u64 *)__get_free_pages(GFP_KERNEL,
                                                 get_order(ioc->pdir_size));
        if(NULL == ioc->pdir_base) {
-               panic("%s:%s() could not allocate I/O Page Table\n", __FILE__,
-                     __FUNCTION__);
+               panic("%s() could not allocate I/O Page Table\n", __FUNCTION__);
        }
        memset(ioc->pdir_base, 0, ioc->pdir_size);

        BUG_ON((((unsigned long)ioc->pdir_base) & PAGE_MASK) != (unsigned
long)ioc->pdir_base);
-       DBG_INIT(" base %p", ioc->pdir_base);
+       DBG_INIT(" base %p\n", ioc->pdir_base);

        /* resource map size dictated by pdir_size */
        ioc->res_size = (ioc->pdir_size / sizeof(u64)) >> 3;
@@ -1343,8 +1342,7 @@
        ioc->res_map = (u8 *)__get_free_pages(GFP_KERNEL,
                                              get_order(ioc->res_size));
        if(NULL == ioc->res_map) {
-               panic("%s:%s() could not allocate resource map\n", __FILE__,
-                     __FUNCTION__);
+               panic("%s() could not allocate resource map\n", __FUNCTION__);
        }
        memset(ioc->res_map, 0, ioc->res_size);

@@ -1394,15 +1392,21 @@

        res->parent = NULL;
        res->flags = IORESOURCE_MEM;
-       res->start = (unsigned long)(signed) __raw_readl(ioaddr) << 16;
-       res->end = (unsigned long)(signed) (__raw_readl(ioaddr + 4) << 16)
- 1;
+       /*
+        * bracing ((signed) ...) are required for 64bit kernel
+        */
+       res->start = (unsigned long)((signed) READ_U32(ioaddr) << 16);
+       res->end = (unsigned long)((signed) (READ_U32(ioaddr + 4) << 16)
- 1);
        res->name = name;
+       /*
+        * Check if the set of range registers is disable
+        */
        if (res->end + 1 == res->start)
                return;
        result = request_resource(&iomem_resource, res);
        if (result < 0) {
-               printk(KERN_ERR "%s: failed to claim CCIO bus address space
(%08lx,%08lx)\n",
-                      __FILE__, res->start, res->end);
+               printk(KERN_ERR "%s() failed to claim CCIO bus address space
(%08lx,%08lx)\n",
+                       __FUNCTION__, res->start, res->end);
        }
 }

jso@iatst001:~/work$ vi ccio-dma.c.diff
jso@iatst001:~/work$ more ccio-dma.c.diff1
--- drivers/parisc/ccio-dma.c.orig1     2005-05-20 12:15:35.000000000 +0200
+++ drivers/parisc/ccio-dma.c   2005-05-20 12:14:50.000000000 +0200
@@ -387,8 +387,7 @@
                       __FILE__,  __FUNCTION__, pages_needed);
        }

-       panic("%s: %s() I/O MMU is out of mapping resources.\n", __FILE__,
-             __FUNCTION__);
+       panic("%s() I/O MMU is out of mapping resources.\n", __FUNCTION__);

 resource_found:

@@ -578,7 +577,7 @@
        ** WORD 0 - high order word
        */

-#ifdef __LP64__
+#ifdef CONFIG_64BIT
        /*
        ** get bits 12:15 of physical address
        ** shift bits 16:31 of physical address
@@ -589,7 +588,7 @@
        asm volatile ("depd  %1,35,4,%0" : "+r" (pa) : "r" (ci));
 #else
        pa = 0;
-#endif
+#endif /* CONFIG_64BIT */
        /*
        ** get CPU coherency index bits
        ** Grab virtual index [0:11]
@@ -1288,10 +1287,10 @@

        if (iova_space_size < (1 << (20 - PAGE_SHIFT))) {
                iova_space_size =  1 << (20 - PAGE_SHIFT);
-#ifdef __LP64__
+#ifdef CONFIG_64BIT
        } else if (iova_space_size > (1 << (30 - PAGE_SHIFT))) {
                iova_space_size =  1 << (30 - PAGE_SHIFT);
-#endif
+#endif /* CONFIG_64BIT */
        }

        /*
@@ -1487,15 +1486,15 @@
                return 0;

        if (!expand_ioc_area(parent, size, min, max, align)) {
-               __raw_writel(((parent->start)>>16) | 0xffff0000,
+               WRITE_U32(((parent->start)>>16) | 0xffff0000,
                             &ioc->ioc_regs->io_io_low);
-               __raw_writel(((parent->end)>>16) | 0xffff0000,
+               WRITE_U32(((parent->end)>>16) | 0xffff0000,
                             &ioc->ioc_regs->io_io_high);
        } else if (!expand_ioc_area(parent + 1, size, min, max, align)) {
                parent++;
-               __raw_writel(((parent->start)>>16) | 0xffff0000,
+               WRITE_U32(((parent->start)>>16) | 0xffff0000,
                             &ioc->ioc_regs->io_io_low_hv);
-               __raw_writel(((parent->end)>>16) | 0xffff0000,
+               WRITE_U32(((parent->end)>>16) | 0xffff0000,
                             &ioc->ioc_regs->io_io_high_hv);
        } else {
                return -EBUSY;
====<>====

and btw some stuff which could interesting sba:
--- drivers/parisc/sba_iommu.c.orig     2005-05-20 09:07:26.000000000 +0200
+++ drivers/parisc/sba_iommu.c  2005-05-20 09:33:23.000000000 +0200
@@ -91,7 +91,7 @@
 #define DBG_RES(x...)
 #endif

-#if defined(__LP64__) && !defined(CONFIG_PDC_NARROW)
+#if defined(CONFIG_64BIT) && !defined(CONFIG_PDC_NARROW)
 /* "low end" PA8800 machines use ZX1 chipset */
 #define ZX1_SUPPORT
 #endif
@@ -231,7 +231,7 @@
        spinlock_t      res_lock;
        unsigned int    res_bitshift;   /* from the LEFT! */
        unsigned int    res_size;       /* size of resource map in bytes
*/
-#if SBA_HINT_SUPPORT
+#ifdef SBA_HINT_SUPPORT
 /* FIXME : DMA HINTs not used */
        unsigned long   hint_mask_pdir; /* bits used for DMA hints */
        unsigned int    hint_shift_pdir;
@@ -294,7 +294,7 @@
 /* Looks nice and keeps the compiler happy */
 #define SBA_DEV(d) ((struct sba_device *) (d))

-#if SBA_AGP_SUPPORT
+#ifdef SBA_AGP_SUPPORT
 static int reserve_sba_gart = 1;
 #endif

@@ -314,7 +314,7 @@
 #define WRITE_REG32(val, addr) __raw_writel(cpu_to_le32(val), addr)
 #define WRITE_REG64(val, addr) __raw_writeq(cpu_to_le64(val), addr)

-#ifdef __LP64__
+#ifdef CONFIG_64BIT
 #define READ_REG(addr)         READ_REG64(addr)
 #define WRITE_REG(value, addr) WRITE_REG64(value, addr)
 #else
@@ -324,7 +324,7 @@

 #ifdef DEBUG_SBA_INIT

-/* NOTE: When __LP64__ isn't defined, READ_REG64() is two 32-bit reads */
+/* NOTE: When CONFIG_64BIT isn't defined, READ_REG64() is two 32-bit reads
*/

 /**
  * sba_dump_ranges - debugging only - print ranges assigned to this IOA
@@ -364,7 +364,7 @@
 #else
 #define sba_dump_ranges(x)
 #define sba_dump_tlb(x)
-#endif
+#endif /* DEBUG_SBA_INIT */


 #ifdef ASSERT_PDIR_SANITY
@@ -674,7 +674,7 @@
 *
 ***************************************************************/

-#if SBA_HINT_SUPPORT
+#ifdef SBA_HINT_SUPPORT
 #define SBA_DMA_HINT(ioc, val) ((val) << (ioc)->hint_shift_pdir)
 #endif

@@ -1245,8 +1245,10 @@
        unsigned long pdir_order = get_order(pdir_size);

        pdir_base = __get_free_pages(GFP_KERNEL, pdir_order);
-       if (NULL == (void *) pdir_base)
-               panic("sba_ioc_init() could not allocate I/O Page Table\n");
+       if (NULL == (void *) pdir_base) {
+               panic("%s() could not allocate I/O Page Table\n",
+                       __FUNCTION__);
+       }

        /* If this is not PA8700 (PCX-W2)
        **      OR newer than ver 2.2
@@ -1354,7 +1356,7 @@
        u32 iova_space_mask;
        u32 iova_space_size;
        int iov_order, tcnfg;
-#if SBA_AGP_SUPPORT
+#ifdef SBA_AGP_SUPPORT
        int agp_found = 0;
 #endif
        /*
@@ -1391,7 +1393,7 @@
        DBG_INIT("%s() pdir %p size %x\n",
                        __FUNCTION__, ioc->pdir_base, ioc->pdir_size);

-#if SBA_HINT_SUPPORT
+#ifdef SBA_HINT_SUPPORT
        ioc->hint_shift_pdir = iov_order + PAGE_SHIFT;
        ioc->hint_mask_pdir = ~(0x3 << (iov_order + PAGE_SHIFT));

@@ -1415,7 +1417,7 @@

        WRITE_REG(ioc->imask, ioc->ioc_hpa + IOC_IMASK);

-#ifdef __LP64__
+#ifdef CONFIG_64BIT
        /*
        ** Setting the upper bits makes checking for bypass addresses
        ** a little faster later on.
@@ -1448,7 +1450,7 @@
        */
        WRITE_REG(ioc->ibase | 31, ioc->ioc_hpa + IOC_PCOM);

-#if SBA_AGP_SUPPORT
+#ifdef SBA_AGP_SUPPORT
        /*
        ** If an AGP device is present, only use half of the IOV space
        ** for PCI DMA.  Unfortunately we can't know ahead of time
@@ -1528,7 +1530,7 @@
        DBG_INIT("%s() pdir %p size %x\n",
                        __FUNCTION__, ioc->pdir_base, pdir_size);

-#if SBA_HINT_SUPPORT
+#ifdef SBA_HINT_SUPPORT
        /* FIXME : DMA HINTs not used */
        ioc->hint_shift_pdir = iov_order + PAGE_SHIFT;
        ioc->hint_mask_pdir = ~(0x3 << (iov_order + PAGE_SHIFT));
====<>====
(Just get rid if you dislike)

Thanks,
    Joel




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Re: [parisc-linux] ccio-dma 64bit debug_init info

[Grant Grundler]

On Fri, May 20, 2005 at 12:42:05PM +0200, Joel Soete wrote:
> > BTW, PDC sets all of this address stuff up AFAIK.
>
> Any idea where is the doc about this feature?

Sorry, I only know this from experience, not a document.

> > This last one seems to be disabled.
> Ah ok (any idea why? hw failure?)

Because it's not needed?
i.e. no devices downstream

> so here is a first patch:

Does this patch work for you?
Which machine(s) did you test it on?

> --- drivers/parisc/ccio-dma.c.orig      2005-05-20 08:47:17.000000000 +0200
> +++ drivers/parisc/ccio-dma.c.orig1     2005-05-20 12:15:35.000000000 +0200
...
> -       res->start = (unsigned long)(signed) __raw_readl(ioaddr) << 16;
> -       res->end = (unsigned long)(signed) (__raw_readl(ioaddr + 4) << 16)
> - 1;
> +       /*
> +        * bracing ((signed) ...) are required for 64bit kernel

	* bracing ((signed) ...) are required for 64bit kernel because
	* we only want to sign extend the lower 16 bits. The upper 16-bits
	* of range registers are hardcoded to 0xffff.

...
> +       /*
> +        * Check if the set of range registers is disable

	* Check if this MMIO range is disable

...
> Some additional stuff:
> --- drivers/parisc/ccio-dma.c.orig      2005-05-20 08:47:17.000000000 +0200
> +++ drivers/parisc/ccio-dma.c.orig1     2005-05-20 12:15:35.000000000 +0200
> @@ -1328,13 +1328,12 @@

I'm ignoring this chunk because it looks identical to the
previous patch. Please re-submit additional changes seperately.
I'm ok with dropping __FILE__ usage.

> -#ifdef __LP64__
> +#ifdef CONFIG_64BIT

I'll replace __LP64__ with CONFIG_64BIT - don't need a patch for that.

> -               __raw_writel(((parent->end)>>16) | 0xffff0000,
> +               WRITE_U32(((parent->end)>>16) | 0xffff0000,
>                              &ioc->ioc_regs->io_io_high);

Please submit a seperate patch for these.

And if everything is working for you,
can you try with this change:
- #define CCIO_INLINE     /* inline */
+ #define CCIO_INLINE inline

I would expect some minor, measurable improvements in performance.


> and btw some stuff which could interesting sba:
> --- drivers/parisc/sba_iommu.c.orig     2005-05-20 09:07:26.000000000 +0200
> +++ drivers/parisc/sba_iommu.c  2005-05-20 09:33:23.000000000 +0200
> @@ -91,7 +91,7 @@
>  #define DBG_RES(x...)
>  #endif
> 
> -#if defined(__LP64__) && !defined(CONFIG_PDC_NARROW)
> +#if defined(CONFIG_64BIT) && !defined(CONFIG_PDC_NARROW)

Yeah, I can apply those as well.

thanks,
grant
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Re: [parisc-linux] ccio-dma 64bit debug_init info

[Grant Grundler]

On Sun, May 22, 2005 at 01:06:03PM +0000, Joel Soete wrote:
> linux-2.6.12-rc4-pa5-050522.tar               100%  207MB 881.1KB/s   04:00
...
> mmm the builtin nic of the c110 is only 10M/half duplex, I presume that's 
> why there was no improvement or may be another more relevant test?

Both actually.

If possible, connect the C110 with 100BT NIC to *any* other 100BT with
a cross-over cable or to switch. I think you need a card-mode DINO card
(EISA form factor) for C110 since it doesn't have PCI.
Then run pktgen (kernel psuedo-driver). This script needs some adjusting
but should get you started:
	http://iou.parisc-linux.org/ols2004/documents/pktgen-testing/pktgen-single

If you can plug in multiple 100BT (or gige NICs),
look at some of the other scripts in the same directory.

hth,
grant
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Re: [parisc-linux] ccio-dma 64bit debug_init info

[Joel Soete]

Hello James,
> 
> On Fri, 2005-05-20 at 19:16 +0200, Joel Soete wrote:
> > Btw I also have an external bootable disk narrow SE connected to the
s710
> > driver. Do you know if this one is 64bit capable?
> 
> The lasi700 driver works fine in a 64 bit kernel, yes.
> 
You have right I just reinstall an external disk on lasi700 (53c700) cont=
roler
and boot a 64bit kernel (with ncr53c8x as module) :-)

BUT it is horribly slow:
    o it takes about a 1.5 h to boot (about 5 min for its twin 32bit)
    o a ssh connection takes about a min too (only some seconds for 32bit=

kernel)

and fwiw top:
top - 13:49:13 up  1:02,  1 user,  load average: 1.98, 3.13, 3.64
Tasks:  39 total,   4 running,  35 sleeping,   0 stopped,   0 zombie
Cpu(s):  0.0% us,  0.0% sy,  0.0% ni, 100.0% id,  0.0% wa,  0.0% hi,  0.0=
%
si
Mem:    252696k total,    47148k used,   205548k free,     3192k buffers
Swap:   131928k total,        0k used,   131928k free,    27104k cached
[...]

just show an 100% idle system?

Another known issue for this kind of d model?

Any idea?

Thanks,
    Joel

btw: I read this strange messages when it init raid5
[snip]
md: linear personality registered as nr 1
md: raid0 personality registered as nr 2
md: raid1 personality registered as nr 3
md: raid5 personality registered as nr 4
raid5: measuring checksumming speed
   8regs     : -923425.-184 MB/sec
   8regs_prefetch: 1824022.112 MB/sec
   32regs    : 328350.816 MB/sec
   32regs_prefetch: -1188109.-184 MB/sec
raid5: using function: 8regs_prefetch (1824022.112 MB/sec)
md: md driver 0.90.1 MAX_MD_DEVS=3D256, MD_SB_DISKS=3D27
[snip]

while the 32bit showed me more relevant values:
md: linear personality registered as nr 1
md: raid0 personality registered as nr 2
md: raid1 personality registered as nr 3
md: raid5 personality registered as nr 4
raid5: measuring checksumming speed
   8regs     :   574.400 MB/sec
   8regs_prefetch:   387.600 MB/sec
   32regs    :   447.600 MB/sec
   32regs_prefetch:   345.200 MB/sec
raid5: using function: 8regs (574.400 MB/sec)
md: md driver 0.90.1 MAX_MD_DEVS=3D256, MD_SB_DISKS=3D27

obviously I remove also raid5 support but it doesn't help :-(



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Re: [parisc-linux] ccio-dma 64bit debug_init info

[Joel Soete]

Hello Grant,

>
> On Fri, May 13, 2005 at 07:50:05AM +0200, Joel Soete wrote:
> > Ah I thought (too quickly) that it could be the reason why:
> > ...
> > ccio-dma.c: failed to claim CCIO bus address space (ffffffff00000000,=
ffffffffffffffff)
>
> That's a completely different issue.
> It would be interesting to know why it's asking for that range.
> Where are the values of that range coming from?
> (ie what is the origin of ffffffff00000000 value)
>
Here are more DBG_INIT() :-)
32bit kernel:
...
Found devices:
1. U2-IOA BC Runway Port at 0xfff88000 [8] { 12, 0xf, 0x580, 0x0000b }
2. UL 550 Lasi Core BA at 0xffd00000 [8/16] { 11, 0x0, 0x02f, 0x00081 },
 additional addresses: 0xffd0c000 0xffc00000
3. UL 550 Lasi Core RS-232 at 0xffd05000 [8/16/4] { 10, 0x0, 0x02f, 0x000=
8c
}
4. UL 550 Core SCSI at 0xffd06000 [8/16/5] { 10, 0x0, 0x02f, 0x00082 }
5. UL 350 Core LAN (802.3) at 0xffd07000 [8/16/6] { 10, 0x0, 0x02f, 0x000=
8a
}
6. UL 550 Core Centronics at 0xffd02000 [8/16/0] { 10, 0x0, 0x02f, 0x0007=
4
},  additional addresses: 0xffd01000 0xffd03000
7. UL 550 Core PS/2 Port at 0xffd08000 [8/16/7] { 10, 0x0, 0x02f, 0x00084=

}
8. UL 550 Core PS/2 Port at 0xffd08100 [8/16/8] { 10, 0x0, 0x02f, 0x00084=

}
9. UL 550 Core Wax BA at 0xffe00000 [8/20] { 11, 0x0, 0x031, 0x0008e }
10. UL 550 Wax EISA BA at 0xfc000000 [8/20/5] { 11, 0x0, 0x031, 0x00090 }=
,
 additional addresses: 0xffc88000
11. UL 550 Wax Core RS-232 at 0xffe02000 [8/20/2] { 10, 0x0, 0x031, 0x000=
8c
}
12. Bluefish Add-on FW-SCSI at 0xf1004000 [8/4] { 4, 0x1, 0x013, 0x00089
}
13. Bluefish Add-on FW-SCSI at 0xf1008000 [8/8] { 4, 0x1, 0x013, 0x00089
}
14. Bluefish Add-on FW-SCSI at 0xf100c000 [8/12] { 4, 0x1, 0x013, 0x00089=

}
15. U2-IOA BC GSC+ Port at 0xf103f000 [8/63] { 7, 0x1, 0x501, 0x0000c }
16. U2-IOA BC Runway Port at 0xfff8a000 [10] { 12, 0xf, 0x580, 0x0000b }
17. U2-IOA BC GSC+ Port at 0xf183f000 [10/63] { 7, 0x1, 0x501, 0x0000c }
18. UL proc 2-way U180 1M/1M at 0xfffa0000 [32] { 0, 0x0, 0x5aa, 0x00004
}
19. UL proc 2-way U180 1M/1M at 0xfffa2000 [34] { 0, 0x0, 0x5aa, 0x00004
}
20. Memory at 0xfffb1000 [49] { 1, 0x0, 0x07c, 0x00009 }
CONFIG_SMP=3Dn  ignoring additional CPUs
CPU: probe of 34 failed with error 1
CPU(s): 1 x PA8000 (PCX-U) at 180.000000 MHz
Setting cache flush threshold to 20 (1 CPUs online)
Found U2 at 0xfff88000
ccio_probe() ioc_count 0
ccio_probe() dev->hpa fff88000
ccio_probe() ioc->ioc_regs fff88000
ccio_ioc_init() num_physpages 65536
     count_parisc_driver 2
     iova_space_size 32768
     limited iova_space_size 32768
     iov_order 15
     iova_space_size now bytes 134217728
     ioc->pdir_size 262144
ccio_ioc_init() hpa 0xfff88000 mem 256MB IOV 128MB (27 bits)
ccio_ioc_init() pdir 10740000 size 40000
 base 10740000
ccio_ioc_init() res_size 0x1000
ccio_ioc_init() res_map 106b7000 size 1000
 chainid_shift 0x13
ccio_init_resource(res=3D10712c68, name=3DGSC Bus [8/], ioaddr=3Dfff88078=
)
ccio_init_resource() res->start f1000000
ccio_init_resource() res->end f17fffff
ccio_init_resource() res->end + 1  f1800000
ccio_init_resource() claimed CCIO bus address space (f1000000, f17fffff)
ccio_init_resource(res=3D10712c84, name=3DGSC Bus [8/], ioaddr=3Dfff88060=
)
ccio_init_resource() res->start fc000000
ccio_init_resource() res->end fff7ffff
ccio_init_resource() res->end + 1  fff80000
ccio_init_resource() claimed CCIO bus address space (fc000000, fff7ffff)
Found U2 at 0xfff8a000
ccio_probe() ioc_count 1
ccio_probe() dev->hpa fff8a000
ccio_probe() ioc->ioc_regs fff8a000
ccio_ioc_init() num_physpages 65536
     count_parisc_driver 2
     iova_space_size 32768
     limited iova_space_size 32768
     iov_order 15
     iova_space_size now bytes 134217728
     ioc->pdir_size 262144
ccio_ioc_init() hpa 0xfff8a000 mem 256MB IOV 128MB (27 bits)
ccio_ioc_init() pdir 10780000 size 40000
 base 10780000
ccio_ioc_init() res_size 0x1000
ccio_ioc_init() res_map 106b9000 size 1000
 chainid_shift 0x13
ccio_init_resource(res=3D1071245c, name=3DGSC Bus [10/], ioaddr=3Dfff8a07=
8)
ccio_init_resource() res->start f1800000
ccio_init_resource() res->end f1ffffff
ccio_init_resource() res->end + 1  f2000000
ccio_init_resource() claimed CCIO bus address space (f1800000, f1ffffff)
ccio_init_resource(res=3D10712478, name=3DGSC Bus [10/], ioaddr=3Dfff8a06=
0)
ccio_init_resource() res->start 00000000
ccio_init_resource() res->end ffffffff
ccio_init_resource() res->end + 1  00000000
Lasi version 0 at 0xffd00000 found.
...

64bit kernel:
Found devices:
1. U2-IOA BC Runway Port at 0xfffffffffff88000 [8] { 12, 0xf, 0x580, 0x00=
00b
}
2. UL 550 Lasi Core BA at 0xffffffffffd00000 [8/16] { 11, 0x0, 0x02f, 0x0=
0081
},  additional addresses: 0xffffffffffd0c000 0xffffffffffc00000
3. UL 550 Lasi Core RS-232 at 0xffffffffffd05000 [8/16/4] { 10, 0x0, 0x02=
f,
0x0008c }
4. UL 550 Core SCSI at 0xffffffffffd06000 [8/16/5] { 10, 0x0, 0x02f, 0x00=
082
}
5. UL 350 Core LAN (802.3) at 0xffffffffffd07000 [8/16/6] { 10, 0x0, 0x02=
f,
0x0008a }
6. UL 550 Core Centronics at 0xffffffffffd02000 [8/16/0] { 10, 0x0, 0x02f=
,
0x00074 },  additional addresses: 0xffffffffffd01000 0xffffffffffd03000
7. UL 550 Core PS/2 Port at 0xffffffffffd08000 [8/16/7] { 10, 0x0, 0x02f,=

0x00084 }
8. UL 550 Core PS/2 Port at 0xffffffffffd08100 [8/16/8] { 10, 0x0, 0x02f,=

0x00084 }
9. UL 550 Core Wax BA at 0xffffffffffe00000 [8/20] { 11, 0x0, 0x031, 0x00=
08e
}
10. UL 550 Wax EISA BA at 0xfffffffffc000000 [8/20/5] { 11, 0x0, 0x031, 0=
x00090
},  additional addresses: 0xffffffffffc88000
11. UL 550 Wax Core RS-232 at 0xffffffffffe02000 [8/20/2] { 10, 0x0, 0x03=
1,
0x0008c }
12. Bluefish Add-on FW-SCSI at 0xfffffffff1004000 [8/4] { 4, 0x1, 0x013,
0x00089 }
13. Bluefish Add-on FW-SCSI at 0xfffffffff1008000 [8/8] { 4, 0x1, 0x013,
0x00089 }
14. Bluefish Add-on FW-SCSI at 0xfffffffff100c000 [8/12] { 4, 0x1, 0x013,=

0x00089 }
15. U2-IOA BC GSC+ Port at 0xfffffffff103f000 [8/63] { 7, 0x1, 0x501, 0x0=
000c
}
16. U2-IOA BC Runway Port at 0xfffffffffff8a000 [10] { 12, 0xf, 0x580, 0x=
0000b
}
17. U2-IOA BC GSC+ Port at 0xfffffffff183f000 [10/63] { 7, 0x1, 0x501, 0x=
0000c
}
18. UL proc 2-way U180 1M/1M at 0xfffffffffffa0000 [32] { 0, 0x0, 0x5aa,
0x00004 }
19. UL proc 2-way U180 1M/1M at 0xfffffffffffa2000 [34] { 0, 0x0, 0x5aa,
0x00004 }
20. Memory at 0xfffffffffffb1000 [49] { 1, 0x0, 0x07c, 0x00009 }
CONFIG_SMP=3Dn  ignoring additional CPUs
CPU: probe of 34 failed with error 1
CPU(s): 1 x PA8000 (PCX-U) at 180.000000 MHz
Setting cache flush threshold to e9f80 (1 CPUs online)
Found U2 at 0xfffffffffff88000
ccio_probe() ioc_count 0
ccio_probe() dev->hpa fffffffffff88000
ccio_probe() ioc->ioc_regs fffffffffff88000
ccio_ioc_init() num_physpages 65536
     count_parisc_driver 2
     iova_space_size 32768
     limited iova_space_size 32768
     iov_order 15
     iova_space_size now bytes 134217728
     ioc->pdir_size 262144
ccio_ioc_init() hpa 0xfffffffffff88000 mem 256MB IOV 128MB (27 bits)
ccio_ioc_init() pdir 0000000010a80000 size 40000
 base 0000000010a80000
ccio_ioc_init() res_size 0x1000
ccio_ioc_init() res_map 00000000109e4000 size 1000
 chainid_shift 0x13
ccio_init_resource(res=3D00000000109e3858, name=3DGSC Bus [8/], ioaddr=3D=
fffffffffff88078)
ccio_init_resource() res->start fffffffff1000000
ccio_init_resource() res->end fffffffff17fffff
ccio_init_resource() res->end + 1  fffffffff1800000
ccio_init_resource() claimed CCIO bus address space (fffffffff1000000, ff=
fffffff17fffff)
ccio_init_resource(res=3D00000000109e3890, name=3DGSC Bus [8/], ioaddr=3D=
fffffffffff88060)
ccio_init_resource() res->start fffffffffc000000
ccio_init_resource() res->end fffffffffff7ffff
ccio_init_resource() res->end + 1  fffffffffff80000
ccio_init_resource() claimed CCIO bus address space (fffffffffc000000, ff=
fffffffff7ffff)
Found U2 at 0xfffffffffff8a000
ccio_probe() ioc_count 1
ccio_probe() dev->hpa fffffffffff8a000
ccio_probe() ioc->ioc_regs fffffffffff8a000
ccio_ioc_init() num_physpages 65536
     count_parisc_driver 2
     iova_space_size 32768
     limited iova_space_size 32768
     iov_order 15
     iova_space_size now bytes 134217728
     ioc->pdir_size 262144
ccio_ioc_init() hpa 0xfffffffffff8a000 mem 256MB IOV 128MB (27 bits)
ccio_ioc_init() pdir 0000000010ac0000 size 40000
 base 0000000010ac0000
ccio_ioc_init() res_size 0x1000
ccio_ioc_init() res_map 00000000109e6000 size 1000
 chainid_shift 0x13
ccio_init_resource(res=3D00000000109e5858, name=3DGSC Bus [10/], ioaddr=3D=
fffffffffff8a078)
ccio_init_resource() res->start fffffffff1800000
ccio_init_resource() res->end fffffffff1ffffff
ccio_init_resource() res->end + 1  fffffffff2000000
ccio_init_resource() claimed CCIO bus address space (fffffffff1800000, ff=
fffffff1ffffff)
ccio_init_resource(res=3D00000000109e5890, name=3DGSC Bus [10/], ioaddr=3D=
fffffffffff8a060)
ccio_init_resource() res->start ffffffff00000000
ccio_init_resource() res->end ffffffffffffffff
ccio_init_resource() res->end + 1  0000000000000000
ccio_init_resource() failed to claim CCIO bus address space (ffffffff0000=
0000,
ffffffffffffffff)
ccio_init_resource() claimed CCIO bus address space (ffffffff00000000, ff=
ffffffffffffff)
Lasi version 0 at 0xffffffffffd00000 found.

even thought I have no doc to now what would means:
        res->start =3D (unsigned long)(signed) READ_U32(ioaddr) << 16; (=3D=
=3D
0x0 in 32bits)
        res->end =3D (unsigned long)(signed) (READ_U32(ioaddr + 4) << 16)=
 -
1; (=3D=3D 0xffffffff in 32bits too)

but seems that test:
        if (res->end + 1 =3D=3D res->start)
is a stuff which not love 64bit :-(

Any idea?

Thanks,
    Joel

PS: I also noticed something weird versus my c110:
Found devices:
1. U2-IOA BC Runway Port at 0xfff8a000 [10] { 12, 0x7, 0x580, 0x0000b }
...
4. U2-IOA BC Runway Port at 0xfff88000 [8] { 12, 0x7, 0x580, 0x0000b }
...
Found U2 at 0xfff8a000
...
ccio_init_resource(res=3D10be2434, name=3DGSC Bus [10/], ioaddr=3Dfff8a07=
8)
ccio_init_resource() claimed CCIO bus address space (f3fc0000, f3ffffff)
ccio_init_resource(res=3D10be2450, name=3DGSC Bus [10/], ioaddr=3Dfff8a06=
0)
ccio_init_resource() claimed CCIO bus address space (f4000000, f7ffffff)
Found U2 at 0xfff88000
...
ccio_init_resource(res=3D10becc34, name=3DGSC Bus [8/], ioaddr=3Dfff88078=
)
ccio_init_resource() claimed CCIO bus address space (f3f80000, f3fbffff)
ccio_init_resource(res=3D10becc50, name=3DGSC Bus [8/], ioaddr=3Dfff88060=
)
ccio_init_resource() claimed CCIO bus address space (f8000000, ffe3ffff)
...

So there are well (2*2) resources initialized.

OTC on the d380 (32bit kernel)
Found devices:
1. U2-IOA BC Runway Port at 0xfff88000 [8] { 12, 0xf, 0x580, 0x0000b }
...
16. U2-IOA BC Runway Port at 0xfff8a000 [10] { 12, 0xf, 0x580, 0x0000b }
...
Found U2 at 0xfff88000
...
ccio_init_resource(res=3D10712c68, name=3DGSC Bus [8/], ioaddr=3Dfff88078=
)
ccio_init_resource() claimed CCIO bus address space (f1000000, f17fffff)
ccio_init_resource(res=3D10712c84, name=3DGSC Bus [8/], ioaddr=3Dfff88060=
)
ccio_init_resource() claimed CCIO bus address space (fc000000, fff7ffff)
Found U2 at 0xfff8a000
...
ccio_init_resource(res=3D1071245c, name=3DGSC Bus [10/], ioaddr=3Dfff8a07=
8)
ccio_init_resource() claimed CCIO bus address space (f1800000, f1ffffff)
ccio_init_resource(res=3D10712478, name=3DGSC Bus [10/], ioaddr=3Dfff8a06=
0)
...
if I well understand only 3 resources initialized?


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Re: [parisc-linux] ccio-dma 64bit debug_init info

[Grant Grundler]

On Tue, May 17, 2005 at 06:29:18PM +0200, Joel Soete wrote:
> > > ccio-dma.c: failed to claim CCIO bus address space (ffffffff00000000,ffffffffffffffff)
...
> > It would be interesting to know why it's asking for that range.
> > Where are the values of that range coming from?

> 32bit kernel:
...
> ccio_init_resource(res=10712c68, name=GSC Bus [8/], ioaddr=fff88078)
> ccio_init_resource() res->start f1000000
> ccio_init_resource() res->end f17fffff
> ccio_init_resource() res->end + 1  f1800000
> ccio_init_resource() claimed CCIO bus address space (f1000000, f17fffff)
> ccio_init_resource(res=10712c84, name=GSC Bus [8/], ioaddr=fff88060)
> ccio_init_resource() res->start fc000000
> ccio_init_resource() res->end fff7ffff
> ccio_init_resource() res->end + 1  fff80000
> ccio_init_resource() claimed CCIO bus address space (fc000000, fff7ffff)
...

Ah...I forgot that U2/Uturn have two sets of range registers.
One per GSC bus....

BTW, PDC sets all of this address stuff up AFAIK.

...
> ccio_init_resource(res=1071245c, name=GSC Bus [10/], ioaddr=fff8a078)
> ccio_init_resource() res->start f1800000
> ccio_init_resource() res->end f1ffffff
> ccio_init_resource() res->end + 1  f2000000
> ccio_init_resource() claimed CCIO bus address space (f1800000, f1ffffff)
> ccio_init_resource(res=10712478, name=GSC Bus [10/], ioaddr=fff8a060)
> ccio_init_resource() res->start 00000000
> ccio_init_resource() res->end ffffffff
> ccio_init_resource() res->end + 1  00000000
> Lasi version 0 at 0xffd00000 found.
> ...

This last one seems to be disabled.
That's what this code in ccio_init_resource() is testing for:
	if (res->end + 1 == res->start)
                return;
 
/me puts on his fortune teller hat and looks in his crystal ball:
	"Joel will be submitting a patch shortly...You must add a comment
	explaining WTF this test is doing..."


> 64bit kernel:
...
> ccio_init_resource(res=00000000109e3858, name=GSC Bus [8/], ioaddr=fffffffffff88078)
> ccio_init_resource() res->start fffffffff1000000
> ccio_init_resource() res->end fffffffff17fffff
> ccio_init_resource() res->end + 1  fffffffff1800000
> ccio_init_resource() claimed CCIO bus address space (fffffffff1000000, fffffffff17fffff)
> ccio_init_resource(res=00000000109e3890, name=GSC Bus [8/], ioaddr=fffffffffff88060)
> ccio_init_resource() res->start fffffffffc000000
> ccio_init_resource() res->end fffffffffff7ffff
> ccio_init_resource() res->end + 1  fffffffffff80000
> ccio_init_resource() claimed CCIO bus address space (fffffffffc000000, fffffffffff7ffff)

No problem with the first one.

...
> ccio_init_resource(res=00000000109e5858, name=GSC Bus [10/], ioaddr=fffffffffff8a078)
> ccio_init_resource() res->start fffffffff1800000
> ccio_init_resource() res->end fffffffff1ffffff
> ccio_init_resource() res->end + 1  fffffffff2000000
> ccio_init_resource() claimed CCIO bus address space (fffffffff1800000, fffffffff1ffffff)
> ccio_init_resource(res=00000000109e5890, name=GSC Bus [10/], ioaddr=fffffffffff8a060)
> ccio_init_resource() res->start ffffffff00000000
> ccio_init_resource() res->end ffffffffffffffff
> ccio_init_resource() res->end + 1  0000000000000000

This fails because io_io_low/high registers in reality are only 16 bits.
The upper 16 bits are hardcoded to 1's.
The conversion of res->start to 64-bit is wrong for this one case:
	res->start = (unsigned long)(signed) __raw_readl(ioaddr) << 16;

__raw_readl(ioaddr) returns 0xffff0000.
0xffff0000 << 16 should be 0 but it's not since this is 64-bit.
That line should read something like:
	res->start = (unsigned long) ((signed) __raw_readl(ioaddr) << 16);

And please add a comment here too that parenthesis *do* matter.
Then it should fail the same test that I point out above....

> ccio_init_resource() failed to claim CCIO bus address space (ffffffff00000000,
> ffffffffffffffff)

...and we wouldn't even try to acquire this range.

> ccio_init_resource() claimed CCIO bus address space (ffffffff00000000, ffffffffffffffff)
> Lasi version 0 at 0xffffffffffd00000 found.
> 
> even thought I have no doc to now what would means:
>         res->start = (unsigned long)(signed) READ_U32(ioaddr) << 16; (==
> 0x0 in 32bits)
>         res->end = (unsigned long)(signed) (READ_U32(ioaddr + 4) << 16) -
> 1; (== 0xffffffff in 32bits too)
> 
> but seems that test:
>         if (res->end + 1 == res->start)
> is a stuff which not love 64bit :-(

You almost got it right.

grant
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Re: [parisc-linux] ccio-dma 64bit debug_init info

[Joel Soete]

> 
> On Fri, May 13, 2005 at 07:50:05AM +0200, Joel Soete wrote:
> > Ah I thought (too quickly) that it could be the reason why:
> > ...
> > ccio-dma.c: failed to claim CCIO bus address space (ffffffff00000000,=
ffffffffffffffff)
> 
> That's a completely different issue.
> It would be interesting to know why it's asking for that range.
> Where are the values of that range coming from?
> (ie what is the origin of ffffffff00000000 value)
> 
Ah ok I will check...

btw 32 claimed are:
Setting cache flush threshold to 40 (1 CPUs online)
Found U2 at 0xfff88000
ccio_init_resource: claim CCIO bus address space (f1000000,f17fffff)
ccio_init_resource: claim CCIO bus address space (fc000000,fff7ffff)
Found U2 at 0xfff8a000
ccio_init_resource: claim CCIO bus address space (f1800000,f1ffffff)

(just added printk at the end of ccio_init :-)

Thanks,
    Joel


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[parisc-linux] ccio-dma 64bit debug_init info

[Joel Soete]

Hello all,

I try to figure out what's wrong with ccio-dma for 64bit and put on DEBUG=
_INIT
an collect:
for 32bit kernel:
...
Setting cache flush threshold to 20 (1 CPUs online)
Found U2 at 0xfff88000
ccio_ioc_init() hpa 0xfff88000 mem 256MB IOV 128MB (27 bits)
 base 10740000
ccio_ioc_init() res_size 0x1000
 chainid_shift 0x13 
Found U2 at 0xfff8a000
ccio_ioc_init() hpa 0xfff8a000 mem 256MB IOV 128MB (27 bits) 
 base 10780000 
ccio_ioc_init() res_size 0x1000
 chainid_shift 0x13 
Lasi version 0 at 0xffd00000 found.
...

Otc for 64bit kernel:
...
Setting cache flush threshold to ee7c0 (1 CPUs online)
Found U2 at 0xfffffffffff88000
ccio_ioc_init() hpa 0xfffffffffff88000 mem 256MB IOV 128MB (27 bits) 
 base 0000000010a80000 
ccio_ioc_init() res_size 0x1000
 chainid_shift 0x13 
Found U2 at 0xfffffffffff8a000
ccio_ioc_init() hpa 0xfffffffffff8a000 mem 256MB IOV 128MB (27 bits) 
 base 0000000010ac0000
ccio_ioc_init() res_size 0x1000
 chainid_shift 0x13 
...

mmm base address seems to be wrong.

Any idea from where came this pb?

Thanks,
    Joel


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Re: [parisc-linux] ccio-dma 64bit debug_init info

[Grant Grundler]

On Thu, May 12, 2005 at 07:37:27PM +0200, Joel Soete wrote:
> Hello all,
> 
> I try to figure out what's wrong with ccio-dma for 64bit and put on DEBUG_INIT
> an collect:
> for 32bit kernel:
>  base 10740000
>  base 10780000
> ...
> 
> Otc for 64bit kernel:
> ...
>  base 0000000010a80000
>  base 0000000010ac0000
> ...
> 
> mmm base address seems to be wrong.

You mean it's different. What makes you think it's wrong?

grant
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