Re: [parisc-linux] Heavy Iron Reference Docs

["Michael S. Zick" <mszick@morethan.org>]

On Sun April 30 2006 16:25, John David Anglin wrote:
> 
> Note the line doesn't have to be dirty.  Unless extreme care is
> used, the line could have been be brought into cache by a load for
> data elsewhere on the line.  So for correct operation of 'ldcw,co',
> there really must be no inter-processor timing problems in kicking
> out cachelines.  Otherwise, we could end up with two dirty cachelines
> and a broken spinlock.
> 

Somewhere it is written: "No data should be stored on the same cache
line as the lock unless all access is protected by that lock."

I recall the quote, do not recall which document.

That is what you just said above.  It makes sense even if not using
the coherent version of the semaphore instruction.

It makes even more sense if we are directly trying to control the
cache behavior using the coherent version.

One lock per cache line and knowledge of how long the cache line
is on a machine seems to be safe rule for now.

I.E: Fix it first, make it elegant later.

> It may be this is only reliable on fully coherent systems.  While
> the N-class is classified as a UMA machine, it has two system buses
> separated by a memory controller.  Each system bus can handle four
> processors with L1 and L2 cache.  Thus, it would seem safer to adopt
> the prewrite and use ldcw without the cache control completer.
> 

Scratches head...

I wonder where Joel has his processors installed in relation to the
two busses?  Both on same buss or one per buss?  Would his lockups
go away if he picked the other relationship?

I will ask him.  (or perhaps I just did)

Mike
> Dave
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