Re: [parisc-linux] Heavy Iron Reference Docs

[Grant Grundler <grundler@parisc-linux.org>]

On Sun, Apr 30, 2006 at 05:25:13PM -0400, John David Anglin wrote:
...
> I also suggest using an ordered store for the unlock operation.  This
> doesn't cost anything and may help to ensure that the order of memory
> accesses as seen by another processor occur in the expected sequence.

I've had it drilled into my head that all parisc implmentations
have strongly ordered memory subsystems. John Marvin (jsm) has
stated that more than a few times on this list. So "ordered store"
is the same as a regular store.

> It all comes down to this crucial bit of code in the ldcw description:

I'd rather have someone like Jerry Huck or someone in his experience
comment on this before we go down this path.  I'll try to find
someone to consult with this week.

...
> It may be this is only reliable on fully coherent systems.  While
> the N-class is classified as a UMA machine, it has two system buses
> separated by a memory controller.  Each system bus can handle four
> processors with L1 and L2 cache.

AFAIK, N-class has no L2 cache.

But it's worse than you think.
N-class has two _Merced_ busses connected to the memory controller. 
Each Processor is connected via a double pumped Runway Bus to "Dew"
which acts as a "bridge" to one of the Merced Busses.

[ Digression - certain document says:
	In PA-RISC, code fetches are non-coherent, such that PCX-W doesn't
	even supply Vindex bits that would allow the code fetches to be
	coherent.
]

> Thus, it would seem safer to adopt
> the prewrite and use ldcw without the cache control completer.

I'm skeptical but will ask about this.
Maybe I'm thinking kernel space only...is this intended only for
user space or for kernel also?

thanks,
grant
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