Re: [PATCH v3] parisc: Fix crash due alternative coding for NP iopdir_fdc bit

[Sven Schnelle <svens@stackframe.org>]

Hi,

On Wed, May 29, 2019 at 04:15:03PM +0200, Helge Deller wrote:
> >> Exactly. And as:
> >>
> >> a) All C3600 PDC versions clear the NP bit
> >> b) All C37XX/J5000 PDC version set the NP bit
> >>
> >> i don't think there's some bug in the PDC. I would guess that the patch Carlo
> >> reported to fix issues is just hiding the real problem. Would be interesting
> >> to run Carlo's Test on a C37XX.
> >
> > Probably, hardware cache coherent I/O is not implemented correctly for Elroy based systems.
> > https://www.hpl.hp.com/hpjournal/96feb/feb96a6.pdf
> > Does it work on C360?
> 
> I slowly start to get confused...
> Just thinking about another possibility: Maybe we can rely on the value of the
> NP iopdir_fdc bit only on machines with >= PA8700 CPUs?
> For older machines (which would need opdir_fdc) HP-UX or other operating
> systems decides on the found CPU.
> This would explain why it's not  set on Carlo's C3600, and if Sven's C240
> (with a PA8200 CPU) doesn't has the bit set too, then this could explain this theory.

I just re-tested my kexec branch, and the HPMC i was seeing when kexec'ing a new
kernel on my J5000 is now gone with Helge's patch. J5000 also has PCX-W. It was
only triggered when i had SMP enabled, but this is somehow not suprising given
the fact that a cache flush was missing.

Regards
Sven