[PATCH] parisc: fix LMMIO mismatch between PAT length and MASK register

[PATCH] parisc: fix LMMIO mismatch between PAT length and MASK register

[Helge Deller]

From: Thomas Bogendoerfer <tsbogend@alpha.franken.de>

The LMMIO length reported by PAT and the length given by the LBA MASK
register are not consistent. This leads e.g. to a non-working ATI FireGL
card with the radeon DRM driver since the memory can't be mapped.

Fix this by correctly adjusting the resource sizes.

Signed-off-by: Helge Deller <deller@gmx.de>

diff --git a/drivers/parisc/lba_pci.c b/drivers/parisc/lba_pci.c
index 1f05913..7dc0e40 100644
--- a/drivers/parisc/lba_pci.c
+++ b/drivers/parisc/lba_pci.c
@@ -994,6 +994,15 @@ lba_pat_resources(struct parisc_device *pa_dev, struct lba_device *lba_dev)
 		case PAT_LMMIO:
 			/* used to fix up pre-initialized MEM BARs */
 			if (!lba_dev->hba.lmmio_space.flags) {
+				unsigned long lba_len;
+				lba_len = ~READ_REG32(lba_dev->hba.base_addr
+						+ LBA_LMMIO_MASK);
+				if ((p->end - p->start) != lba_len) {
+					pr_warn("PCI%02x LMMIO mismatch between PAT length (0x%lx) and MASK register (0x%lx), fixing.\n",
+					  (int)lba_dev->hba.bus_num.start,
+						p->end - p->start, lba_len);
+					p->end = p->start + lba_len;
+				}
 				sprintf(lba_dev->hba.lmmio_name,
 						"PCI%02x LMMIO",
 						(int)lba_dev->hba.bus_num.start);

Re: [PATCH] parisc: fix LMMIO mismatch between PAT length and MASK register

[Matt Turner]

On Fri, Jun 14, 2013 at 12:11 AM, Helge Deller <deller@gmx.de> wrote:
> From: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
>
> The LMMIO length reported by PAT and the length given by the LBA MASK
> register are not consistent. This leads e.g. to a non-working ATI FireGL
> card with the radeon DRM driver since the memory can't be mapped.
>
> Fix this by correctly adjusting the resource sizes.
>
> Signed-off-by: Helge Deller <deller@gmx.de>
>
> diff --git a/drivers/parisc/lba_pci.c b/drivers/parisc/lba_pci.c
> index 1f05913..7dc0e40 100644
> --- a/drivers/parisc/lba_pci.c
> +++ b/drivers/parisc/lba_pci.c
> @@ -994,6 +994,15 @@ lba_pat_resources(struct parisc_device *pa_dev, struct lba_device *lba_dev)
>                 case PAT_LMMIO:
>                         /* used to fix up pre-initialized MEM BARs */
>                         if (!lba_dev->hba.lmmio_space.flags) {
> +                               unsigned long lba_len;
> +                               lba_len = ~READ_REG32(lba_dev->hba.base_addr
> +                                               + LBA_LMMIO_MASK);
> +                               if ((p->end - p->start) != lba_len) {
> +                                       pr_warn("PCI%02x LMMIO mismatch between PAT length (0x%lx) and MASK register (0x%lx), fixing.\n",
> +                                         (int)lba_dev->hba.bus_num.start,
> +                                               p->end - p->start, lba_len);
> +                                       p->end = p->start + lba_len;
> +                               }
>                                 sprintf(lba_dev->hba.lmmio_name,
>                                                 "PCI%02x LMMIO",
>                                                 (int)lba_dev->hba.bus_num.start);
> --

With these two patches, does kernel modesetting (and X11?) work?

Re: [PATCH] parisc: fix LMMIO mismatch between PAT length and MASK register

[Helge Deller]

* Matt Turner <mattst88@gmail.com>:
> On Fri, Jun 14, 2013 at 12:11 AM, Helge Deller <deller@gmx.de> wrote:
> > From: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
> >
> > The LMMIO length reported by PAT and the length given by the LBA MASK
> > register are not consistent. This leads e.g. to a non-working ATI FireGL
> > card with the radeon DRM driver since the memory can't be mapped.
> >
> > Fix this by correctly adjusting the resource sizes.
> >
> > Signed-off-by: Helge Deller <deller@gmx.de>
> >
> > diff --git a/drivers/parisc/lba_pci.c b/drivers/parisc/lba_pci.c
> > index 1f05913..7dc0e40 100644
> > --- a/drivers/parisc/lba_pci.c
> > +++ b/drivers/parisc/lba_pci.c
> > @@ -994,6 +994,15 @@ lba_pat_resources(struct parisc_device *pa_dev, struct lba_device *lba_dev)
> >                 case PAT_LMMIO:
> >                         /* used to fix up pre-initialized MEM BARs */
> >                         if (!lba_dev->hba.lmmio_space.flags) {
> > +                               unsigned long lba_len;
> > +                               lba_len = ~READ_REG32(lba_dev->hba.base_addr
> > +                                               + LBA_LMMIO_MASK);
> > +                               if ((p->end - p->start) != lba_len) {
> > +                                       pr_warn("PCI%02x LMMIO mismatch between PAT length (0x%lx) and MASK register (0x%lx), fixing.\n",
> > +                                         (int)lba_dev->hba.bus_num.start,
> > +                                               p->end - p->start, lba_len);
> > +                                       p->end = p->start + lba_len;
> > +                               }
> >                                 sprintf(lba_dev->hba.lmmio_name,
> >                                                 "PCI%02x LMMIO",
> >                                                 (int)lba_dev->hba.bus_num.start);
> > --
> 
> With these two patches, does kernel modesetting (and X11?) work?

Yes, C8000 with ATI FireGL works then for me with framebuffer, SMP, serial port...everything I tested so far.

Important: *Disable* RADEON Framebuffer driver, and enable Radeon DRM driver instead!

I did not tested X11 yet (still need to fully install the C8000 with our
unstable) - but Thomas mentioned once that this is needed for X11.

BTW, I'll prepare a new installation CD for all machines soon...hopefully until end of
next week and hopefully when kernel 3.10 is released.

If you want to test, pull from git://git.kernel.org/pub/scm/linux/kernel/git/deller/parisc-linux.git
a)  my "for-3.10" branch, then
b)  my "important-for-3.10" branch (two fixed on which I wait for James)...

PS: Does someone has a C800 with 0x77 serial ports? In that case some
small patch to the serial driver is needed to get it detected....

Helge

Re: [PATCH] parisc: fix LMMIO mismatch between PAT length and MASK register

[Helge Deller]

* Helge Deller <deller@gmx.de>:
> PS: Does someone has a C800 with 0x77 serial ports? In that case some
> small patch to the serial driver is needed to get it detected....

I meant C8000 of course...

Re: [PATCH] parisc: fix LMMIO mismatch between PAT length and MASK register

[Thomas Bogendoerfer]

On Fri, Jun 14, 2013 at 09:38:27AM +0200, Helge Deller wrote:
> I did not tested X11 yet (still need to fully install the C8000 with our
> unstable) - but Thomas mentioned once that this is needed for X11.

the pci mmap thing is a must for X11 to even get the card detected. This
patch is needed for the FireGL X3 cards with 256MB video memory.

Thomas.

-- 
Crap can work. Given enough thrust pigs will fly, but it's not necessarily a
good idea.                                                [ RFC1925, 2.3 ]

Re: [PATCH] parisc: fix LMMIO mismatch between PAT length and MASK register

[Alex Ivanov]

Helge Deller <deller <at> gmx.de> writes:

> I did not tested X11 yet (still need to fully install the C8000 with our
> unstable) - but Thomas mentioned once that this is needed for X11.

I've built from test-3.10 branch of your repo:
Linux version 3.10.0-rc6-64bit-c3000+ (root@parisc) 
(gcc version 4.6.4 (GCC) ) #4 SMP PREEMPT Mon Jul 8 23:16:48 
MSK 2013

I'm using a c8000 with firegl x3. I approve that console works, 
although in an unaccelerated mode. However xorg isn't:
http://pastebin.com/Y1h2BVHB
The system is latest unstable. The xorg is of 1:7.7+3 version.

Re: [PATCH] parisc: fix LMMIO mismatch between PAT length and MASK register

[John David Anglin]

On 7/9/2013 1:34 AM, Alex Ivanov wrote:
> I'm using a c8000 with firegl x3. I approve that console works,
> although in an unaccelerated mode. However xorg isn't:
> http://pastebin.com/Y1h2BVHB
> The system is latest unstable. The xorg is of 1:7.7+3 version.
Suggest you hack arch/parisc/kernel/cache.c to disable this
optimization:

         /* Flushing the whole cache on each cpu takes forever on
            rp3440, etc.  So, avoid it if the mm isn't too big.  */
         if (mm_total_size(mm) < parisc_cache_flush_threshold) {

It is probably the get_ptep call in the non current case that's failing
with firegl x3.  It would be useful if you could test if the current case
, "mm->context == mfsp(3)" case works.  You would have to move return
and disable non current block.

Dave

-- 
John David Anglin    dave.anglin@bell.net

Re: [PATCH] parisc: fix LMMIO mismatch between PAT length and MASK register

[Alex Ivanov]

John David Anglin <dave.anglin <at> bell.net> writes:

> It would be useful if you could test if the current case
> , "mm->context == mfsp(3)" case works.
> You would have to move return
> and disable non current block.

Done. The system seems to work as usual. Should i do 
some specific checks?

> Suggest you hack arch/parisc/kernel/cache.c to 
> disable this optimization

The panic on SMP kernel changed to another one:
http://pastebin.com/SfUfd0Un
Same was before with an UP kernel. The only thing
i've changed since is moving to the latest toolchains.
Can't reproduce the previous panic case, so can't
comment on your proposed solution.

P.S.: The hw is not faulty, works ok under hpux.

Re: [PATCH] parisc: fix LMMIO mismatch between PAT length and MASK register

[John David Anglin]

[-- Attachment #1: Type: text/plain, Size: 397 bytes --]

On 7/9/2013 3:45 PM, Alex Ivanov wrote:
> The panic on SMP kernel changed to another one:
> http://pastebin.com/SfUfd0Un
This is just a guess but I don't think page is valid
if the pfn is not valid.  You might try this untested change.

flush_cache_mm might have same problem (i.e., we may need to
check whether the pfn for the pte is valid).

Dave

-- 
John David Anglin    dave.anglin@bell.net


[-- Attachment #2: cache.c.d.txt --]
[-- Type: text/plain, Size: 702 bytes --]

diff --git a/arch/parisc/kernel/cache.c b/arch/parisc/kernel/cache.c
index 65fb4cb..8f60123 100644
--- a/arch/parisc/kernel/cache.c
+++ b/arch/parisc/kernel/cache.c
@@ -74,10 +74,13 @@ EXPORT_SYMBOL(flush_cache_all_local);
 void
 update_mmu_cache(struct vm_area_struct *vma, unsigned long address, pte_t *ptep)
 {
-	struct page *page = pte_page(*ptep);
+	struct page *page;
 
-	if (pfn_valid(page_to_pfn(page)) && page_mapping(page) &&
-	    test_bit(PG_dcache_dirty, &page->flags)) {
+	if (!pfn_valid(*ptep))
+		return;
+
+	page = pte_page(*ptep);
+	if (page_mapping(page) && test_bit(PG_dcache_dirty, &page->flags)) {
 
 		flush_kernel_dcache_page(page);
 		clear_bit(PG_dcache_dirty, &page->flags);

Re: [PATCH] parisc: fix LMMIO mismatch between PAT length and MASK register

[John David Anglin]

[-- Attachment #1: Type: text/plain, Size: 501 bytes --]

On 9-Jul-13, at 4:59 PM, John David Anglin wrote:

> On 7/9/2013 3:45 PM, Alex Ivanov wrote:
>> The panic on SMP kernel changed to another one:
>> http://pastebin.com/SfUfd0Un
> This is just a guess but I don't think page is valid
> if the pfn is not valid.  You might try this untested change.
>
> flush_cache_mm might have same problem (i.e., we may need to
> check whether the pfn for the pte is valid).

This version compiles and boots on rp3440.

Dave
--
John David Anglin	dave.anglin@bell.net



[-- Attachment #2: cache.c.d.txt --]
[-- Type: text/plain, Size: 1078 bytes --]

diff --git a/arch/parisc/kernel/cache.c b/arch/parisc/kernel/cache.c
index 65fb4cb..b07720f 100644
--- a/arch/parisc/kernel/cache.c
+++ b/arch/parisc/kernel/cache.c
@@ -74,10 +74,13 @@ EXPORT_SYMBOL(flush_cache_all_local);
 void
 update_mmu_cache(struct vm_area_struct *vma, unsigned long address, pte_t *ptep)
 {
-	struct page *page = pte_page(*ptep);
+	struct page *page;
 
-	if (pfn_valid(page_to_pfn(page)) && page_mapping(page) &&
-	    test_bit(PG_dcache_dirty, &page->flags)) {
+	if (!pfn_valid(pte_pfn(*ptep)))
+		return;
+
+	page = pte_page(*ptep);
+	if (page_mapping(page) && test_bit(PG_dcache_dirty, &page->flags)) {
 
 		flush_kernel_dcache_page(page);
 		clear_bit(PG_dcache_dirty, &page->flags);
@@ -519,8 +522,9 @@ void flush_cache_mm(struct mm_struct *mm)
 					pte_t *ptep = get_ptep(pgd, addr);
 					if (ptep != NULL) {
 						pte_t pte = *ptep;
-						__flush_cache_page(vma, addr,
-						  page_to_phys(pte_page(pte)));
+						if (pfn_valid(pte_pfn(pte)))
+							__flush_cache_page(vma, addr,
+						  		page_to_phys(pte_page(pte)));
 					}
 				}
 			}

Re: [PATCH] parisc: fix LMMIO mismatch between PAT length and MASK register

[Alex Ivanov]

Sorry for not CC'ing to the list.

10.07.2013, 03:35, "John David Anglin" <dave.anglin@bell.net>:

> =9AOn 9-Jul-13, at 4:59 PM, John David Anglin wrote:
>> =9A=9AOn 7/9/2013 3:45 PM, Alex Ivanov wrote:
>>> =9A=9AThe panic on SMP kernel changed to another one:
>>> =9A=9Ahttp://pastebin.com/SfUfd0Un
>> =9A=9AThis is just a guess but I don't think page is valid
>> =9A=9Aif the pfn is not valid. =9AYou might try this untested change=
=2E
>>
>> =9A=9Aflush_cache_mm might have same problem (i.e., we may need to
>> =9A=9Acheck whether the pfn for the pte is valid).
> =9AThis version compiles and boots on rp3440.
>
> =9ADave
> =9A--
> =9AJohn David Anglin dave.anglin@bell.net

Dave,

Thank you so much! Your guess looks to be right. After applying of your
patch there was no more KP and X just worked.
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Re: [PATCH] parisc: fix LMMIO mismatch between PAT length and MASK register

[John David Anglin]

On 7/10/2013 4:19 PM, Alex Ivanov wrote:
> Sorry for not CC'ing to the list.
>
> 10.07.2013, 03:35, "John David Anglin" <dave.anglin@bell.net>:
>
>>   On 9-Jul-13, at 4:59 PM, John David Anglin wrote:
>>>    On 7/9/2013 3:45 PM, Alex Ivanov wrote:
>>>>    The panic on SMP kernel changed to another one:
>>>>    http://pastebin.com/SfUfd0Un
>>>    This is just a guess but I don't think page is valid
>>>    if the pfn is not valid.  You might try this untested change.
>>>
>>>    flush_cache_mm might have same problem (i.e., we may need to
>>>    check whether the pfn for the pte is valid).
>>   This version compiles and boots on rp3440.
>>
>>   Dave
>>   --
>>   John David Anglin dave.anglin@bell.net
> Dave,
>
> Thank you so much! Your guess looks to be right. After applying of your
> patch there was no more KP and X just worked.
I have been studying this issue a bit more.  It looks to me as if it 
would be better to call
vm_normal_page to get the page.  It returns NULL when we a have special 
mapping that
doesn't want to be associated with a struct page.  See comment in 
mm/memory.c.

I'll send a patch when I get a chance to test this approach.

Dave

-- 
John David Anglin    dave.anglin@bell.net

Re: [PATCH] parisc: fix LMMIO mismatch between PAT length and MASK register

[Matt Turner]

On Wed, Jul 10, 2013 at 1:19 PM, Alex Ivanov <gnidorah@p0n4ik.tk> wrote:
> Thank you so much! Your guess looks to be right. After applying of your
> patch there was no more KP and X just worked.

Nice! Does DRI work?

Re: [PATCH] parisc: fix LMMIO mismatch between PAT length and MASK register

[Alex Ivanov]

11.07.2013, 01:14, "Matt Turner" <mattst88@gmail.com>:
> On Wed, Jul 10, 2013 at 1:19 PM, Alex Ivanov <gnidorah@p0n4ik.tk> wro=
te:
>
>> =9AThank you so much! Your guess looks to be right. After applying o=
f your
>> =9Apatch there was no more KP and X just worked.
>
> Nice! Does DRI work?

Not on my side. Plus i can't visually jump over 8bit depth, although Xo=
rg=20
states 24bit in it's log.
As for DRI, i'm experiencing=20
"ring test failed (scratch(0x15E4)=3D0xCAFEDEAD)" with a firegl x3.

Can't figure out why, the ring vaddr (0x0000000060001000) is within the
limits of dma32. But the ring test fails. And i'm afraid that just addi=
ng a=20
buffer bounces in places will not help.
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Re: [PATCH] parisc: fix LMMIO mismatch between PAT length and MASK register

[Helge Deller]

adding linux parisc mailing list...:

On 07/11/2013 09:46 PM, Helge Deller wrote:
> On 07/10/2013 11:29 PM, Alex Ivanov wrote:
>> 11.07.2013, 01:14, "Matt Turner" <mattst88@gmail.com>:
>>> On Wed, Jul 10, 2013 at 1:19 PM, Alex Ivanov <gnidorah@p0n4ik.tk> wrote:
>>>
>>>>  Thank you so much! Your guess looks to be right. After applying of your
>>>>  patch there was no more KP and X just worked.
>>>
>>> Nice! Does DRI work?
>>
>> Not on my side. Plus i can't visually jump over 8bit depth, although Xorg 
>> states 24bit in it's log.
>> As for DRI, i'm experiencing 
>> "ring test failed (scratch(0x15E4)=0xCAFEDEAD)" with a firegl x3.
> 
> FWIW, I'm seeing the same failure on my FireGL X1:
> 80:00.0 VGA compatible controller: Advanced Micro Devices [AMD] nee ATI Radeon R300 NG [FireGL X1] (rev 80)
> 
> [drm] radeon: irq initialized.
> [drm] Loading R300 Microcode
> [drm] radeon: ring at 0x0000000060001000
> [drm:r100_ring_test] *ERROR* radeon: ring test failed (scratch(0x15E4)=0xCAFEDEAD)
> [drm:r100_cp_init] *ERROR* radeon: cp isn't working (-22).
> radeon 0000:80:00.0: failed initializing CP (-22).
> radeon 0000:80:00.0: Disabling GPU acceleration
> [drm:r100_cp_fini] *ERROR* Wait for CP idle timeout, shutting down CP.
> [drm] radeon: cp finalized
> [drm] radeon: cp finalized
> 
> I haven't tested X11 yet.
> 
>> Can't figure out why, the ring vaddr (0x0000000060001000) is within the
>> limits of dma32. But the ring test fails. And i'm afraid that just adding a 
>> buffer bounces in places will not help.
> 
> Helge
> 

Re: [PATCH] parisc: fix LMMIO mismatch between PAT length and MASK register

[Alex Ivanov]

11.07.2013, 23:48, "Helge Deller" <deller@gmx.de>:
> adding linux parisc mailing list...:
>
> On 07/11/2013 09:46 PM, Helge Deller wrote:
>
>> =9AOn 07/10/2013 11:29 PM, Alex Ivanov wrote:
>>> =9A11.07.2013, 01:14, "Matt Turner" <mattst88@gmail.com>:
>>>> =9AOn Wed, Jul 10, 2013 at 1:19 PM, Alex Ivanov <gnidorah@p0n4ik.t=
k> wrote:
>>>>> =9A=9AThank you so much! Your guess looks to be right. After appl=
ying of your
>>>>> =9A=9Apatch there was no more KP and X just worked.
>>>> =9ANice! Does DRI work?
>>> =9ANot on my side. Plus i can't visually jump over 8bit depth, alth=
ough Xorg
>>> =9Astates 24bit in it's log.
>>> =9AAs for DRI, i'm experiencing
>>> =9A"ring test failed (scratch(0x15E4)=3D0xCAFEDEAD)" with a firegl =
x3.
>> =9AFWIW, I'm seeing the same failure on my FireGL X1:
>> =9A80:00.0 VGA compatible controller: Advanced Micro Devices [AMD] n=
ee ATI Radeon R300 NG [FireGL X1] (rev 80)
>>
>> =9A[drm] radeon: irq initialized.
>> =9A[drm] Loading R300 Microcode
>> =9A[drm] radeon: ring at 0x0000000060001000
>> =9A[drm:r100_ring_test] *ERROR* radeon: ring test failed (scratch(0x=
15E4)=3D0xCAFEDEAD)
>> =9A[drm:r100_cp_init] *ERROR* radeon: cp isn't working (-22).
>> =9Aradeon 0000:80:00.0: failed initializing CP (-22).
>> =9Aradeon 0000:80:00.0: Disabling GPU acceleration
>> =9A[drm:r100_cp_fini] *ERROR* Wait for CP idle timeout, shutting dow=
n CP.
>> =9A[drm] radeon: cp finalized
>> =9A[drm] radeon: cp finalized

I still have no clue why this happens. Broken SBA IOMMU / DRM code? Mis=
sing syncing primitives?
Should we forward this to dri-devel mail list?
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Re: [PATCH] parisc: fix LMMIO mismatch between PAT length and MASK register

[John David Anglin]

On 4-Aug-13, at 7:00 AM, Alex Ivanov wrote:

> 11.07.2013, 23:48, "Helge Deller" <deller@gmx.de>:
>> adding linux parisc mailing list...:
>>
>> On 07/11/2013 09:46 PM, Helge Deller wrote:
>>
>>>  On 07/10/2013 11:29 PM, Alex Ivanov wrote:
>>>>  11.07.2013, 01:14, "Matt Turner" <mattst88@gmail.com>:
>>>>>  On Wed, Jul 10, 2013 at 1:19 PM, Alex Ivanov  
>>>>> <gnidorah@p0n4ik.tk> wrote:
>>>>>>   Thank you so much! Your guess looks to be right. After  
>>>>>> applying of your
>>>>>>   patch there was no more KP and X just worked.
>>>>>  Nice! Does DRI work?
>>>>  Not on my side. Plus i can't visually jump over 8bit depth,  
>>>> although Xorg
>>>>  states 24bit in it's log.
>>>>  As for DRI, i'm experiencing
>>>>  "ring test failed (scratch(0x15E4)=0xCAFEDEAD)" with a firegl x3.
>>>  FWIW, I'm seeing the same failure on my FireGL X1:
>>>  80:00.0 VGA compatible controller: Advanced Micro Devices [AMD]  
>>> nee ATI Radeon R300 NG [FireGL X1] (rev 80)
>>>
>>>  [drm] radeon: irq initialized.
>>>  [drm] Loading R300 Microcode
>>>  [drm] radeon: ring at 0x0000000060001000
>>>  [drm:r100_ring_test] *ERROR* radeon: ring test failed  
>>> (scratch(0x15E4)=0xCAFEDEAD)
>>>  [drm:r100_cp_init] *ERROR* radeon: cp isn't working (-22).
>>>  radeon 0000:80:00.0: failed initializing CP (-22).
>>>  radeon 0000:80:00.0: Disabling GPU acceleration
>>>  [drm:r100_cp_fini] *ERROR* Wait for CP idle timeout, shutting  
>>> down CP.
>>>  [drm] radeon: cp finalized
>>>  [drm] radeon: cp finalized
>
> I still have no clue why this happens. Broken SBA IOMMU / DRM code?  
> Missing syncing primitives?

I wonder if there is a endian issue in the microcode load.

Dave
--
John David Anglin	dave.anglin@bell.net

Re: [PATCH] parisc: fix LMMIO mismatch between PAT length and MASK register

[Matt Turner]

On Sun, Aug 4, 2013 at 8:44 AM, John David Anglin <dave.anglin@bell.net> wrote:
> I wonder if there is a endian issue in the microcode load.

It should work on PowerPC (big-endian).

Re: [PATCH] parisc: fix LMMIO mismatch between PAT length and MASK register

[John David Anglin]

On 4-Aug-13, at 7:00 AM, Alex Ivanov wrote:

> 11.07.2013, 23:48, "Helge Deller" <deller@gmx.de>:
>> adding linux parisc mailing list...:
>>
>> On 07/11/2013 09:46 PM, Helge Deller wrote:
>>
>>>  On 07/10/2013 11:29 PM, Alex Ivanov wrote:
>>>>  11.07.2013, 01:14, "Matt Turner" <mattst88@gmail.com>:
>>>>>  On Wed, Jul 10, 2013 at 1:19 PM, Alex Ivanov  
>>>>> <gnidorah@p0n4ik.tk> wrote:
>>>>>>   Thank you so much! Your guess looks to be right. After  
>>>>>> applying of your
>>>>>>   patch there was no more KP and X just worked.
>>>>>  Nice! Does DRI work?
>>>>  Not on my side. Plus i can't visually jump over 8bit depth,  
>>>> although Xorg
>>>>  states 24bit in it's log.
>>>>  As for DRI, i'm experiencing
>>>>  "ring test failed (scratch(0x15E4)=0xCAFEDEAD)" with a firegl x3.
>>>  FWIW, I'm seeing the same failure on my FireGL X1:
>>>  80:00.0 VGA compatible controller: Advanced Micro Devices [AMD]  
>>> nee ATI Radeon R300 NG [FireGL X1] (rev 80)
>>>
>>>  [drm] radeon: irq initialized.
>>>  [drm] Loading R300 Microcode
>>>  [drm] radeon: ring at 0x0000000060001000
>>>  [drm:r100_ring_test] *ERROR* radeon: ring test failed  
>>> (scratch(0x15E4)=0xCAFEDEAD)
>>>  [drm:r100_cp_init] *ERROR* radeon: cp isn't working (-22).
>>>  radeon 0000:80:00.0: failed initializing CP (-22).
>>>  radeon 0000:80:00.0: Disabling GPU acceleration
>>>  [drm:r100_cp_fini] *ERROR* Wait for CP idle timeout, shutting  
>>> down CP.
>>>  [drm] radeon: cp finalized
>>>  [drm] radeon: cp finalized

Have you tried agpmode=-1 to force PCI mode.  It seems like this was a  
problem at one time on ubuntu:
http://phoronix.com/forums/showthread.php?17615-Testing-radeon-KMS-on-Ubuntu

Dave
--
John David Anglin	dave.anglin@bell.net

Re: [PATCH] parisc: fix LMMIO mismatch between PAT length and MASK register

[Thomas Bogendoerfer]

On Fri, Jun 14, 2013 at 09:11:42AM +0200, Helge Deller wrote:
> From: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
> 
> The LMMIO length reported by PAT and the length given by the LBA MASK
> register are not consistent. This leads e.g. to a non-working ATI FireGL
> card with the radeon DRM driver since the memory can't be mapped.
> 
> Fix this by correctly adjusting the resource sizes.
> 
> Signed-off-by: Helge Deller <deller@gmx.de>

add my Acked-By or Signed-off-by, whatever you like.

BTW. thanks for cleaning up the patches.

Thomas.

-- 
Crap can work. Given enough thrust pigs will fly, but it's not necessarily a
good idea.                                                [ RFC1925, 2.3 ]

Re: [PATCH] parisc: fix LMMIO mismatch between PAT length and MASK register

[Helge Deller]

* Helge Deller <deller@gmx.de>:
> From: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
> 
> The LMMIO length reported by PAT and the length given by the LBA MASK
> register are not consistent. This leads e.g. to a non-working ATI FireGL
> card with the radeon DRM driver since the memory can't be mapped.
> 
> Fix this by correctly adjusting the resource sizes.
> 
> Signed-off-by: Helge Deller <deller@gmx.de>

This is an updated/cleaner approach to this problem.
Still I want some more testing on it with various machines.

Basically we now extend the LMMIO range up to 256MB above the initial
start of the region if the value of the MASK register seems to allow it.

Signed-off-by: Helge Deller <deller@gmx.de>

diff --git a/drivers/parisc/lba_pci.c b/drivers/parisc/lba_pci.c
index 1f05913..acc3fe8 100644
--- a/drivers/parisc/lba_pci.c
+++ b/drivers/parisc/lba_pci.c
@@ -613,6 +613,46 @@ truncate_pat_collision(struct resource *root, struct resource *new)
 	return 0;	/* truncation successful */
 }
 
+/*
+ * extend_lmmio_len: extend lmmio range to maximum length
+ */
+static unsigned long
+extend_lmmio_len(unsigned long start, unsigned long end, unsigned long lba_len)
+{
+	struct resource *tmp;
+
+	pr_debug("LMMIO mismatch: PAT length = 0x%lx, MASK register = 0x%lx\n",
+		end - start, lba_len);
+
+	lba_len = min(lba_len+1, 256UL*1024*1024); /* limit to 256 MB */
+
+	pr_info("LBA: lmmio_space [0x%lx-0x%lx] - original\n", start, end);
+
+	end += lba_len;
+	if (end < start) /* fix overflow */
+		end = -1ULL;
+
+	pr_debug("LBA: lmmio_space [0x%lx-0x%lx] - current\n", start, end);
+
+	/* first overlap */
+	for (tmp = iomem_resource.child; tmp; tmp = tmp->sibling) {
+		pr_debug("LBA: testing %pR\n", tmp);
+		if (tmp->start == start)
+			continue; /* ignore ourself */
+		if (tmp->end < start)
+			continue;
+		if (tmp->start > end)
+			continue;
+		if (end >= tmp->start)
+			end = tmp->start - 1;
+	}
+
+	pr_info("LBA: lmmio_space [0x%lx-0x%lx] - new\n", start, end);
+
+	/* return new end */
+	return end;
+}
+
 #else
 #define truncate_pat_collision(r,n)  (0)
 #endif
@@ -994,6 +1034,14 @@ lba_pat_resources(struct parisc_device *pa_dev, struct lba_device *lba_dev)
 		case PAT_LMMIO:
 			/* used to fix up pre-initialized MEM BARs */
 			if (!lba_dev->hba.lmmio_space.flags) {
+				unsigned long lba_len;
+
+				lba_len = ~READ_REG32(lba_dev->hba.base_addr
+						+ LBA_LMMIO_MASK);
+				if ((p->end - p->start) != lba_len)
+					p->end = extend_lmmio_len(p->start,
+						p->end, lba_len);
+
 				sprintf(lba_dev->hba.lmmio_name,
 						"PCI%02x LMMIO",
 						(int)lba_dev->hba.bus_num.start);

Fwd: [PATCH] parisc: fix LMMIO mismatch between PAT length and MASK register

[Alex Ivanov]

> =EF=D4: Alex Ivanov <gnidorah@p0n4ik.tk>
> =F4=C5=CD=C1: =EF=D4=D7=C5=D4: [PATCH] parisc: fix LMMIO mismatch bet=
ween PAT length and MASK register
> =E4=C1=D4=C1: 10 =C1=D7=C7=D5=D3=D4=C1 2013 =C7., 23:55:35 GMT+04:00
> =EB=CF=CD=D5: John David Anglin <dave.anglin@bell.net>
>=20
>=20
> 10.08.2013, =D7 23:41, John David Anglin <dave.anglin@bell.net> =CE=C1=
=D0=C9=D3=C1=CC(=C1):
>>=20
>> Have you tried agpmode=3D-1 to force PCI mode.  It seems like this w=
as a problem at one time on ubuntu:
>> http://phoronix.com/forums/showthread.php?17615-Testing-radeon-KMS-o=
n-Ubuntu
>>=20
>> Dave
>> --
>> John David Anglin	dave.anglin@bell.net
>=20
>=20
> John,
>=20
> I've tried this one and many other things (except the messing with en=
dianness) so far. The error is=20
> still there.
>=20
> Thanks.
>=20

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Re: [PATCH] parisc: fix LMMIO mismatch between PAT length and MASK register

[John David Anglin]

On 10-Aug-13, at 3:56 PM, Alex Ivanov wrote:

>> I've tried this one and many other things (except the messing with  
>> endianness) so far. The error is
>> still there.
>


Alex, I don't know which distro your using but I built and uploaded a  
new debian build of mesa and some packages it
depends on to the parisc archive.  Mesa and the open source ATI driver  
build without problems on parisc.  However, this
thread suggests we need to go backwards to resolve the endian issues:
http://forums.gentoo.org/viewtopic-p-7128758.html

I have a RV100 in my rp3440 that I may play a bit with if I get a  
chance.

While this might be a kernel issue, I suggest that the bug needs to be  
filed on the relevant distro package list and
maybe on the package source list as well.

Dave
--
John David Anglin	dave.anglin@bell.net