[parisc-linux] N Class SMP pb ?

[parisc-linux] N Class SMP pb ?

[Joel Soete]

Hi Willy,

I come back to you about your mail: 
<http://lists.parisc-linux.org/pipermail/parisc-linux/2002-March/015827.html>
in which you spoke about "Strech (the memory controller)". Do you have 
more docs about this device?

I put you this question because in "PA 2.0 architecture" book, it is 
mentionned that 'systems' could be equiped with a hardware cache manager 
and so i would like to know if "Strech" is such a device.
Secondarily, is there some hp9000 with such 'hardware cache' manager and 
which one?

btw is there a means to get cache's tags and corresponding physical 
adresses to put it in a table to dump it for each processors (assuming 
that each processor cache are managed independently: don't have yet 
enough clue about this detail) at crash time (to verify if two processor 
do not try to access wrongly the same physical page)?

Thanks in advance,
    Joel