[parisc-linux] Re: [parisc-linux-cvs] 7300LC

[parisc-linux] Re: [parisc-linux-cvs] 7300LC

[Randolph Chung]

willy, kyle found out that this doesn't work:

> > Split out 7300LC from 7100LC and PREFETCH from PA20.

extern inline void prefetchw(const void *addr)
{
        __asm__("ldd 0(%0), %%r0" : : "r" (addr));
}

on pa11 gas won't assemble the ldd insn.

is this supposed to work for pa7300lc? if so we might have to rewrite
prefetchw to use a .word or something...

randolph
-- 
Randolph Chung
Debian GNU/Linux Developer, hppa/ia64 ports
http://www.tausq.org/

Re: [parisc-linux] Re: [parisc-linux-cvs] 7300LC

[John David Anglin]

> willy, kyle found out that this doesn't work:
> 
> > > Split out 7300LC from 7100LC and PREFETCH from PA20.
> 
> extern inline void prefetchw(const void *addr)
> {
>         __asm__("ldd 0(%0), %%r0" : : "r" (addr));
> }
> 
> on pa11 gas won't assemble the ldd insn.

Right.  "ldd" requires pa20.

It looks like the 7300LC is PCX-L2.  I think this is PA 1.1e chip.
<http://www.openpa.net/cpu.html#xl2>.

Dave
-- 
J. David Anglin                                  dave.anglin@nrc-cnrc.gc.ca
National Research Council of Canada              (613) 990-0752 (FAX: 952-6602)

[parisc-linux] Re: [parisc-linux-cvs] 7300LC

[Matthew Wilcox]

On Sun, Apr 25, 2004 at 06:41:11PM -0700, Randolph Chung wrote:
> willy, kyle found out that this doesn't work:
> 
> > > Split out 7300LC from 7100LC and PREFETCH from PA20.
> 
> extern inline void prefetchw(const void *addr)
> {
>         __asm__("ldd 0(%0), %%r0" : : "r" (addr));
> }
> 
> on pa11 gas won't assemble the ldd insn.
> 
> is this supposed to work for pa7300lc? if so we might have to rewrite
> prefetchw to use a .word or something...

It is supposed to work, yes.  I gleaned this information from
http://cpus.hp.com/technical_references/b7300lc.shtml section 2.2.4
The 7300LC ERS (http://ftp.parisc-linux.org/docs/chips/pcxl2_ers.pdf)
is of no help in this matter.  In section 14.5, it says:

  Because the processor does not necessarily stall even with two cache
  misses pending, software prefetching can lead to better performance
  increases than on the PA7100LC. This is because a software prefetch,
  initiated by a load to general register 0, is not treated like a
  load miss by the data cache and therefore can be completed in the
  ``background'' by the hardware and is less likely to cause processor
  stalls.

But, thinking about it, PA7300LC isn't SMP-capable.  Is there any
difference between prefetch-for-read and prefetch-for-write on a
uniprocessor system?  I don't think so.  So possibly we should just
define prefetchw to be the same as prefetch for CONFIG_PA7300LC and
different for CONFIG_PA20.  Makes sense?

-- 
"Next the statesmen will invent cheap lies, putting the blame upon 
the nation that is attacked, and every man will be glad of those
conscience-soothing falsities, and will diligently study them, and refuse
to examine any refutations of them; and thus he will by and by convince 
himself that the war is just, and will thank God for the better sleep 
he enjoys after this process of grotesque self-deception." -- Mark Twain

RE: [parisc-linux] Re: [parisc-linux-cvs] 7300LC

[Joel Soete]

> on pa11 gas won't assemble the ldd insn.

Yes, it doesn't (i test on a b180 which just have a PA7300LC).

Joel

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RE: [parisc-linux] Re: [parisc-linux-cvs] 7300LC

[Jim Hull]

The prefetch for read (using LDW) vs. prefetch for write (using LDD) applies
only to PA2.0 processors.  PA1.1 processors (including the 7300LC), since
they're only 32-bit machines, don't implement LDD (64-bit load).  For PA1.1,
there's only one kind of prefetch, using LDW.

 -- Jim
    HP PA-RISC/Itanium Processor Architect

> -----Original Message-----
> From: parisc-linux-bounces@lists.parisc-linux.org 
> [mailto:parisc-linux-bounces@lists.parisc-linux.org] On 
> Behalf Of Matthew Wilcox
> Sent: Monday, April 26, 2004 4:59 AM
> To: Randolph Chung
> Cc: Matthew Wilcox; parisc-linux@lists.parisc-linux.org
> Subject: [parisc-linux] Re: [parisc-linux-cvs] 7300LC
> 
> 
> On Sun, Apr 25, 2004 at 06:41:11PM -0700, Randolph Chung wrote:
> > willy, kyle found out that this doesn't work:
> > 
> > > > Split out 7300LC from 7100LC and PREFETCH from PA20.
> > 
> > extern inline void prefetchw(const void *addr)
> > {
> >         __asm__("ldd 0(%0), %%r0" : : "r" (addr));
> > }
> > 
> > on pa11 gas won't assemble the ldd insn.
> > 
> > is this supposed to work for pa7300lc? if so we might have 
> to rewrite
> > prefetchw to use a .word or something...
> 
> It is supposed to work, yes.  I gleaned this information from
> http://cpus.hp.com/technical_references/b7300lc.shtml section 2.2.4
> The 7300LC ERS (http://ftp.parisc-linux.org/docs/chips/pcxl2_ers.pdf)
> is of no help in this matter.  In section 14.5, it says:
> 
>   Because the processor does not necessarily stall even with two cache
>   misses pending, software prefetching can lead to better performance
>   increases than on the PA7100LC. This is because a software prefetch,
>   initiated by a load to general register 0, is not treated like a
>   load miss by the data cache and therefore can be completed in the
>   ``background'' by the hardware and is less likely to cause processor
>   stalls.
> 
> But, thinking about it, PA7300LC isn't SMP-capable.  Is there any
> difference between prefetch-for-read and prefetch-for-write on a
> uniprocessor system?  I don't think so.  So possibly we should just
> define prefetchw to be the same as prefetch for CONFIG_PA7300LC and
> different for CONFIG_PA20.  Makes sense?
> 
> -- 
> "Next the statesmen will invent cheap lies, putting the blame upon 
> the nation that is attacked, and every man will be glad of those
> conscience-soothing falsities, and will diligently study 
> them, and refuse
> to examine any refutations of them; and thus he will by and 
> by convince 
> himself that the war is just, and will thank God for the better sleep 
> he enjoys after this process of grotesque self-deception." -- 
> Mark Twain
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