[PATCH] parisc: Fix unalignment handler for fldw and fstw

[PATCH] parisc: Fix unalignment handler for fldw and fstw

[Helge Deller]

This ugly bug has been since forever in the parisc kernel and I wonder
why it wasn't detected earlier. Interestingly I noticed this bug just
because the libime debian package failed to build on *native* hardware,
while it successfully built in qemu.

The instruction "fldw 0(addr),%fr22L" (and the other fldw/fstw
instructions) encode the target register (%fr22) in the rightmost 5
bits. The 7th rightmost bit defines if the left or right half of %fr22
should be used.

While processing unaligned address accesses, the FR3() define is used to
calculate the offset into the floating-point register set.  But the
calculation in FR3() was buggy, so that for example instead of %fr22,
register %fr12 [((22 * 2) & 0x1f) = 12] was used.

Correct the calculation in FR3() to get the correct FP register.

Signed-off-by: Helge Deller <deller@gmx.de>
Cc: <stable@vger.kernel.org>

diff --git a/arch/parisc/kernel/unaligned.c b/arch/parisc/kernel/unaligned.c
index bac581b5ecfc..e8a4d77cff53 100644
--- a/arch/parisc/kernel/unaligned.c
+++ b/arch/parisc/kernel/unaligned.c
@@ -93,7 +93,7 @@
 #define R1(i) (((i)>>21)&0x1f)
 #define R2(i) (((i)>>16)&0x1f)
 #define R3(i) ((i)&0x1f)
-#define FR3(i) ((((i)<<1)&0x1f)|(((i)>>6)&1))
+#define FR3(i) ((((i)&0x1f)<<1)|(((i)>>6)&1))
 #define IM(i,n) (((i)>>1&((1<<(n-1))-1))|((i)&1?((0-1L)<<(n-1)):0))
 #define IM5_2(i) IM((i)>>16,5)
 #define IM5_3(i) IM((i),5)