* [PATCH 01/10] dt-bindings: spmi: Add MediaTek MT8196 SPMI 2 Arbiter/Controllers
2026-01-23 18:20 [PATCH 00/10] spmi: Patches for the merge window Stephen Boyd
@ 2026-01-23 18:20 ` Stephen Boyd
2026-01-23 18:20 ` [PATCH 02/10] spmi: mtk-pmif: Add multi-bus support for SPMI 2.0 Stephen Boyd
` (8 subsequent siblings)
9 siblings, 0 replies; 11+ messages in thread
From: Stephen Boyd @ 2026-01-23 18:20 UTC (permalink / raw)
To: Greg Kroah-Hartman
Cc: AngeloGioacchino Del Regno, linux-kernel, patches,
Rob Herring (Arm), Nícolas F. R. A. Prado
From: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Document the MT8196 SPMI 2.0 Controller with a new schema.
This is a MIPI SPMI 2.0 compliant IP, composed of a main arbiter
and two SPMI master controllers with Request Capable Slave (RCS)
support.
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
---
.../bindings/spmi/mediatek,mt8196-spmi.yaml | 138 ++++++++++++++++++
1 file changed, 138 insertions(+)
create mode 100644 Documentation/devicetree/bindings/spmi/mediatek,mt8196-spmi.yaml
diff --git a/Documentation/devicetree/bindings/spmi/mediatek,mt8196-spmi.yaml b/Documentation/devicetree/bindings/spmi/mediatek,mt8196-spmi.yaml
new file mode 100644
index 000000000000..7a534f0a1d87
--- /dev/null
+++ b/Documentation/devicetree/bindings/spmi/mediatek,mt8196-spmi.yaml
@@ -0,0 +1,138 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/spmi/mediatek,mt8196-spmi.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MediaTek MT8196 SPMI 2.0 Controller
+
+maintainers:
+ - Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com>
+ - AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
+
+description:
+ The MediaTek MT8196 SoC features a SPMI version 2.0 compliant controller,
+ with internal wrapping arbitration logic to allow for multiple on-chip
+ devices to control up to two SPMI buses.
+ The main arbiter also acts as an interrupt controller, arbitering also
+ the interrupts coming from SPMI-connected devices into each of the nested
+ interrupt controllers from any of the present SPMI buses.
+
+properties:
+ compatible:
+ oneOf:
+ - enum:
+ - mediatek,mt8196-spmi
+ - items:
+ - enum:
+ - mediatek,mt6991-spmi
+ - const: mediatek,mt8196-spmi
+
+ ranges: true
+
+ '#address-cells':
+ const: 1
+
+ '#size-cells':
+ const: 1
+
+patternProperties:
+ "^spmi@[a-f0-9]+$":
+ type: object
+ $ref: /schemas/spmi/spmi.yaml
+ unevaluatedProperties: false
+
+ properties:
+ reg:
+ items:
+ - description: controller interface registers
+ - description: spmi master controller registers
+
+ reg-names:
+ items:
+ - const: pmif
+ - const: spmimst
+
+ clocks:
+ items:
+ - description: controller interface system clock
+ - description: controller interface timer clock
+ - description: spmi controller master clock
+
+ clock-names:
+ items:
+ - const: pmif_sys_ck
+ - const: pmif_tmr_ck
+ - const: spmimst_clk_mux
+
+ interrupts:
+ maxItems: 1
+
+ interrupt-names:
+ const: rcs
+
+ interrupt-controller: true
+
+ "#interrupt-cells":
+ const: 3
+ description: |
+ cell 1: slave ID for the requested interrupt (0-15)
+ cell 2: the requested peripheral interrupt (0-7)
+ cell 3: interrupt flags indicating level-sense information,
+ as defined in dt-bindings/interrupt-controller/irq.h
+ required:
+ - reg
+ - reg-names
+ - clocks
+ - clock-names
+ - interrupts
+ - interrupt-names
+ - interrupt-controller
+ - "#interrupt-cells"
+
+required:
+ - compatible
+ - ranges
+ - '#address-cells'
+ - '#size-cells'
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ spmi-arbiter@1c018000 {
+ compatible = "mediatek,mt8196-spmi";
+ ranges = <0 0 0x1c018000 0x4900>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ spmi@0 {
+ reg = <0 0x900>, <0x4800 0x100>;
+ reg-names = "pmif", "spmimst";
+ interrupts-extended = <&pio 292 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "rcs";
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ clocks = <&pmif_sys>, <&pmif_tmr>, <&spmi_mst>;
+ clock-names = "pmif_sys_ck", "pmif_tmr_ck", "spmimst_clk_mux";
+ };
+
+ spmi@2000 {
+ reg = <0x2000 0x900>, <0x4000 0x100>;
+ reg-names = "pmif", "spmimst";
+ interrupts-extended = <&pio 291 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "rcs";
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ clocks = <&pmif_sys>, <&pmif_tmr>, <&spmi_mst>;
+ clock-names = "pmif_sys_ck", "pmif_tmr_ck", "spmimst_clk_mux";
+ };
+ };
+ };
+...
--
https://git.kernel.org/pub/scm/linux/kernel/git/clk/linux.git
https://git.kernel.org/pub/scm/linux/kernel/git/sboyd/spmi.git
^ permalink raw reply related [flat|nested] 11+ messages in thread* [PATCH 02/10] spmi: mtk-pmif: Add multi-bus support for SPMI 2.0
2026-01-23 18:20 [PATCH 00/10] spmi: Patches for the merge window Stephen Boyd
2026-01-23 18:20 ` [PATCH 01/10] dt-bindings: spmi: Add MediaTek MT8196 SPMI 2 Arbiter/Controllers Stephen Boyd
@ 2026-01-23 18:20 ` Stephen Boyd
2026-01-23 18:20 ` [PATCH 03/10] spmi: mtk-pmif: Keep spinlock until read is fully done Stephen Boyd
` (7 subsequent siblings)
9 siblings, 0 replies; 11+ messages in thread
From: Stephen Boyd @ 2026-01-23 18:20 UTC (permalink / raw)
To: Greg Kroah-Hartman
Cc: AngeloGioacchino Del Regno, linux-kernel, patches,
Nícolas F. R. A. Prado
From: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
In preparation for adding support for MT8196/MT6991 SoCs having
multiple SPMI busses, move the bus specific parameters into a new
pmif_bus structure and keep the SoC-specific data in the already
existing struct pmif, and add means to register multiple SPMI
controllers.
While this needs a different devicetree node structure, where each
of the controllers are in subnodes of a main SPMI node, and where
each has its own resources (iospaces and clocks), support for the
legacy single-controller was retained and doesn't require any DT
change in the currently supported SoCs.
Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
---
drivers/spmi/spmi-mtk-pmif.c | 235 +++++++++++++++++++++++------------
1 file changed, 157 insertions(+), 78 deletions(-)
diff --git a/drivers/spmi/spmi-mtk-pmif.c b/drivers/spmi/spmi-mtk-pmif.c
index 160d36f7d238..68f458587c67 100644
--- a/drivers/spmi/spmi-mtk-pmif.c
+++ b/drivers/spmi/spmi-mtk-pmif.c
@@ -1,6 +1,8 @@
// SPDX-License-Identifier: GPL-2.0
//
// Copyright (c) 2021 MediaTek Inc.
+// Copyright (c) 2025 Collabora Ltd
+// AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
#include <linux/clk.h>
#include <linux/iopoll.h>
@@ -25,6 +27,7 @@
#define PMIF_CHAN_OFFSET 0x5
+#define PMIF_MAX_BUSES 2
#define PMIF_MAX_CLKS 3
#define SPMI_OP_ST_BUSY 1
@@ -41,16 +44,22 @@ struct pmif_data {
const u32 *regs;
const u32 *spmimst_regs;
u32 soc_chan;
+ u32 num_spmi_buses;
};
-struct pmif {
+struct pmif_bus {
void __iomem *base;
void __iomem *spmimst_base;
- struct ch_reg chan;
+ struct spmi_controller *ctrl;
struct clk_bulk_data clks[PMIF_MAX_CLKS];
size_t nclks;
+ raw_spinlock_t lock;
+};
+
+struct pmif {
+ struct pmif_bus bus[PMIF_MAX_BUSES];
+ struct ch_reg chan;
const struct pmif_data *data;
- raw_spinlock_t lock;
};
static const char * const pmif_clock_names[] = {
@@ -262,33 +271,41 @@ static const u32 mt8195_spmi_regs[] = {
[SPMI_MST_DBG] = 0x00FC,
};
-static u32 pmif_readl(struct pmif *arb, enum pmif_regs reg)
+static inline struct pmif *to_mtk_pmif(struct spmi_controller *ctrl)
+{
+ return dev_get_drvdata(ctrl->dev.parent);
+}
+
+static u32 pmif_readl(struct pmif *arb, struct pmif_bus *pbus, enum pmif_regs reg)
{
- return readl(arb->base + arb->data->regs[reg]);
+ return readl(pbus->base + arb->data->regs[reg]);
}
-static void pmif_writel(struct pmif *arb, u32 val, enum pmif_regs reg)
+static void pmif_writel(struct pmif *arb, struct pmif_bus *pbus,
+ u32 val, enum pmif_regs reg)
{
- writel(val, arb->base + arb->data->regs[reg]);
+ writel(val, pbus->base + arb->data->regs[reg]);
}
-static void mtk_spmi_writel(struct pmif *arb, u32 val, enum spmi_regs reg)
+static void mtk_spmi_writel(struct pmif *arb, struct pmif_bus *pbus,
+ u32 val, enum spmi_regs reg)
{
- writel(val, arb->spmimst_base + arb->data->spmimst_regs[reg]);
+ writel(val, pbus->spmimst_base + arb->data->spmimst_regs[reg]);
}
-static bool pmif_is_fsm_vldclr(struct pmif *arb)
+static bool pmif_is_fsm_vldclr(struct pmif *arb, struct pmif_bus *pbus)
{
u32 reg_rdata;
- reg_rdata = pmif_readl(arb, arb->chan.ch_sta);
+ reg_rdata = pmif_readl(arb, pbus, arb->chan.ch_sta);
return GET_SWINF(reg_rdata) == SWINF_WFVLDCLR;
}
static int pmif_arb_cmd(struct spmi_controller *ctrl, u8 opc, u8 sid)
{
- struct pmif *arb = spmi_controller_get_drvdata(ctrl);
+ struct pmif_bus *pbus = spmi_controller_get_drvdata(ctrl);
+ struct pmif *arb = to_mtk_pmif(ctrl);
u32 rdata, cmd;
int ret;
@@ -298,8 +315,8 @@ static int pmif_arb_cmd(struct spmi_controller *ctrl, u8 opc, u8 sid)
cmd = opc - SPMI_CMD_RESET;
- mtk_spmi_writel(arb, (cmd << 0x4) | sid, SPMI_OP_ST_CTRL);
- ret = readl_poll_timeout_atomic(arb->spmimst_base + arb->data->spmimst_regs[SPMI_OP_ST_STA],
+ mtk_spmi_writel(arb, pbus, (cmd << 0x4) | sid, SPMI_OP_ST_CTRL);
+ ret = readl_poll_timeout_atomic(pbus->spmimst_base + arb->data->spmimst_regs[SPMI_OP_ST_STA],
rdata, (rdata & SPMI_OP_ST_BUSY) == SPMI_OP_ST_BUSY,
PMIF_DELAY_US, PMIF_TIMEOUT_US);
if (ret < 0)
@@ -311,7 +328,8 @@ static int pmif_arb_cmd(struct spmi_controller *ctrl, u8 opc, u8 sid)
static int pmif_spmi_read_cmd(struct spmi_controller *ctrl, u8 opc, u8 sid,
u16 addr, u8 *buf, size_t len)
{
- struct pmif *arb = spmi_controller_get_drvdata(ctrl);
+ struct pmif_bus *pbus = spmi_controller_get_drvdata(ctrl);
+ struct pmif *arb = to_mtk_pmif(ctrl);
struct ch_reg *inf_reg;
int ret;
u32 data, cmd;
@@ -336,31 +354,31 @@ static int pmif_spmi_read_cmd(struct spmi_controller *ctrl, u8 opc, u8 sid,
else
return -EINVAL;
- raw_spin_lock_irqsave(&arb->lock, flags);
+ raw_spin_lock_irqsave(&pbus->lock, flags);
/* Wait for Software Interface FSM state to be IDLE. */
inf_reg = &arb->chan;
- ret = readl_poll_timeout_atomic(arb->base + arb->data->regs[inf_reg->ch_sta],
+ ret = readl_poll_timeout_atomic(pbus->base + arb->data->regs[inf_reg->ch_sta],
data, GET_SWINF(data) == SWINF_IDLE,
PMIF_DELAY_US, PMIF_TIMEOUT_US);
if (ret < 0) {
/* set channel ready if the data has transferred */
- if (pmif_is_fsm_vldclr(arb))
- pmif_writel(arb, 1, inf_reg->ch_rdy);
- raw_spin_unlock_irqrestore(&arb->lock, flags);
+ if (pmif_is_fsm_vldclr(arb, pbus))
+ pmif_writel(arb, pbus, 1, inf_reg->ch_rdy);
+ raw_spin_unlock_irqrestore(&pbus->lock, flags);
dev_err(&ctrl->dev, "failed to wait for SWINF_IDLE\n");
return ret;
}
/* Send the command. */
cmd = (opc << 30) | (sid << 24) | ((len - 1) << 16) | addr;
- pmif_writel(arb, cmd, inf_reg->ch_send);
- raw_spin_unlock_irqrestore(&arb->lock, flags);
+ pmif_writel(arb, pbus, cmd, inf_reg->ch_send);
+ raw_spin_unlock_irqrestore(&pbus->lock, flags);
/*
* Wait for Software Interface FSM state to be WFVLDCLR,
* read the data and clear the valid flag.
*/
- ret = readl_poll_timeout_atomic(arb->base + arb->data->regs[inf_reg->ch_sta],
+ ret = readl_poll_timeout_atomic(pbus->base + arb->data->regs[inf_reg->ch_sta],
data, GET_SWINF(data) == SWINF_WFVLDCLR,
PMIF_DELAY_US, PMIF_TIMEOUT_US);
if (ret < 0) {
@@ -368,9 +386,9 @@ static int pmif_spmi_read_cmd(struct spmi_controller *ctrl, u8 opc, u8 sid,
return ret;
}
- data = pmif_readl(arb, inf_reg->rdata);
+ data = pmif_readl(arb, pbus, inf_reg->rdata);
memcpy(buf, &data, len);
- pmif_writel(arb, 1, inf_reg->ch_rdy);
+ pmif_writel(arb, pbus, 1, inf_reg->ch_rdy);
return 0;
}
@@ -378,7 +396,8 @@ static int pmif_spmi_read_cmd(struct spmi_controller *ctrl, u8 opc, u8 sid,
static int pmif_spmi_write_cmd(struct spmi_controller *ctrl, u8 opc, u8 sid,
u16 addr, const u8 *buf, size_t len)
{
- struct pmif *arb = spmi_controller_get_drvdata(ctrl);
+ struct pmif_bus *pbus = spmi_controller_get_drvdata(ctrl);
+ struct pmif *arb = to_mtk_pmif(ctrl);
struct ch_reg *inf_reg;
int ret;
u32 data, wdata, cmd;
@@ -409,27 +428,27 @@ static int pmif_spmi_write_cmd(struct spmi_controller *ctrl, u8 opc, u8 sid,
/* Set the write data. */
memcpy(&wdata, buf, len);
- raw_spin_lock_irqsave(&arb->lock, flags);
+ raw_spin_lock_irqsave(&pbus->lock, flags);
/* Wait for Software Interface FSM state to be IDLE. */
inf_reg = &arb->chan;
- ret = readl_poll_timeout_atomic(arb->base + arb->data->regs[inf_reg->ch_sta],
+ ret = readl_poll_timeout_atomic(pbus->base + arb->data->regs[inf_reg->ch_sta],
data, GET_SWINF(data) == SWINF_IDLE,
PMIF_DELAY_US, PMIF_TIMEOUT_US);
if (ret < 0) {
/* set channel ready if the data has transferred */
- if (pmif_is_fsm_vldclr(arb))
- pmif_writel(arb, 1, inf_reg->ch_rdy);
- raw_spin_unlock_irqrestore(&arb->lock, flags);
+ if (pmif_is_fsm_vldclr(arb, pbus))
+ pmif_writel(arb, pbus, 1, inf_reg->ch_rdy);
+ raw_spin_unlock_irqrestore(&pbus->lock, flags);
dev_err(&ctrl->dev, "failed to wait for SWINF_IDLE\n");
return ret;
}
- pmif_writel(arb, wdata, inf_reg->wdata);
+ pmif_writel(arb, pbus, wdata, inf_reg->wdata);
/* Send the command. */
cmd = (opc << 30) | BIT(29) | (sid << 24) | ((len - 1) << 16) | addr;
- pmif_writel(arb, cmd, inf_reg->ch_send);
- raw_spin_unlock_irqrestore(&arb->lock, flags);
+ pmif_writel(arb, pbus, cmd, inf_reg->ch_send);
+ raw_spin_unlock_irqrestore(&pbus->lock, flags);
return 0;
}
@@ -446,84 +465,143 @@ static const struct pmif_data mt8195_pmif_arb = {
.soc_chan = 2,
};
-static int mtk_spmi_probe(struct platform_device *pdev)
+static int mtk_spmi_bus_probe(struct platform_device *pdev,
+ struct device_node *node,
+ const struct pmif_data *pdata,
+ struct pmif_bus *pbus)
{
- struct pmif *arb;
struct spmi_controller *ctrl;
- int err, i;
- u32 chan_offset;
+ int err, idx, bus_id, i;
+
+ if (pdata->num_spmi_buses > 1)
+ bus_id = of_alias_get_id(node, "spmi");
+ else
+ bus_id = 0;
+
+ if (bus_id < 0)
+ return dev_err_probe(&pdev->dev, bus_id,
+ "Cannot find SPMI Bus alias ID\n");
- ctrl = devm_spmi_controller_alloc(&pdev->dev, sizeof(*arb));
+ ctrl = devm_spmi_controller_alloc(&pdev->dev, sizeof(*pbus));
if (IS_ERR(ctrl))
return PTR_ERR(ctrl);
- arb = spmi_controller_get_drvdata(ctrl);
- arb->data = device_get_match_data(&pdev->dev);
- if (!arb->data) {
- dev_err(&pdev->dev, "Cannot get drv_data\n");
+ pbus = spmi_controller_get_drvdata(ctrl);
+ pbus->ctrl = ctrl;
+
+ idx = of_property_match_string(node, "reg-names", "pmif");
+ if (idx < 0)
return -EINVAL;
- }
- arb->base = devm_platform_ioremap_resource_byname(pdev, "pmif");
- if (IS_ERR(arb->base))
- return PTR_ERR(arb->base);
+ pbus->base = devm_of_iomap(&pdev->dev, node, idx, NULL);
+ if (IS_ERR(pbus->base))
+ return PTR_ERR(pbus->base);
- arb->spmimst_base = devm_platform_ioremap_resource_byname(pdev, "spmimst");
- if (IS_ERR(arb->spmimst_base))
- return PTR_ERR(arb->spmimst_base);
+ idx = of_property_match_string(node, "reg-names", "spmimst");
+ if (idx < 0)
+ return -EINVAL;
- arb->nclks = ARRAY_SIZE(pmif_clock_names);
- for (i = 0; i < arb->nclks; i++)
- arb->clks[i].id = pmif_clock_names[i];
+ pbus->spmimst_base = devm_of_iomap(&pdev->dev, node, idx, NULL);
+ if (IS_ERR(pbus->spmimst_base))
+ return PTR_ERR(pbus->spmimst_base);
- err = clk_bulk_get(&pdev->dev, arb->nclks, arb->clks);
- if (err) {
- dev_err(&pdev->dev, "Failed to get clocks: %d\n", err);
- return err;
+ pbus->nclks = ARRAY_SIZE(pmif_clock_names);
+ for (i = 0; i < pbus->nclks; i++) {
+ pbus->clks[i].id = pmif_clock_names[i];
+ pbus->clks[i].clk = of_clk_get_by_name(node, pbus->clks[i].id);
+ if (IS_ERR(pbus->clks[i].clk))
+ return PTR_ERR(pbus->clks[i].clk);
}
- err = clk_bulk_prepare_enable(arb->nclks, arb->clks);
- if (err) {
- dev_err(&pdev->dev, "Failed to enable clocks: %d\n", err);
+ err = clk_bulk_prepare_enable(pbus->nclks, pbus->clks);
+ if (err)
goto err_put_clks;
- }
ctrl->cmd = pmif_arb_cmd;
ctrl->read_cmd = pmif_spmi_read_cmd;
ctrl->write_cmd = pmif_spmi_write_cmd;
+ ctrl->dev.of_node = node;
+ dev_set_name(&ctrl->dev, "spmi-%d", bus_id);
- chan_offset = PMIF_CHAN_OFFSET * arb->data->soc_chan;
- arb->chan.ch_sta = PMIF_SWINF_0_STA + chan_offset;
- arb->chan.wdata = PMIF_SWINF_0_WDATA_31_0 + chan_offset;
- arb->chan.rdata = PMIF_SWINF_0_RDATA_31_0 + chan_offset;
- arb->chan.ch_send = PMIF_SWINF_0_ACC + chan_offset;
- arb->chan.ch_rdy = PMIF_SWINF_0_VLD_CLR + chan_offset;
-
- raw_spin_lock_init(&arb->lock);
-
- platform_set_drvdata(pdev, ctrl);
+ raw_spin_lock_init(&pbus->lock);
err = spmi_controller_add(ctrl);
if (err)
goto err_domain_remove;
+ pbus->ctrl = ctrl;
+
return 0;
err_domain_remove:
- clk_bulk_disable_unprepare(arb->nclks, arb->clks);
+ clk_bulk_disable_unprepare(pbus->nclks, pbus->clks);
err_put_clks:
- clk_bulk_put(arb->nclks, arb->clks);
+ clk_bulk_put(pbus->nclks, pbus->clks);
return err;
}
+static int mtk_spmi_probe(struct platform_device *pdev)
+{
+ struct device_node *node = pdev->dev.of_node;
+ struct pmif *arb;
+ u32 chan_offset;
+ u8 cur_bus = 0;
+ int ret;
+
+ arb = devm_kzalloc(&pdev->dev, sizeof(*arb), GFP_KERNEL);
+ if (!arb)
+ return -ENOMEM;
+
+ arb->data = device_get_match_data(&pdev->dev);
+ if (!arb->data) {
+ dev_err(&pdev->dev, "Cannot get drv_data\n");
+ return -EINVAL;
+ }
+
+ platform_set_drvdata(pdev, arb);
+
+ if (!arb->data->num_spmi_buses) {
+ ret = mtk_spmi_bus_probe(pdev, node, arb->data, &arb->bus[cur_bus]);
+ if (ret)
+ return ret;
+ } else {
+ for_each_available_child_of_node_scoped(node, child) {
+ if (!of_node_name_eq(child, "spmi"))
+ continue;
+
+ ret = mtk_spmi_bus_probe(pdev, child, arb->data,
+ &arb->bus[cur_bus]);
+ if (ret)
+ return ret;
+ cur_bus++;
+ }
+ }
+
+ chan_offset = PMIF_CHAN_OFFSET * arb->data->soc_chan;
+ arb->chan.ch_sta = PMIF_SWINF_0_STA + chan_offset;
+ arb->chan.wdata = PMIF_SWINF_0_WDATA_31_0 + chan_offset;
+ arb->chan.rdata = PMIF_SWINF_0_RDATA_31_0 + chan_offset;
+ arb->chan.ch_send = PMIF_SWINF_0_ACC + chan_offset;
+ arb->chan.ch_rdy = PMIF_SWINF_0_VLD_CLR + chan_offset;
+
+ return 0;
+}
+
static void mtk_spmi_remove(struct platform_device *pdev)
{
- struct spmi_controller *ctrl = platform_get_drvdata(pdev);
- struct pmif *arb = spmi_controller_get_drvdata(ctrl);
+ struct pmif *arb = platform_get_drvdata(pdev);
+ int i;
- spmi_controller_remove(ctrl);
- clk_bulk_disable_unprepare(arb->nclks, arb->clks);
- clk_bulk_put(arb->nclks, arb->clks);
+ for (i = 0; i < PMIF_MAX_BUSES; i++) {
+ struct pmif_bus *pbus = &arb->bus[i];
+
+ if (!pbus->ctrl)
+ continue;
+
+ spmi_controller_remove(pbus->ctrl);
+ clk_bulk_disable_unprepare(pbus->nclks, pbus->clks);
+ clk_bulk_put(pbus->nclks, pbus->clks);
+ }
}
static const struct of_device_id mtk_spmi_match_table[] = {
@@ -549,6 +627,7 @@ static struct platform_driver mtk_spmi_driver = {
};
module_platform_driver(mtk_spmi_driver);
+MODULE_AUTHOR("AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>");
MODULE_AUTHOR("Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com>");
MODULE_DESCRIPTION("MediaTek SPMI Driver");
MODULE_LICENSE("GPL");
--
https://git.kernel.org/pub/scm/linux/kernel/git/clk/linux.git
https://git.kernel.org/pub/scm/linux/kernel/git/sboyd/spmi.git
^ permalink raw reply related [flat|nested] 11+ messages in thread* [PATCH 03/10] spmi: mtk-pmif: Keep spinlock until read is fully done
2026-01-23 18:20 [PATCH 00/10] spmi: Patches for the merge window Stephen Boyd
2026-01-23 18:20 ` [PATCH 01/10] dt-bindings: spmi: Add MediaTek MT8196 SPMI 2 Arbiter/Controllers Stephen Boyd
2026-01-23 18:20 ` [PATCH 02/10] spmi: mtk-pmif: Add multi-bus support for SPMI 2.0 Stephen Boyd
@ 2026-01-23 18:20 ` Stephen Boyd
2026-01-23 18:20 ` [PATCH 04/10] spmi: mtk-pmif: Implement Request Capable Slave (RCS) interrupt Stephen Boyd
` (6 subsequent siblings)
9 siblings, 0 replies; 11+ messages in thread
From: Stephen Boyd @ 2026-01-23 18:20 UTC (permalink / raw)
To: Greg Kroah-Hartman
Cc: AngeloGioacchino Del Regno, linux-kernel, patches,
Nícolas F. R. A. Prado, Chen-Yu Tsai
From: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Move the spin unlocking to after reading the contents of the
PMIF_SWINF_(x)_RDATA_31_0 register in pmif_spmi_read_cmd():
since this is the only register that we can read to get the
data from all of the arbitered busses, a concurrent request
for reading (especially on a busy arbiter) will show a race
condition and a unexpected or corrupted value may be read.
Doing the entire read sequence while spin locked guarantees
that concurrent access to the arbiter doesn't happen.
Fixes: f200fff8d019 ("spmi: mtk-pmif: Serialize PMIF status check and command submission")
Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
---
drivers/spmi/spmi-mtk-pmif.c | 8 +++++---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/drivers/spmi/spmi-mtk-pmif.c b/drivers/spmi/spmi-mtk-pmif.c
index 68f458587c67..9f416b231ab8 100644
--- a/drivers/spmi/spmi-mtk-pmif.c
+++ b/drivers/spmi/spmi-mtk-pmif.c
@@ -22,7 +22,7 @@
#define PMIF_CMD_EXT_REG 2
#define PMIF_CMD_EXT_REG_LONG 3
-#define PMIF_DELAY_US 10
+#define PMIF_DELAY_US 2
#define PMIF_TIMEOUT_US (10 * 1000)
#define PMIF_CHAN_OFFSET 0x5
@@ -372,7 +372,6 @@ static int pmif_spmi_read_cmd(struct spmi_controller *ctrl, u8 opc, u8 sid,
/* Send the command. */
cmd = (opc << 30) | (sid << 24) | ((len - 1) << 16) | addr;
pmif_writel(arb, pbus, cmd, inf_reg->ch_send);
- raw_spin_unlock_irqrestore(&pbus->lock, flags);
/*
* Wait for Software Interface FSM state to be WFVLDCLR,
@@ -382,13 +381,16 @@ static int pmif_spmi_read_cmd(struct spmi_controller *ctrl, u8 opc, u8 sid,
data, GET_SWINF(data) == SWINF_WFVLDCLR,
PMIF_DELAY_US, PMIF_TIMEOUT_US);
if (ret < 0) {
+ raw_spin_unlock_irqrestore(&pbus->lock, flags);
dev_err(&ctrl->dev, "failed to wait for SWINF_WFVLDCLR\n");
return ret;
}
data = pmif_readl(arb, pbus, inf_reg->rdata);
- memcpy(buf, &data, len);
pmif_writel(arb, pbus, 1, inf_reg->ch_rdy);
+ raw_spin_unlock_irqrestore(&pbus->lock, flags);
+
+ memcpy(buf, &data, len);
return 0;
}
--
https://git.kernel.org/pub/scm/linux/kernel/git/clk/linux.git
https://git.kernel.org/pub/scm/linux/kernel/git/sboyd/spmi.git
^ permalink raw reply related [flat|nested] 11+ messages in thread* [PATCH 04/10] spmi: mtk-pmif: Implement Request Capable Slave (RCS) interrupt
2026-01-23 18:20 [PATCH 00/10] spmi: Patches for the merge window Stephen Boyd
` (2 preceding siblings ...)
2026-01-23 18:20 ` [PATCH 03/10] spmi: mtk-pmif: Keep spinlock until read is fully done Stephen Boyd
@ 2026-01-23 18:20 ` Stephen Boyd
2026-01-23 18:20 ` [PATCH 05/10] spmi: mtk-pmif: Add support for MT8196 SPMI Controller Stephen Boyd
` (5 subsequent siblings)
9 siblings, 0 replies; 11+ messages in thread
From: Stephen Boyd @ 2026-01-23 18:20 UTC (permalink / raw)
To: Greg Kroah-Hartman
Cc: AngeloGioacchino Del Regno, linux-kernel, patches,
Nícolas F. R. A. Prado
From: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Add support for the per-bus RCS interrupt by adding a new linear
irqdomain and its irqchip.
The SPMI controller will raise an interrupt when any of the SPMI
connected devices' irq needs attention (whenever any interrupt
fires on any SID) in one of four registers, where each register
holds four sets of four bits of information about a SID interrupt.
This controller's RCS interrupt status knowledge is limited to the
address of the SID that raised an interrupt, but does not have any
details about the devices irq numbers: as this may change with a
future SPMI controller IP version, the devicetree is meant to hold
three cells, where the first one is the SPMI SID interrupt number,
the second one is a device interrupt number, and the third one is
the irq sense type.
Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
---
drivers/spmi/spmi-mtk-pmif.c | 232 ++++++++++++++++++++++++++++++++++-
1 file changed, 226 insertions(+), 6 deletions(-)
diff --git a/drivers/spmi/spmi-mtk-pmif.c b/drivers/spmi/spmi-mtk-pmif.c
index 9f416b231ab8..624611dd4849 100644
--- a/drivers/spmi/spmi-mtk-pmif.c
+++ b/drivers/spmi/spmi-mtk-pmif.c
@@ -5,12 +5,17 @@
// AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
#include <linux/clk.h>
+#include <linux/interrupt.h>
#include <linux/iopoll.h>
+#include <linux/irq.h>
+#include <linux/irqdomain.h>
#include <linux/module.h>
#include <linux/of.h>
+#include <linux/of_irq.h>
#include <linux/platform_device.h>
#include <linux/property.h>
#include <linux/spmi.h>
+#include <linux/irqchip/chained_irq.h>
#define SWINF_IDLE 0x00
#define SWINF_WFVLDCLR 0x06
@@ -26,6 +31,7 @@
#define PMIF_TIMEOUT_US (10 * 1000)
#define PMIF_CHAN_OFFSET 0x5
+#define PMIF_RCS_IRQ_MASK GENMASK(7, 0)
#define PMIF_MAX_BUSES 2
#define PMIF_MAX_CLKS 3
@@ -44,6 +50,7 @@ struct pmif_data {
const u32 *regs;
const u32 *spmimst_regs;
u32 soc_chan;
+ u8 spmi_ver;
u32 num_spmi_buses;
};
@@ -51,8 +58,13 @@ struct pmif_bus {
void __iomem *base;
void __iomem *spmimst_base;
struct spmi_controller *ctrl;
+ struct irq_domain *dom;
+ int irq;
struct clk_bulk_data clks[PMIF_MAX_CLKS];
size_t nclks;
+ u8 irq_min_sid;
+ u8 irq_max_sid;
+ u16 irq_en;
raw_spinlock_t lock;
};
@@ -287,6 +299,11 @@ static void pmif_writel(struct pmif *arb, struct pmif_bus *pbus,
writel(val, pbus->base + arb->data->regs[reg]);
}
+static u32 mtk_spmi_readl(struct pmif *arb, struct pmif_bus *pbus, enum spmi_regs reg)
+{
+ return readl(pbus->spmimst_base + arb->data->spmimst_regs[reg]);
+}
+
static void mtk_spmi_writel(struct pmif *arb, struct pmif_bus *pbus,
u32 val, enum spmi_regs reg)
{
@@ -343,7 +360,6 @@ static int pmif_spmi_read_cmd(struct spmi_controller *ctrl, u8 opc, u8 sid,
if (len > 4) {
dev_err(&ctrl->dev, "pmif supports 1..4 bytes per trans, but:%zu requested", len);
-
return -EINVAL;
}
@@ -455,6 +471,159 @@ static int pmif_spmi_write_cmd(struct spmi_controller *ctrl, u8 opc, u8 sid,
return 0;
}
+static void mtk_spmi_handle_chained_irq(struct irq_desc *desc)
+{
+ struct pmif_bus *pbus = irq_desc_get_handler_data(desc);
+ struct irq_chip *chip = irq_desc_get_chip(desc);
+ struct pmif *arb = to_mtk_pmif(pbus->ctrl);
+ u8 regidx_min, regidx_max;
+ bool irq_handled = false;
+ unsigned int i;
+
+ regidx_min = pbus->irq_min_sid / 4;
+ regidx_min += SPMI_SLV_3_0_EINT;
+
+ regidx_max = pbus->irq_max_sid / 4;
+ regidx_max += SPMI_SLV_3_0_EINT;
+
+ chained_irq_enter(chip, desc);
+
+ for (i = regidx_min; i <= regidx_max; i++) {
+ u32 val = mtk_spmi_readl(arb, pbus, i);
+
+ while (val) {
+ u8 bit = __ffs(val);
+ u8 bank = bit / 7;
+ u8 sid = ((i - SPMI_SLV_3_0_EINT) * 4) + bank;
+
+ val &= ~(PMIF_RCS_IRQ_MASK << (8 * bank));
+
+ /* Check if IRQs for this SID are enabled */
+ if (!(pbus->irq_en & BIT(sid)))
+ continue;
+
+ generic_handle_domain_irq_safe(pbus->dom, sid);
+ irq_handled = true;
+ }
+ }
+
+ if (!irq_handled)
+ handle_bad_irq(desc);
+
+ chained_irq_exit(chip, desc);
+}
+
+static void mtk_spmi_rcs_irq_eoi(struct irq_data *d)
+{
+ struct pmif_bus *pbus = irq_data_get_irq_chip_data(d);
+ struct pmif *arb = to_mtk_pmif(pbus->ctrl);
+ irq_hw_number_t irq = irqd_to_hwirq(d);
+ unsigned int reg, shift;
+
+ /* There are four interrupts (8 bits each) per register */
+ reg = SPMI_SLV_3_0_EINT + d->hwirq / 4;
+ shift = (irq % 4) * 8;
+
+ mtk_spmi_writel(arb, pbus, PMIF_RCS_IRQ_MASK << shift, reg);
+}
+
+static void mtk_spmi_rcs_irq_enable(struct irq_data *d)
+{
+ struct pmif_bus *pbus = irq_data_get_irq_chip_data(d);
+ irq_hw_number_t irq = irqd_to_hwirq(d);
+
+ pbus->irq_en |= BIT(irq);
+}
+
+static void mtk_spmi_rcs_irq_disable(struct irq_data *d)
+{
+ struct pmif_bus *pbus = irq_data_get_irq_chip_data(d);
+ irq_hw_number_t irq = irqd_to_hwirq(d);
+
+ pbus->irq_en &= ~BIT(irq);
+}
+
+static int mtk_spmi_rcs_irq_set_wake(struct irq_data *d, unsigned int on)
+{
+ struct pmif_bus *pbus = irq_data_get_irq_chip_data(d);
+
+ return irq_set_irq_wake(pbus->irq, on);
+}
+
+static const struct irq_chip mtk_spmi_rcs_irq_chip = {
+ .name = "spmi_rcs",
+ .irq_eoi = mtk_spmi_rcs_irq_eoi,
+ .irq_enable = mtk_spmi_rcs_irq_enable,
+ .irq_disable = mtk_spmi_rcs_irq_disable,
+ .irq_set_wake = mtk_spmi_rcs_irq_set_wake,
+};
+
+static int mtk_spmi_rcs_irq_translate(struct irq_domain *d, struct irq_fwspec *fwspec,
+ unsigned long *out_hwirq, unsigned int *out_type)
+{
+ struct pmif_bus *pbus = d->host_data;
+ struct device *dev = &pbus->ctrl->dev;
+ u32 *intspec = fwspec->param;
+
+ if (intspec[0] > SPMI_MAX_SLAVE_ID)
+ return -EINVAL;
+
+ /*
+ * The IRQ number in intspec[1] is ignored on purpose here!
+ *
+ * The controller only has knowledge of which SID raised an interrupt
+ * and the type of irq, but doesn't know about any device irq number,
+ * hence that must be read from the SPMI device's registers.
+ */
+ *out_hwirq = intspec[0];
+ *out_type = intspec[2] & IRQ_TYPE_SENSE_MASK;
+
+ if (pbus->irq_min_sid > intspec[0])
+ pbus->irq_min_sid = intspec[0];
+
+ if (pbus->irq_max_sid < intspec[0])
+ pbus->irq_max_sid = intspec[0];
+
+ dev_dbg(dev, "Found SPMI IRQ %u (map: 0x%lx)\n", intspec[0], *out_hwirq);
+
+ return 0;
+}
+
+static struct lock_class_key mtk_spmi_rcs_irqlock_class, mtk_spmi_rcs_irqreq_class;
+
+static int mtk_spmi_rcs_irq_alloc(struct irq_domain *d, unsigned int virq,
+ unsigned int nr_irqs, void *data)
+{
+ struct pmif_bus *pbus = d->host_data;
+ struct device *dev = &pbus->ctrl->dev;
+ struct irq_fwspec *fwspec = data;
+ irq_hw_number_t hwirq;
+ unsigned int irqtype;
+ int i, ret;
+
+ ret = mtk_spmi_rcs_irq_translate(d, fwspec, &hwirq, &irqtype);
+ if (ret)
+ return ret;
+
+ for (i = 0; i < nr_irqs; i++) {
+ dev_dbg(dev, "Mapping IRQ%u (hwirq %lu) with type %u\n",
+ virq, hwirq, irqtype);
+
+ irq_set_lockdep_class(virq, &mtk_spmi_rcs_irqlock_class,
+ &mtk_spmi_rcs_irqreq_class);
+ irq_domain_set_info(d, virq, hwirq, &mtk_spmi_rcs_irq_chip,
+ pbus, handle_level_irq, NULL, NULL);
+ }
+
+ return 0;
+}
+
+static const struct irq_domain_ops mtk_spmi_rcs_irq_domain_ops = {
+ .alloc = mtk_spmi_rcs_irq_alloc,
+ .free = irq_domain_free_irqs_common,
+ .translate = mtk_spmi_rcs_irq_translate,
+};
+
static const struct pmif_data mt6873_pmif_arb = {
.regs = mt6873_regs,
.spmimst_regs = mt6873_spmi_regs,
@@ -467,6 +636,44 @@ static const struct pmif_data mt8195_pmif_arb = {
.soc_chan = 2,
};
+static int mtk_spmi_irq_init(struct device_node *node,
+ const struct pmif_data *pdata,
+ struct pmif_bus *pbus)
+{
+ struct pmif *arb = to_mtk_pmif(pbus->ctrl);
+ unsigned int i;
+
+ /* No interrupts required for SPMI 1.x controller */
+ if (pdata->spmi_ver < 2) {
+ pbus->dom = NULL;
+ return 0;
+ }
+
+ pbus->irq = of_irq_get_byname(node, "rcs");
+ if (pbus->irq <= 0)
+ return pbus->irq ? : -ENXIO;
+
+ pbus->dom = irq_domain_create_tree(of_fwnode_handle(node),
+ &mtk_spmi_rcs_irq_domain_ops, pbus);
+ if (!pbus->dom)
+ return -ENOMEM;
+
+ /* Clear possible unhandled interrupts coming from bootloader SPMI init */
+ for (i = SPMI_SLV_3_0_EINT; i <= SPMI_SLV_F_C_EINT; i++)
+ mtk_spmi_writel(arb, pbus, GENMASK(31, 0), i);
+
+ return 0;
+}
+
+static void mtk_spmi_irq_remove(struct pmif_bus *pbus)
+{
+ if (!pbus->dom)
+ return;
+
+ irq_set_chained_handler_and_data(pbus->irq, NULL, NULL);
+ irq_domain_remove(pbus->dom);
+}
+
static int mtk_spmi_bus_probe(struct platform_device *pdev,
struct device_node *node,
const struct pmif_data *pdata,
@@ -512,12 +719,21 @@ static int mtk_spmi_bus_probe(struct platform_device *pdev,
pbus->clks[i].id = pmif_clock_names[i];
pbus->clks[i].clk = of_clk_get_by_name(node, pbus->clks[i].id);
if (IS_ERR(pbus->clks[i].clk))
- return PTR_ERR(pbus->clks[i].clk);
+ return dev_err_probe(&pdev->dev, PTR_ERR(pbus->clks[i].clk),
+ "Failed to get clocks\n");
}
err = clk_bulk_prepare_enable(pbus->nclks, pbus->clks);
- if (err)
+ if (err) {
+ dev_err_probe(&pdev->dev, err, "Failed to enable clocks\n");
goto err_put_clks;
+ }
+
+ err = mtk_spmi_irq_init(node, pdata, pbus);
+ if (err) {
+ dev_err_probe(&pdev->dev, err, "Cannot initialize SPMI IRQs\n");
+ goto err_disable_clks;
+ }
ctrl->cmd = pmif_arb_cmd;
ctrl->read_cmd = pmif_spmi_read_cmd;
@@ -529,13 +745,16 @@ static int mtk_spmi_bus_probe(struct platform_device *pdev,
err = spmi_controller_add(ctrl);
if (err)
- goto err_domain_remove;
+ goto err_remove_irq;
- pbus->ctrl = ctrl;
+ if (pbus->dom)
+ irq_set_chained_handler_and_data(pbus->irq, mtk_spmi_handle_chained_irq, pbus);
return 0;
-err_domain_remove:
+err_remove_irq:
+ mtk_spmi_irq_remove(pbus);
+err_disable_clks:
clk_bulk_disable_unprepare(pbus->nclks, pbus->clks);
err_put_clks:
clk_bulk_put(pbus->nclks, pbus->clks);
@@ -600,6 +819,7 @@ static void mtk_spmi_remove(struct platform_device *pdev)
if (!pbus->ctrl)
continue;
+ mtk_spmi_irq_remove(pbus);
spmi_controller_remove(pbus->ctrl);
clk_bulk_disable_unprepare(pbus->nclks, pbus->clks);
clk_bulk_put(pbus->nclks, pbus->clks);
--
https://git.kernel.org/pub/scm/linux/kernel/git/clk/linux.git
https://git.kernel.org/pub/scm/linux/kernel/git/sboyd/spmi.git
^ permalink raw reply related [flat|nested] 11+ messages in thread* [PATCH 05/10] spmi: mtk-pmif: Add support for MT8196 SPMI Controller
2026-01-23 18:20 [PATCH 00/10] spmi: Patches for the merge window Stephen Boyd
` (3 preceding siblings ...)
2026-01-23 18:20 ` [PATCH 04/10] spmi: mtk-pmif: Implement Request Capable Slave (RCS) interrupt Stephen Boyd
@ 2026-01-23 18:20 ` Stephen Boyd
2026-01-23 18:20 ` [PATCH 06/10] spmi: apple: Add "apple,t8103-spmi" compatible Stephen Boyd
` (4 subsequent siblings)
9 siblings, 0 replies; 11+ messages in thread
From: Stephen Boyd @ 2026-01-23 18:20 UTC (permalink / raw)
To: Greg Kroah-Hartman
Cc: AngeloGioacchino Del Regno, linux-kernel, patches,
Nícolas F. R. A. Prado
From: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Add support for the SPMI controller found in the MT8196 SoC:
this supports SPMI 2.0 and features two SPMI buses.
Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
---
drivers/spmi/spmi-mtk-pmif.c | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/drivers/spmi/spmi-mtk-pmif.c b/drivers/spmi/spmi-mtk-pmif.c
index 624611dd4849..1048420b5afb 100644
--- a/drivers/spmi/spmi-mtk-pmif.c
+++ b/drivers/spmi/spmi-mtk-pmif.c
@@ -636,6 +636,14 @@ static const struct pmif_data mt8195_pmif_arb = {
.soc_chan = 2,
};
+static const struct pmif_data mt8196_pmif_arb = {
+ .regs = mt8195_regs,
+ .spmimst_regs = mt8195_spmi_regs,
+ .soc_chan = 2,
+ .spmi_ver = 2,
+ .num_spmi_buses = 2,
+};
+
static int mtk_spmi_irq_init(struct device_node *node,
const struct pmif_data *pdata,
struct pmif_bus *pbus)
@@ -833,6 +841,9 @@ static const struct of_device_id mtk_spmi_match_table[] = {
}, {
.compatible = "mediatek,mt8195-spmi",
.data = &mt8195_pmif_arb,
+ }, {
+ .compatible = "mediatek,mt8196-spmi",
+ .data = &mt8196_pmif_arb,
}, {
/* sentinel */
},
--
https://git.kernel.org/pub/scm/linux/kernel/git/clk/linux.git
https://git.kernel.org/pub/scm/linux/kernel/git/sboyd/spmi.git
^ permalink raw reply related [flat|nested] 11+ messages in thread* [PATCH 06/10] spmi: apple: Add "apple,t8103-spmi" compatible
2026-01-23 18:20 [PATCH 00/10] spmi: Patches for the merge window Stephen Boyd
` (4 preceding siblings ...)
2026-01-23 18:20 ` [PATCH 05/10] spmi: mtk-pmif: Add support for MT8196 SPMI Controller Stephen Boyd
@ 2026-01-23 18:20 ` Stephen Boyd
2026-01-23 18:20 ` [PATCH 07/10] dt-bindings: spmi: split out common QCOM SPMI PMIC arbiter properties Stephen Boyd
` (3 subsequent siblings)
9 siblings, 0 replies; 11+ messages in thread
From: Stephen Boyd @ 2026-01-23 18:20 UTC (permalink / raw)
To: Greg Kroah-Hartman
Cc: Janne Grunau, linux-kernel, patches, stable, Neal Gompa
From: Janne Grunau <j@jannau.net>
After discussion with the devicetree maintainers we agreed to not extend
lists with the generic compatible "apple,spmi" anymore [1]. Use
"apple,t8103-spmi" as base compatible as it is the SoC the driver and
bindings were written for.
[1]: https://lore.kernel.org/asahi/12ab93b7-1fc2-4ce0-926e-c8141cfe81bf@kernel.org/
Fixes: 77ca75e80c71 ("spmi: add a spmi driver for Apple SoC")
Cc: stable@vger.kernel.org
Reviewed-by: Neal Gompa <neal@gompa.dev>
Signed-off-by: Janne Grunau <j@jannau.net>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
---
drivers/spmi/spmi-apple-controller.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/spmi/spmi-apple-controller.c b/drivers/spmi/spmi-apple-controller.c
index 697b3e8bb023..87e3ee9d4f2a 100644
--- a/drivers/spmi/spmi-apple-controller.c
+++ b/drivers/spmi/spmi-apple-controller.c
@@ -149,6 +149,7 @@ static int apple_spmi_probe(struct platform_device *pdev)
}
static const struct of_device_id apple_spmi_match_table[] = {
+ { .compatible = "apple,t8103-spmi", },
{ .compatible = "apple,spmi", },
{}
};
--
https://git.kernel.org/pub/scm/linux/kernel/git/clk/linux.git
https://git.kernel.org/pub/scm/linux/kernel/git/sboyd/spmi.git
^ permalink raw reply related [flat|nested] 11+ messages in thread* [PATCH 07/10] dt-bindings: spmi: split out common QCOM SPMI PMIC arbiter properties
2026-01-23 18:20 [PATCH 00/10] spmi: Patches for the merge window Stephen Boyd
` (5 preceding siblings ...)
2026-01-23 18:20 ` [PATCH 06/10] spmi: apple: Add "apple,t8103-spmi" compatible Stephen Boyd
@ 2026-01-23 18:20 ` Stephen Boyd
2026-01-23 18:20 ` [PATCH 08/10] dt-bindings: spmi: add support for glymur-spmi-pmic-arb (arbiter v8) Stephen Boyd
` (2 subsequent siblings)
9 siblings, 0 replies; 11+ messages in thread
From: Stephen Boyd @ 2026-01-23 18:20 UTC (permalink / raw)
To: Greg Kroah-Hartman
Cc: Jishnu Prakash, linux-kernel, patches, Rob Herring (Arm)
From: Jishnu Prakash <jishnu.prakash@oss.qualcomm.com>
Split out the common SPMI PMIC arbiter properties for QCOM devices into a
separate file so that it can be included as a reference for devices
using them. This will be needed for the upcoming PMIC v8 arbiter
support patch, as the v8 arbiter also uses these common properties.
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Jishnu Prakash <jishnu.prakash@oss.qualcomm.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
---
.../spmi/qcom,spmi-pmic-arb-common.yaml | 35 +++++++++++++++++++
.../bindings/spmi/qcom,spmi-pmic-arb.yaml | 17 +--------
.../spmi/qcom,x1e80100-spmi-pmic-arb.yaml | 21 +++--------
3 files changed, 40 insertions(+), 33 deletions(-)
create mode 100644 Documentation/devicetree/bindings/spmi/qcom,spmi-pmic-arb-common.yaml
diff --git a/Documentation/devicetree/bindings/spmi/qcom,spmi-pmic-arb-common.yaml b/Documentation/devicetree/bindings/spmi/qcom,spmi-pmic-arb-common.yaml
new file mode 100644
index 000000000000..8c38ed145e74
--- /dev/null
+++ b/Documentation/devicetree/bindings/spmi/qcom,spmi-pmic-arb-common.yaml
@@ -0,0 +1,35 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/spmi/qcom,spmi-pmic-arb-common.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Technologies, Inc. SPMI Controller (common)
+
+maintainers:
+ - David Collins <david.collins@oss.qualcomm.com>
+
+description: |
+ This defines some common properties used to define Qualcomm SPMI controllers
+ for PMIC arbiter.
+
+properties:
+ qcom,ee:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ minimum: 0
+ maximum: 5
+ description:
+ indicates the active Execution Environment identifier
+
+ qcom,channel:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ minimum: 0
+ maximum: 5
+ description:
+ which of the PMIC Arb provided channels to use for accesses
+
+required:
+ - qcom,ee
+ - qcom,channel
+
+additionalProperties: true
diff --git a/Documentation/devicetree/bindings/spmi/qcom,spmi-pmic-arb.yaml b/Documentation/devicetree/bindings/spmi/qcom,spmi-pmic-arb.yaml
index 51daf1b847a9..d0c683dd5284 100644
--- a/Documentation/devicetree/bindings/spmi/qcom,spmi-pmic-arb.yaml
+++ b/Documentation/devicetree/bindings/spmi/qcom,spmi-pmic-arb.yaml
@@ -19,6 +19,7 @@ description: |
allOf:
- $ref: spmi.yaml
+ - $ref: qcom,spmi-pmic-arb-common.yaml
properties:
compatible:
@@ -71,20 +72,6 @@ properties:
'#size-cells': true
- qcom,ee:
- $ref: /schemas/types.yaml#/definitions/uint32
- minimum: 0
- maximum: 5
- description: >
- indicates the active Execution Environment identifier
-
- qcom,channel:
- $ref: /schemas/types.yaml#/definitions/uint32
- minimum: 0
- maximum: 5
- description: >
- which of the PMIC Arb provided channels to use for accesses
-
qcom,bus-id:
$ref: /schemas/types.yaml#/definitions/uint32
minimum: 0
@@ -97,8 +84,6 @@ properties:
required:
- compatible
- reg-names
- - qcom,ee
- - qcom,channel
unevaluatedProperties: false
diff --git a/Documentation/devicetree/bindings/spmi/qcom,x1e80100-spmi-pmic-arb.yaml b/Documentation/devicetree/bindings/spmi/qcom,x1e80100-spmi-pmic-arb.yaml
index 7c3cc20a80d6..08369fdd2161 100644
--- a/Documentation/devicetree/bindings/spmi/qcom,x1e80100-spmi-pmic-arb.yaml
+++ b/Documentation/devicetree/bindings/spmi/qcom,x1e80100-spmi-pmic-arb.yaml
@@ -17,6 +17,9 @@ description: |
The PMIC Arbiter can also act as an interrupt controller, providing interrupts
to slave devices.
+allOf:
+ - $ref: qcom,spmi-pmic-arb-common.yaml
+
properties:
compatible:
oneOf:
@@ -45,20 +48,6 @@ properties:
'#size-cells':
const: 2
- qcom,ee:
- $ref: /schemas/types.yaml#/definitions/uint32
- minimum: 0
- maximum: 5
- description: >
- indicates the active Execution Environment identifier
-
- qcom,channel:
- $ref: /schemas/types.yaml#/definitions/uint32
- minimum: 0
- maximum: 5
- description: >
- which of the PMIC Arb provided channels to use for accesses
-
patternProperties:
"^spmi@[a-f0-9]+$":
type: object
@@ -96,10 +85,8 @@ patternProperties:
required:
- compatible
- reg-names
- - qcom,ee
- - qcom,channel
-additionalProperties: false
+unevaluatedProperties: false
examples:
- |
--
https://git.kernel.org/pub/scm/linux/kernel/git/clk/linux.git
https://git.kernel.org/pub/scm/linux/kernel/git/sboyd/spmi.git
^ permalink raw reply related [flat|nested] 11+ messages in thread* [PATCH 08/10] dt-bindings: spmi: add support for glymur-spmi-pmic-arb (arbiter v8)
2026-01-23 18:20 [PATCH 00/10] spmi: Patches for the merge window Stephen Boyd
` (6 preceding siblings ...)
2026-01-23 18:20 ` [PATCH 07/10] dt-bindings: spmi: split out common QCOM SPMI PMIC arbiter properties Stephen Boyd
@ 2026-01-23 18:20 ` Stephen Boyd
2026-01-23 18:20 ` [PATCH 09/10] spmi: spmi-pmic-arb: add support for PMIC arbiter v8 Stephen Boyd
2026-01-23 18:20 ` [PATCH 10/10] dt-bindings: spmi: spmi-mtk-pmif: Add compatible for MT8189 SoC Stephen Boyd
9 siblings, 0 replies; 11+ messages in thread
From: Stephen Boyd @ 2026-01-23 18:20 UTC (permalink / raw)
To: Greg Kroah-Hartman
Cc: Jishnu Prakash, linux-kernel, patches, David Collins,
Pankaj Patil, Kamal Wadhwa, Jingyi Wang, Rob Herring (Arm)
From: Jishnu Prakash <jishnu.prakash@oss.qualcomm.com>
SPMI PMIC Arbiter version 8 builds upon version 7 with support for
up to four SPMI buses. To achieve this, the register map was
slightly rearranged. Add a new binding file and compatible string
for version 8 using the name 'glymur' as the Qualcomm Technologies,
Inc. Glymur SoC is the first one to use PMIC arbiter version 8. This
specifies the new register ranges needed only for version 8.
Also document SPMI PMIC Arbiter for Qualcomm Kaanapali SoC, by adding
fallback to Glymur compatible string, as it too has version 8
functionality.
Signed-off-by: David Collins <david.collins@oss.qualcomm.com>
Signed-off-by: Pankaj Patil <pankaj.patil@oss.qualcomm.com>
Signed-off-by: Kamal Wadhwa <kamal.wadhwa@oss.qualcomm.com>
Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Jishnu Prakash <jishnu.prakash@oss.qualcomm.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
---
.../spmi/qcom,glymur-spmi-pmic-arb.yaml | 150 ++++++++++++++++++
1 file changed, 150 insertions(+)
create mode 100644 Documentation/devicetree/bindings/spmi/qcom,glymur-spmi-pmic-arb.yaml
diff --git a/Documentation/devicetree/bindings/spmi/qcom,glymur-spmi-pmic-arb.yaml b/Documentation/devicetree/bindings/spmi/qcom,glymur-spmi-pmic-arb.yaml
new file mode 100644
index 000000000000..3b5005b96c6d
--- /dev/null
+++ b/Documentation/devicetree/bindings/spmi/qcom,glymur-spmi-pmic-arb.yaml
@@ -0,0 +1,150 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/spmi/qcom,glymur-spmi-pmic-arb.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Technologies, Inc. Glymur SPMI Controller (PMIC Arbiter v8)
+
+maintainers:
+ - David Collins <david.collins@oss.qualcomm.com>
+
+description: |
+ The Glymur SPMI PMIC Arbiter implements HW version 8 and it's an SPMI
+ controller with wrapping arbitration logic to allow for multiple on-chip
+ devices to control up to 4 SPMI separate buses.
+
+ The PMIC Arbiter can also act as an interrupt controller, providing interrupts
+ to slave devices.
+
+allOf:
+ - $ref: /schemas/spmi/qcom,spmi-pmic-arb-common.yaml
+
+properties:
+ compatible:
+ oneOf:
+ - items:
+ - enum:
+ - qcom,kaanapali-spmi-pmic-arb
+ - const: qcom,glymur-spmi-pmic-arb
+ - enum:
+ - qcom,glymur-spmi-pmic-arb
+
+ reg:
+ items:
+ - description: core registers
+ - description: tx-channel per virtual slave registers
+ - description: rx-channel (called observer) per virtual slave registers
+ - description: channel to PMIC peripheral mapping registers
+
+ reg-names:
+ items:
+ - const: core
+ - const: chnls
+ - const: obsrvr
+ - const: chnl_map
+
+ ranges: true
+
+ '#address-cells':
+ const: 2
+
+ '#size-cells':
+ const: 2
+
+patternProperties:
+ "^spmi@[a-f0-9]+$":
+ type: object
+ $ref: /schemas/spmi/spmi.yaml
+ unevaluatedProperties: false
+
+ properties:
+ reg:
+ items:
+ - description: configuration registers
+ - description: interrupt controller registers
+ - description: channel owner EE mapping registers
+
+ reg-names:
+ items:
+ - const: cnfg
+ - const: intr
+ - const: chnl_owner
+
+ interrupts:
+ maxItems: 1
+
+ interrupt-names:
+ const: periph_irq
+
+ interrupt-controller: true
+
+ '#interrupt-cells':
+ const: 4
+ description: |
+ cell 1: slave ID for the requested interrupt (0-15)
+ cell 2: peripheral ID for requested interrupt (0-255)
+ cell 3: the requested peripheral interrupt (0-7)
+ cell 4: interrupt flags indicating level-sense information,
+ as defined in dt-bindings/interrupt-controller/irq.h
+
+required:
+ - compatible
+ - reg-names
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ arbiter@c400000 {
+ compatible = "qcom,glymur-spmi-pmic-arb";
+ reg = <0x0 0xc400000 0x0 0x3000>,
+ <0x0 0xc900000 0x0 0x400000>,
+ <0x0 0xc4c0000 0x0 0x400000>,
+ <0x0 0xc403000 0x0 0x8000>;
+ reg-names = "core", "chnls", "obsrvr", "chnl_map";
+
+ qcom,ee = <0>;
+ qcom,channel = <0>;
+
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ spmi@c426000 {
+ reg = <0x0 0xc426000 0x0 0x4000>,
+ <0x0 0xc8c0000 0x0 0x10000>,
+ <0x0 0xc42a000 0x0 0x8000>;
+ reg-names = "cnfg", "intr", "chnl_owner";
+
+ interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "periph_irq";
+ interrupt-controller;
+ #interrupt-cells = <4>;
+
+ #address-cells = <2>;
+ #size-cells = <0>;
+ };
+
+ spmi@c437000 {
+ reg = <0x0 0xc437000 0x0 0x4000>,
+ <0x0 0xc8d0000 0x0 0x10000>,
+ <0x0 0xc43b000 0x0 0x8000>;
+ reg-names = "cnfg", "intr", "chnl_owner";
+
+ interrupts-extended = <&pdc 3 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "periph_irq";
+ interrupt-controller;
+ #interrupt-cells = <4>;
+
+ #address-cells = <2>;
+ #size-cells = <0>;
+ };
+ };
+ };
--
https://git.kernel.org/pub/scm/linux/kernel/git/clk/linux.git
https://git.kernel.org/pub/scm/linux/kernel/git/sboyd/spmi.git
^ permalink raw reply related [flat|nested] 11+ messages in thread* [PATCH 09/10] spmi: spmi-pmic-arb: add support for PMIC arbiter v8
2026-01-23 18:20 [PATCH 00/10] spmi: Patches for the merge window Stephen Boyd
` (7 preceding siblings ...)
2026-01-23 18:20 ` [PATCH 08/10] dt-bindings: spmi: add support for glymur-spmi-pmic-arb (arbiter v8) Stephen Boyd
@ 2026-01-23 18:20 ` Stephen Boyd
2026-01-23 18:20 ` [PATCH 10/10] dt-bindings: spmi: spmi-mtk-pmif: Add compatible for MT8189 SoC Stephen Boyd
9 siblings, 0 replies; 11+ messages in thread
From: Stephen Boyd @ 2026-01-23 18:20 UTC (permalink / raw)
To: Greg Kroah-Hartman
Cc: David Collins, linux-kernel, patches, Kamal Wadhwa,
Jishnu Prakash, Konrad Dybcio
From: David Collins <david.collins@oss.qualcomm.com>
PMIC arbiter v8 supports up to 4 SPMI buses and up to 8192 PMIC
peripherals. Its register map differs from v7 as several fields
increased in size. Add support for PMIC arbiter version 8.
Signed-off-by: David Collins <david.collins@oss.qualcomm.com>
Signed-off-by: Kamal Wadhwa <kamal.wadhwa@oss.qualcomm.com>
Signed-off-by: Jishnu Prakash <jishnu.prakash@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
---
drivers/spmi/spmi-pmic-arb.c | 304 +++++++++++++++++++++++++++++------
1 file changed, 255 insertions(+), 49 deletions(-)
diff --git a/drivers/spmi/spmi-pmic-arb.c b/drivers/spmi/spmi-pmic-arb.c
index 91581974ef84..69f8d456324a 100644
--- a/drivers/spmi/spmi-pmic-arb.c
+++ b/drivers/spmi/spmi-pmic-arb.c
@@ -2,6 +2,8 @@
/*
* Copyright (c) 2012-2015, 2017, 2021, The Linux Foundation. All rights reserved.
*/
+
+#include <linux/bitfield.h>
#include <linux/bitmap.h>
#include <linux/delay.h>
#include <linux/err.h>
@@ -25,12 +27,12 @@
#define PMIC_ARB_VERSION_V3_MIN 0x30000000
#define PMIC_ARB_VERSION_V5_MIN 0x50000000
#define PMIC_ARB_VERSION_V7_MIN 0x70000000
+#define PMIC_ARB_VERSION_V8_MIN 0x80000000
#define PMIC_ARB_INT_EN 0x0004
#define PMIC_ARB_FEATURES 0x0004
#define PMIC_ARB_FEATURES_PERIPH_MASK GENMASK(10, 0)
-
-#define PMIC_ARB_FEATURES1 0x0008
+#define PMIC_ARB_FEATURES_V8_PERIPH_MASK GENMASK(12, 0)
/* PMIC Arbiter channel registers offsets */
#define PMIC_ARB_CMD 0x00
@@ -50,9 +52,11 @@
#define SPMI_MAPPING_BIT_IS_1_RESULT(X) (((X) >> 0) & 0xFF)
#define SPMI_MAPPING_TABLE_TREE_DEPTH 16 /* Maximum of 16-bits */
-#define PMIC_ARB_MAX_PPID BIT(12) /* PPID is 12bit */
+#define PMIC_ARB_MAX_PPID BIT(13)
#define PMIC_ARB_APID_VALID BIT(15)
-#define PMIC_ARB_CHAN_IS_IRQ_OWNER(reg) ((reg) & BIT(24))
+#define PMIC_ARB_CHAN_IS_IRQ_OWNER_MASK BIT(24)
+#define PMIC_ARB_V8_CHAN_IS_IRQ_OWNER_MASK BIT(31)
+
#define INVALID_EE 0xFF
/* Ownership Table */
@@ -96,30 +100,37 @@ enum pmic_arb_channel {
PMIC_ARB_CHANNEL_OBS,
};
-#define PMIC_ARB_MAX_BUSES 2
+#define PMIC_ARB_MAX_BUSES 4
/* Maximum number of support PMIC peripherals */
#define PMIC_ARB_MAX_PERIPHS 512
#define PMIC_ARB_MAX_PERIPHS_V7 1024
+#define PMIC_ARB_MAX_PERIPHS_V8 8192
#define PMIC_ARB_TIMEOUT_US 1000
#define PMIC_ARB_MAX_TRANS_BYTES (8)
#define PMIC_ARB_APID_MASK 0xFF
-#define PMIC_ARB_PPID_MASK 0xFFF
+#define PMIC_ARB_PPID_MASK GENMASK(11, 0)
+#define PMIC_ARB_V8_PPID_MASK GENMASK(12, 0)
/* interrupt enable bit */
#define SPMI_PIC_ACC_ENABLE_BIT BIT(0)
+#define HWIRQ_SID_MASK GENMASK(28, 24)
+#define HWIRQ_PID_MASK GENMASK(23, 16)
+#define HWIRQ_IRQID_MASK GENMASK(15, 13)
+#define HWIRQ_APID_MASK GENMASK(12, 0)
+
#define spec_to_hwirq(slave_id, periph_id, irq_id, apid) \
- ((((slave_id) & 0xF) << 28) | \
- (((periph_id) & 0xFF) << 20) | \
- (((irq_id) & 0x7) << 16) | \
- (((apid) & 0x3FF) << 0))
+ (FIELD_PREP(HWIRQ_SID_MASK, (slave_id)) | \
+ FIELD_PREP(HWIRQ_PID_MASK, (periph_id)) | \
+ FIELD_PREP(HWIRQ_IRQID_MASK, (irq_id)) | \
+ FIELD_PREP(HWIRQ_APID_MASK, (apid)))
-#define hwirq_to_sid(hwirq) (((hwirq) >> 28) & 0xF)
-#define hwirq_to_per(hwirq) (((hwirq) >> 20) & 0xFF)
-#define hwirq_to_irq(hwirq) (((hwirq) >> 16) & 0x7)
-#define hwirq_to_apid(hwirq) (((hwirq) >> 0) & 0x3FF)
+#define hwirq_to_sid(hwirq) FIELD_GET(HWIRQ_SID_MASK, (hwirq))
+#define hwirq_to_per(hwirq) FIELD_GET(HWIRQ_PID_MASK, (hwirq))
+#define hwirq_to_irq(hwirq) FIELD_GET(HWIRQ_IRQID_MASK, (hwirq))
+#define hwirq_to_apid(hwirq) FIELD_GET(HWIRQ_APID_MASK, (hwirq))
struct pmic_arb_ver_ops;
@@ -138,11 +149,12 @@ struct spmi_pmic_arb;
* @domain: irq domain object for PMIC IRQ domain
* @intr: address of the SPMI interrupt control registers.
* @cnfg: address of the PMIC Arbiter configuration registers.
+ * @apid_owner: on v8: address of APID owner mapping table registers
* @spmic: spmi controller registered for this bus
* @lock: lock to synchronize accesses.
- * @base_apid: on v7: minimum APID associated with the particular SPMI
- * bus instance
- * @apid_count: on v5 and v7: number of APIDs associated with the
+ * @base_apid: on v7 and v8: minimum APID associated with the
+ * particular SPMI bus instance
+ * @apid_count: on v5, v7 and v8: number of APIDs associated with the
* particular SPMI bus instance
* @mapping_table: in-memory copy of PPID -> APID mapping table.
* @mapping_table_valid:bitmap containing valid-only periphs
@@ -159,6 +171,7 @@ struct spmi_pmic_arb_bus {
struct irq_domain *domain;
void __iomem *intr;
void __iomem *cnfg;
+ void __iomem *apid_owner;
struct spmi_controller *spmic;
raw_spinlock_t lock;
u16 base_apid;
@@ -181,6 +194,7 @@ struct spmi_pmic_arb_bus {
* @wr_base: on v1 "core", on v2 "chnls" register base off DT.
* @core: core register base for v2 and above only (see above)
* @core_size: core register base size
+ * @apid_map: on v8, APID mapping table register base
* @channel: execution environment channel to use for accesses.
* @ee: the current Execution Environment
* @ver_ops: version dependent operations.
@@ -193,6 +207,7 @@ struct spmi_pmic_arb {
void __iomem *wr_base;
void __iomem *core;
resource_size_t core_size;
+ void __iomem *apid_map;
u8 channel;
u8 ee;
const struct pmic_arb_ver_ops *ver_ops;
@@ -206,6 +221,7 @@ struct spmi_pmic_arb {
*
* @ver_str: version string.
* @get_core_resources: initializes the core, observer and channels
+ * @get_bus_resources: requests per-SPMI bus register resources
* @init_apid: finds the apid base and count
* @ppid_to_apid: finds the apid for a given ppid.
* @non_data_cmd: on v1 issues an spmi non-data command.
@@ -227,6 +243,9 @@ struct spmi_pmic_arb {
struct pmic_arb_ver_ops {
const char *ver_str;
int (*get_core_resources)(struct platform_device *pdev, void __iomem *core);
+ int (*get_bus_resources)(struct platform_device *pdev,
+ struct device_node *node,
+ struct spmi_pmic_arb_bus *bus);
int (*init_apid)(struct spmi_pmic_arb_bus *bus, int index);
int (*ppid_to_apid)(struct spmi_pmic_arb_bus *bus, u16 ppid);
/* spmi commands (read_cmd, write_cmd, cmd) functionality */
@@ -656,7 +675,7 @@ static int periph_interrupt(struct spmi_pmic_arb_bus *bus, u16 apid)
unsigned int irq;
u32 status, id;
int handled = 0;
- u8 sid = (bus->apid_data[apid].ppid >> 8) & 0xF;
+ u8 sid = (bus->apid_data[apid].ppid >> 8) & 0x1F;
u8 per = bus->apid_data[apid].ppid & 0xFF;
status = readl_relaxed(pmic_arb->ver_ops->irq_status(bus, apid));
@@ -686,7 +705,7 @@ static void pmic_arb_chained_irq(struct irq_desc *desc)
int last = bus->max_apid;
/*
* acc_offset will be non-zero for the secondary SPMI bus instance on
- * v7 controllers.
+ * v7 and v8 controllers.
*/
int acc_offset = bus->base_apid >> 5;
u8 ee = pmic_arb->ee;
@@ -913,7 +932,8 @@ static int qpnpint_irq_domain_translate(struct irq_domain *d,
return -EINVAL;
if (fwspec->param_count != 4)
return -EINVAL;
- if (intspec[0] > 0xF || intspec[1] > 0xFF || intspec[2] > 0x7)
+ if (intspec[0] > FIELD_MAX(HWIRQ_SID_MASK) || intspec[1] > FIELD_MAX(HWIRQ_PID_MASK) ||
+ intspec[2] > FIELD_MAX(HWIRQ_IRQID_MASK))
return -EINVAL;
ppid = intspec[0] << 8 | intspec[1];
@@ -1160,7 +1180,9 @@ static int pmic_arb_ppid_to_apid_v2(struct spmi_pmic_arb_bus *bus, u16 ppid)
return apid_valid & ~PMIC_ARB_APID_VALID;
}
-static int pmic_arb_read_apid_map_v5(struct spmi_pmic_arb_bus *bus)
+static int _pmic_arb_read_apid_map(struct spmi_pmic_arb_bus *bus,
+ void __iomem *ppid_base, unsigned long ppid_mask,
+ u8 ppid_shift, unsigned long irq_owner_mask)
{
struct spmi_pmic_arb *pmic_arb = bus->pmic_arb;
struct apid_data *apidd;
@@ -1171,7 +1193,7 @@ static int pmic_arb_read_apid_map_v5(struct spmi_pmic_arb_bus *bus)
/*
* In order to allow multiple EEs to write to a single PPID in arbiter
- * version 5 and 7, there is more than one APID mapped to each PPID.
+ * version 5,7 and 8, there can be more than one APID mapped to each PPID.
* The owner field for each of these mappings specifies the EE which is
* allowed to write to the APID. The owner of the last (highest) APID
* which has the IRQ owner bit set for a given PPID will receive
@@ -1183,19 +1205,30 @@ static int pmic_arb_read_apid_map_v5(struct spmi_pmic_arb_bus *bus)
* APID = N to N+M-1 are assigned to the secondary bus
* where N = number of APIDs supported by the primary bus and
* M = number of APIDs supported by the secondary bus
+ *
+ * In arbiter version 8, the APID numbering space is divided between
+ * the SPMI buses according to this mapping:
+ * APID = 0 to N-1 --> bus 0
+ * APID = N to N+M-1 --> bus 1
+ * APID = N+M to N+M+P-1 --> bus 2
+ * APID = N+M+P to N+M+P+Q-1 --> bus 3
+ * where N = number of APIDs supported by bus 0
+ * M = number of APIDs supported by bus 1
+ * P = number of APIDs supported by bus 2
+ * Q = number of APIDs supported by bus 3
*/
+
apidd = &bus->apid_data[bus->base_apid];
apid_max = bus->base_apid + bus->apid_count;
for (i = bus->base_apid; i < apid_max; i++, apidd++) {
offset = pmic_arb->ver_ops->apid_map_offset(i);
if (offset >= pmic_arb->core_size)
break;
-
- regval = readl_relaxed(pmic_arb->core + offset);
+ regval = readl_relaxed(ppid_base + offset);
if (!regval)
continue;
- ppid = (regval >> 8) & PMIC_ARB_PPID_MASK;
- is_irq_ee = PMIC_ARB_CHAN_IS_IRQ_OWNER(regval);
+ ppid = (regval >> ppid_shift) & ppid_mask;
+ is_irq_ee = regval & irq_owner_mask;
regval = readl_relaxed(pmic_arb->ver_ops->apid_owner(bus, i));
apidd->write_ee = SPMI_OWNERSHIP_PERIPH2OWNER(regval);
@@ -1237,6 +1270,12 @@ static int pmic_arb_read_apid_map_v5(struct spmi_pmic_arb_bus *bus)
return 0;
}
+static int pmic_arb_read_apid_map_v5(struct spmi_pmic_arb_bus *bus)
+{
+ return _pmic_arb_read_apid_map(bus, bus->pmic_arb->core, PMIC_ARB_PPID_MASK,
+ 8, PMIC_ARB_CHAN_IS_IRQ_OWNER_MASK);
+}
+
static int pmic_arb_ppid_to_apid_v5(struct spmi_pmic_arb_bus *bus, u16 ppid)
{
if (!(bus->ppid_to_apid[ppid] & PMIC_ARB_APID_VALID))
@@ -1345,37 +1384,46 @@ static int pmic_arb_get_core_resources_v7(struct platform_device *pdev,
return pmic_arb_get_obsrvr_chnls_v2(pdev);
}
-/*
- * Only v7 supports 2 buses. Each bus will get a different apid count, read
- * from different registers.
- */
-static int pmic_arb_init_apid_v7(struct spmi_pmic_arb_bus *bus, int index)
+static int _pmic_arb_init_apid_v7(struct spmi_pmic_arb_bus *bus, int index,
+ int max_buses, unsigned long periph_mask)
{
struct spmi_pmic_arb *pmic_arb = bus->pmic_arb;
- int ret;
+ int i;
- if (index == 0) {
- bus->base_apid = 0;
- bus->apid_count = readl_relaxed(pmic_arb->core + PMIC_ARB_FEATURES) &
- PMIC_ARB_FEATURES_PERIPH_MASK;
- } else if (index == 1) {
- bus->base_apid = readl_relaxed(pmic_arb->core + PMIC_ARB_FEATURES) &
- PMIC_ARB_FEATURES_PERIPH_MASK;
- bus->apid_count = readl_relaxed(pmic_arb->core + PMIC_ARB_FEATURES1) &
- PMIC_ARB_FEATURES_PERIPH_MASK;
- } else {
- dev_err(&bus->spmic->dev, "Unsupported buses count %d detected\n",
- bus->id);
+ if (index < 0 || index >= max_buses) {
+ dev_err(&bus->spmic->dev, "Unsupported bus index %d detected\n",
+ index);
return -EINVAL;
}
- if (bus->base_apid + bus->apid_count > pmic_arb->max_periphs) {
- dev_err(&bus->spmic->dev, "Unsupported APID count %d detected\n",
+ bus->base_apid = 0;
+ bus->apid_count = 0;
+ for (i = 0; i <= index; i++) {
+ bus->base_apid += bus->apid_count;
+ bus->apid_count = readl_relaxed(pmic_arb->core +
+ PMIC_ARB_FEATURES + i * 4) &
+ periph_mask;
+ }
+
+ if (bus->apid_count == 0) {
+ dev_err(&bus->spmic->dev, "Bus %d not implemented\n", index);
+ return -EINVAL;
+ } else if (bus->base_apid + bus->apid_count > pmic_arb->max_periphs) {
+ dev_err(&bus->spmic->dev, "Unsupported max APID %d detected\n",
bus->base_apid + bus->apid_count);
return -EINVAL;
}
- ret = pmic_arb_init_apid_min_max(bus);
+ return pmic_arb_init_apid_min_max(bus);
+}
+
+/*
+ * Arbiter v7 supports 2 buses. Each bus will get a different apid count, read
+ * from different registers.
+ */
+static int pmic_arb_init_apid_v7(struct spmi_pmic_arb_bus *bus, int index)
+{
+ int ret = _pmic_arb_init_apid_v7(bus, index, 2, PMIC_ARB_FEATURES_PERIPH_MASK);
if (ret)
return ret;
@@ -1424,6 +1472,102 @@ static int pmic_arb_offset_v7(struct spmi_pmic_arb_bus *bus, u8 sid, u16 addr,
return offset;
}
+static int pmic_arb_get_core_resources_v8(struct platform_device *pdev,
+ void __iomem *core)
+{
+ struct spmi_pmic_arb *pmic_arb = platform_get_drvdata(pdev);
+
+ pmic_arb->apid_map = devm_platform_ioremap_resource_byname(pdev, "chnl_map");
+ if (IS_ERR(pmic_arb->apid_map))
+ return PTR_ERR(pmic_arb->apid_map);
+
+ pmic_arb->core = core;
+
+ pmic_arb->max_periphs = PMIC_ARB_MAX_PERIPHS_V8;
+
+ return pmic_arb_get_obsrvr_chnls_v2(pdev);
+}
+
+static int pmic_arb_get_bus_resources_v8(struct platform_device *pdev,
+ struct device_node *node,
+ struct spmi_pmic_arb_bus *bus)
+{
+ int index;
+
+ index = of_property_match_string(node, "reg-names", "chnl_owner");
+ if (index < 0) {
+ dev_err(&pdev->dev, "chnl_owner reg region missing\n");
+ return -EINVAL;
+ }
+
+ bus->apid_owner = devm_of_iomap(&pdev->dev, node, index, NULL);
+
+ return PTR_ERR_OR_ZERO(bus->apid_owner);
+}
+
+static int pmic_arb_read_apid_map_v8(struct spmi_pmic_arb_bus *bus)
+{
+ return _pmic_arb_read_apid_map(bus, bus->pmic_arb->apid_map,
+ PMIC_ARB_V8_PPID_MASK, 0,
+ PMIC_ARB_V8_CHAN_IS_IRQ_OWNER_MASK);
+}
+
+/*
+ * Arbiter v8 supports up to 4 buses. Each bus will get a different apid count, read
+ * from different registers.
+ */
+static int pmic_arb_init_apid_v8(struct spmi_pmic_arb_bus *bus, int index)
+{
+ int ret = _pmic_arb_init_apid_v7(bus, index, 4,
+ PMIC_ARB_FEATURES_V8_PERIPH_MASK);
+ if (ret)
+ return ret;
+
+ ret = pmic_arb_read_apid_map_v8(bus);
+ if (ret) {
+ dev_err(&bus->spmic->dev, "could not read APID->PPID mapping table, rc= %d\n",
+ ret);
+ return ret;
+ }
+
+ return 0;
+}
+
+/*
+ * v8 offset per ee and per apid for observer channels and per apid for
+ * read/write channels.
+ */
+static int pmic_arb_offset_v8(struct spmi_pmic_arb_bus *bus, u8 sid, u16 addr,
+ enum pmic_arb_channel ch_type)
+{
+ struct spmi_pmic_arb *pmic_arb = bus->pmic_arb;
+ u16 apid;
+ int rc;
+ u32 offset = 0;
+ u16 ppid = (sid << 8) | (addr >> 8);
+
+ rc = pmic_arb->ver_ops->ppid_to_apid(bus, ppid);
+ if (rc < 0)
+ return rc;
+
+ apid = rc;
+ switch (ch_type) {
+ case PMIC_ARB_CHANNEL_OBS:
+ offset = 0x40000 * pmic_arb->ee + 0x20 * apid;
+ break;
+ case PMIC_ARB_CHANNEL_RW:
+ if (bus->apid_data[apid].write_ee != pmic_arb->ee) {
+ dev_err(&bus->spmic->dev, "disallowed SPMI write to sid=%u, addr=0x%04X\n",
+ sid, addr);
+ return -EPERM;
+ }
+ offset = 0x200 * apid;
+ break;
+ }
+
+ return offset;
+}
+
static u32 pmic_arb_fmt_cmd_v1(u8 opc, u8 sid, u16 addr, u8 bc)
{
return (opc << 27) | ((sid & 0xf) << 20) | (addr << 4) | (bc & 0x7);
@@ -1490,6 +1634,14 @@ pmic_arb_acc_enable_v7(struct spmi_pmic_arb_bus *bus, u16 n)
return pmic_arb->wr_base + 0x100 + 0x1000 * n;
}
+static void __iomem *
+pmic_arb_acc_enable_v8(struct spmi_pmic_arb_bus *bus, u16 n)
+{
+ struct spmi_pmic_arb *pmic_arb = bus->pmic_arb;
+
+ return pmic_arb->wr_base + 0x100 + 0x200 * n;
+}
+
static void __iomem *
pmic_arb_irq_status_v1(struct spmi_pmic_arb_bus *bus, u16 n)
{
@@ -1516,6 +1668,14 @@ pmic_arb_irq_status_v7(struct spmi_pmic_arb_bus *bus, u16 n)
return pmic_arb->wr_base + 0x104 + 0x1000 * n;
}
+static void __iomem *
+pmic_arb_irq_status_v8(struct spmi_pmic_arb_bus *bus, u16 n)
+{
+ struct spmi_pmic_arb *pmic_arb = bus->pmic_arb;
+
+ return pmic_arb->wr_base + 0x104 + 0x200 * n;
+}
+
static void __iomem *
pmic_arb_irq_clear_v1(struct spmi_pmic_arb_bus *bus, u16 n)
{
@@ -1542,6 +1702,14 @@ pmic_arb_irq_clear_v7(struct spmi_pmic_arb_bus *bus, u16 n)
return pmic_arb->wr_base + 0x108 + 0x1000 * n;
}
+static void __iomem *
+pmic_arb_irq_clear_v8(struct spmi_pmic_arb_bus *bus, u16 n)
+{
+ struct spmi_pmic_arb *pmic_arb = bus->pmic_arb;
+
+ return pmic_arb->wr_base + 0x108 + 0x200 * n;
+}
+
static u32 pmic_arb_apid_map_offset_v2(u16 n)
{
return 0x800 + 0x4 * n;
@@ -1557,6 +1725,12 @@ static u32 pmic_arb_apid_map_offset_v7(u16 n)
return 0x2000 + 0x4 * n;
}
+static u32 pmic_arb_apid_map_offset_v8(u16 n)
+{
+ /* For v8, offset is from "chnl_map" base register, not "core". */
+ return 0x4 * n;
+}
+
static void __iomem *
pmic_arb_apid_owner_v2(struct spmi_pmic_arb_bus *bus, u16 n)
{
@@ -1564,7 +1738,7 @@ pmic_arb_apid_owner_v2(struct spmi_pmic_arb_bus *bus, u16 n)
}
/*
- * For arbiter version 7, APID ownership table registers have independent
+ * For arbiter version 7 and 8, APID ownership table registers have independent
* numbering space for each SPMI bus instance, so each is indexed starting from
* 0.
*/
@@ -1574,6 +1748,12 @@ pmic_arb_apid_owner_v7(struct spmi_pmic_arb_bus *bus, u16 n)
return bus->cnfg + 0x4 * (n - bus->base_apid);
}
+static void __iomem *
+pmic_arb_apid_owner_v8(struct spmi_pmic_arb_bus *bus, u16 n)
+{
+ return bus->apid_owner + 0x4 * (n - bus->base_apid);
+}
+
static const struct pmic_arb_ver_ops pmic_arb_v1 = {
.ver_str = "v1",
.get_core_resources = pmic_arb_get_core_resources_v1,
@@ -1654,6 +1834,23 @@ static const struct pmic_arb_ver_ops pmic_arb_v7 = {
.apid_owner = pmic_arb_apid_owner_v7,
};
+static const struct pmic_arb_ver_ops pmic_arb_v8 = {
+ .ver_str = "v8",
+ .get_core_resources = pmic_arb_get_core_resources_v8,
+ .get_bus_resources = pmic_arb_get_bus_resources_v8,
+ .init_apid = pmic_arb_init_apid_v8,
+ .ppid_to_apid = pmic_arb_ppid_to_apid_v5,
+ .non_data_cmd = pmic_arb_non_data_cmd_v2,
+ .offset = pmic_arb_offset_v8,
+ .fmt_cmd = pmic_arb_fmt_cmd_v2,
+ .owner_acc_status = pmic_arb_owner_acc_status_v7,
+ .acc_enable = pmic_arb_acc_enable_v8,
+ .irq_status = pmic_arb_irq_status_v8,
+ .irq_clear = pmic_arb_irq_clear_v8,
+ .apid_map_offset = pmic_arb_apid_map_offset_v8,
+ .apid_owner = pmic_arb_apid_owner_v8,
+};
+
static const struct irq_domain_ops pmic_arb_irq_domain_ops = {
.activate = qpnpint_irq_domain_activate,
.alloc = qpnpint_irq_domain_alloc,
@@ -1731,6 +1928,12 @@ static int spmi_pmic_arb_bus_init(struct platform_device *pdev,
bus->spmic = ctrl;
bus->id = bus_index;
+ if (pmic_arb->ver_ops->get_bus_resources) {
+ ret = pmic_arb->ver_ops->get_bus_resources(pdev, node, bus);
+ if (ret)
+ return ret;
+ }
+
ret = pmic_arb->ver_ops->init_apid(bus, bus_index);
if (ret)
return ret;
@@ -1825,8 +2028,10 @@ static int spmi_pmic_arb_probe(struct platform_device *pdev)
pmic_arb->ver_ops = &pmic_arb_v3;
else if (hw_ver < PMIC_ARB_VERSION_V7_MIN)
pmic_arb->ver_ops = &pmic_arb_v5;
- else
+ else if (hw_ver < PMIC_ARB_VERSION_V8_MIN)
pmic_arb->ver_ops = &pmic_arb_v7;
+ else
+ pmic_arb->ver_ops = &pmic_arb_v8;
err = pmic_arb->ver_ops->get_core_resources(pdev, core);
if (err)
@@ -1875,6 +2080,7 @@ static void spmi_pmic_arb_remove(struct platform_device *pdev)
static const struct of_device_id spmi_pmic_arb_match_table[] = {
{ .compatible = "qcom,spmi-pmic-arb", },
{ .compatible = "qcom,x1e80100-spmi-pmic-arb", },
+ { .compatible = "qcom,glymur-spmi-pmic-arb", },
{},
};
MODULE_DEVICE_TABLE(of, spmi_pmic_arb_match_table);
--
https://git.kernel.org/pub/scm/linux/kernel/git/clk/linux.git
https://git.kernel.org/pub/scm/linux/kernel/git/sboyd/spmi.git
^ permalink raw reply related [flat|nested] 11+ messages in thread* [PATCH 10/10] dt-bindings: spmi: spmi-mtk-pmif: Add compatible for MT8189 SoC
2026-01-23 18:20 [PATCH 00/10] spmi: Patches for the merge window Stephen Boyd
` (8 preceding siblings ...)
2026-01-23 18:20 ` [PATCH 09/10] spmi: spmi-pmic-arb: add support for PMIC arbiter v8 Stephen Boyd
@ 2026-01-23 18:20 ` Stephen Boyd
9 siblings, 0 replies; 11+ messages in thread
From: Stephen Boyd @ 2026-01-23 18:20 UTC (permalink / raw)
To: Greg Kroah-Hartman
Cc: Louis-Alexis Eyraud, linux-kernel, patches, Conor Dooley,
AngeloGioacchino Del Regno
From: Louis-Alexis Eyraud <louisalexis.eyraud@collabora.com>
Add compatible string for the SPMI block on MT8189 SoC, which is
compatible with the one used on MT8195.
Signed-off-by: Louis-Alexis Eyraud <louisalexis.eyraud@collabora.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
---
Documentation/devicetree/bindings/spmi/mtk,spmi-mtk-pmif.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/spmi/mtk,spmi-mtk-pmif.yaml b/Documentation/devicetree/bindings/spmi/mtk,spmi-mtk-pmif.yaml
index 7f0be0ac644a..dc61d88008a9 100644
--- a/Documentation/devicetree/bindings/spmi/mtk,spmi-mtk-pmif.yaml
+++ b/Documentation/devicetree/bindings/spmi/mtk,spmi-mtk-pmif.yaml
@@ -26,6 +26,7 @@ properties:
- enum:
- mediatek,mt8186-spmi
- mediatek,mt8188-spmi
+ - mediatek,mt8189-spmi
- const: mediatek,mt8195-spmi
reg:
--
https://git.kernel.org/pub/scm/linux/kernel/git/clk/linux.git
https://git.kernel.org/pub/scm/linux/kernel/git/sboyd/spmi.git
^ permalink raw reply related [flat|nested] 11+ messages in thread