[PATCH] iommu/vt-d: Restore WO permissions on second-level paging entries

[PATCH] iommu/vt-d: Restore WO permissions on second-level paging entries

[Jason Gunthorpe]

VT-D HW can do WO permissions on the second-stage but not the first-stage
page table formats. The commit eea53c581688 ("iommu/vt-d: Remove WO
permissions on second-level paging entries") wanted to make this uniform
for VT-D by disabling the support for WO permissions in the second-stage.

This isn't consistent with how other drivers are working. Instead if the
underlying HW can support WO, it should. For instance AMD already supports
WO on its second stage (v1) format and not its first (v2).

If WO support needs to be discoverable it should be done through an
iommu_domain capability flag.

Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
---
 drivers/iommu/intel/iommu.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/drivers/iommu/intel/iommu.c b/drivers/iommu/intel/iommu.c
index 5d5291887516d1..fbe65e97381200 100644
--- a/drivers/iommu/intel/iommu.c
+++ b/drivers/iommu/intel/iommu.c
@@ -1682,9 +1682,8 @@ __domain_mapping(struct dmar_domain *domain, unsigned long iov_pfn,
 	}
 
 	attr = prot & (DMA_PTE_READ | DMA_PTE_WRITE | DMA_PTE_SNP);
-	attr |= DMA_FL_PTE_PRESENT;
 	if (domain->use_first_level) {
-		attr |= DMA_FL_PTE_US | DMA_FL_PTE_ACCESS;
+		attr |= DMA_FL_PTE_PRESENT | DMA_FL_PTE_US | DMA_FL_PTE_ACCESS;
 		if (prot & DMA_PTE_WRITE)
 			attr |= DMA_FL_PTE_DIRTY;
 	}

base-commit: 398ca5040723f1b5bdc35900357f4a889b4b5611
-- 
2.43.0

RE: [PATCH] iommu/vt-d: Restore WO permissions on second-level paging entries

[Tian, Kevin]

> From: Jason Gunthorpe <jgg@nvidia.com>
> Sent: Wednesday, April 30, 2025 12:12 AM
> 
> VT-D HW can do WO permissions on the second-stage but not the first-stage
> page table formats. The commit eea53c581688 ("iommu/vt-d: Remove WO
> permissions on second-level paging entries") wanted to make this uniform
> for VT-D by disabling the support for WO permissions in the second-stage.
> 
> This isn't consistent with how other drivers are working. Instead if the
> underlying HW can support WO, it should. For instance AMD already
> supports
> WO on its second stage (v1) format and not its first (v2).
> 
> If WO support needs to be discoverable it should be done through an
> iommu_domain capability flag.

DMA_FROM_DEVICE ideally implies a WO mapping but it is more
a hint instead of an enforcement. so yes a new flag might be
required when a strict WO support is required.

> 
> Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>

Reviewed-by: Kevin Tian <kevin.tian@intel.com>

Re: [PATCH] iommu/vt-d: Restore WO permissions on second-level paging entries

[Baolu Lu]

On 4/30/25 00:12, Jason Gunthorpe wrote:
> VT-D HW can do WO permissions on the second-stage but not the first-stage
> page table formats. The commit eea53c581688 ("iommu/vt-d: Remove WO
> permissions on second-level paging entries") wanted to make this uniform
> for VT-D by disabling the support for WO permissions in the second-stage.
> 
> This isn't consistent with how other drivers are working. Instead if the
> underlying HW can support WO, it should. For instance AMD already supports
> WO on its second stage (v1) format and not its first (v2).
> 
> If WO support needs to be discoverable it should be done through an
> iommu_domain capability flag.
> 
> Signed-off-by: Jason Gunthorpe<jgg@nvidia.com>
> ---
>   drivers/iommu/intel/iommu.c | 3 +--
>   1 file changed, 1 insertion(+), 2 deletions(-)

Queued for v6.16-rc1. Thank you!