* RE: [PATCH 3/3] PCI: mvebu: add wrapped I/O access functions
2013-08-28 12:14 ` Thomas Petazzoni
@ 2013-08-29 9:35 ` Seungwon Jeon
2013-08-29 12:36 ` [PATCH v2 " Seungwon Jeon
2013-10-04 9:58 ` [PATCH v3] PCI: mvebu: add I/O access wrappers Seungwon Jeon
2 siblings, 0 replies; 7+ messages in thread
From: Seungwon Jeon @ 2013-08-29 9:35 UTC (permalink / raw)
To: 'Thomas Petazzoni'
Cc: linux-pci, 'Jason Cooper', 'Bjorn Helgaas'
On Wednesday, August 28, 2013, Thomas Petazzoni wrote
> Dear Seungwon Jeon,
>
> On Wed, 28 Aug 2013 20:53:47 +0900, Seungwon Jeon wrote:
> > read/write operation for I/O mem is wrapped with hiding
> > base address inside in order to simplify the usage.
> >
> > Signed-off-by: Seungwon Jeon <tgih.jun@samsung.com>
>
> I'm fine with the principle, but I have a few comments below.
>
> > ---
> > drivers/pci/host/pci-mvebu.c | 105 +++++++++++++++++++++++++++---------------
> > 1 files changed, 68 insertions(+), 37 deletions(-)
> >
> > diff --git a/drivers/pci/host/pci-mvebu.c b/drivers/pci/host/pci-mvebu.c
> > index d66530e..db8b00b 100644
> > --- a/drivers/pci/host/pci-mvebu.c
> > +++ b/drivers/pci/host/pci-mvebu.c
> > @@ -141,29 +141,59 @@ struct mvebu_pcie_port {
> > size_t iowin_size;
> > };
> >
> > +static inline void mvebu_writeb(struct mvebu_pcie_port *port, u8 val, u32 reg)
> > +{
> > + writeb(val, port->base + reg);
> > +}
> > +
> > +static inline u8 mvebu_readb(struct mvebu_pcie_port *port, u32 reg)
> > +{
> > + return readb(port->base + reg);
> > +}
>
> Those ones are not needed, all registers of this IP block are 32 bits
> registers.
Dear Thomas Petazzoni,
This is because I saw mvebu_pcie_hw_wr_conf(), which has various bit access.
But it could be modified with both writel and readl, right?
>
> > +
> > +static inline void mvebu_writew(struct mvebu_pcie_port *port, u16 val, u32 reg)
> > +{
> > + writew(val, port->base + reg);
> > +}
> > +
> > +static inline u16 mvebu_readw(struct mvebu_pcie_port *port, u32 reg)
> > +{
> > + return readw(port->base + reg);
> > +}
>
> Provided a small change is done below, those will also not be needed.
>
> > +static inline void mvebu_writel(struct mvebu_pcie_port *port, u32 val, u32 reg)
> > +{
> > + writel(val, port->base + reg);
> > +}
> > +
> > +static inline u32 mvebu_readl(struct mvebu_pcie_port *port, u32 reg)
> > +{
> > + return readl(port->base + reg);
> > +}
>
> Ok, but they should be called mvebu_pcie_readl() and
> mvebu_pcie_writel(), because they are specific to the PCIe IP block.
> Once you've done that, you'll realize that it's in fact longer to write:
>
> mvebu_pcie_readl(port, PCIE_FOO);
>
> than
>
> readl(port->base + PCIE_FOO);
>
> but ok, I do not oppose to the change.
>
> > /* Master + slave enable. */
> > - cmd = readw(port->base + PCIE_CMD_OFF);
> > + cmd = mvebu_readw(port, PCIE_CMD_OFF);
> > cmd |= PCI_COMMAND_IO;
> > cmd |= PCI_COMMAND_MEMORY;
> > cmd |= PCI_COMMAND_MASTER;
> > - writew(cmd, port->base + PCIE_CMD_OFF);
> > + mvebu_writew(port, cmd, PCIE_CMD_OFF);
>
> I believe this can be turned into a 32 bits read/modify/write, because
> the register is really a 32 bits registers, on both Armada 370/XP and
> Kirkwood (I guess Dove is the same).
You mean that here, readw and writew can be replaced by 32 bits access?
Then, I could take only 32-bit access functions.
Thanks,
Seungwon Jeon
>
> With this change, you can keep only the 32 bits variants of the
> accessors functions at the top of the file.
>
> Thanks,
>
> Thomas
> --
> Thomas Petazzoni, Free Electrons
> Kernel, drivers, real-time and embedded Linux
> development, consulting, training and support.
> http://free-electrons.com
^ permalink raw reply [flat|nested] 7+ messages in thread* [PATCH v2 3/3] PCI: mvebu: add wrapped I/O access functions
2013-08-28 12:14 ` Thomas Petazzoni
2013-08-29 9:35 ` Seungwon Jeon
@ 2013-08-29 12:36 ` Seungwon Jeon
2013-08-29 20:11 ` Bjorn Helgaas
2013-10-04 9:58 ` [PATCH v3] PCI: mvebu: add I/O access wrappers Seungwon Jeon
2 siblings, 1 reply; 7+ messages in thread
From: Seungwon Jeon @ 2013-08-29 12:36 UTC (permalink / raw)
To: linux-pci
Cc: 'Thomas Petazzoni', linux-pci, 'Jason Cooper',
'Bjorn Helgaas'
read/write operation for I/O mem is wrapped with hiding
base address inside in order to simplify the usage.
Signed-off-by: Seungwon Jeon <tgih.jun@samsung.com>
---
Changes in v2:
- Only 32-bit accessors are kept.
drivers/pci/host/pci-mvebu.c | 97 ++++++++++++++++++++++++------------------
1 files changed, 55 insertions(+), 42 deletions(-)
diff --git a/drivers/pci/host/pci-mvebu.c b/drivers/pci/host/pci-mvebu.c
index d66530e..8dcd7e6 100644
--- a/drivers/pci/host/pci-mvebu.c
+++ b/drivers/pci/host/pci-mvebu.c
@@ -141,29 +141,39 @@ struct mvebu_pcie_port {
size_t iowin_size;
};
+static inline void mvebu_writel(struct mvebu_pcie_port *port, u32 val, u32 reg)
+{
+ writel(val, port->base + reg);
+}
+
+static inline u32 mvebu_readl(struct mvebu_pcie_port *port, u32 reg)
+{
+ return readl(port->base + reg);
+}
+
static bool mvebu_pcie_link_up(struct mvebu_pcie_port *port)
{
- return !(readl(port->base + PCIE_STAT_OFF) & PCIE_STAT_LINK_DOWN);
+ return !(mvebu_readl(port, PCIE_STAT_OFF) & PCIE_STAT_LINK_DOWN);
}
static void mvebu_pcie_set_local_bus_nr(struct mvebu_pcie_port *port, int nr)
{
u32 stat;
- stat = readl(port->base + PCIE_STAT_OFF);
+ stat = mvebu_readl(port, PCIE_STAT_OFF);
stat &= ~PCIE_STAT_BUS;
stat |= nr << 8;
- writel(stat, port->base + PCIE_STAT_OFF);
+ mvebu_writel(port, stat, PCIE_STAT_OFF);
}
static void mvebu_pcie_set_local_dev_nr(struct mvebu_pcie_port *port, int nr)
{
u32 stat;
- stat = readl(port->base + PCIE_STAT_OFF);
+ stat = mvebu_readl(port, PCIE_STAT_OFF);
stat &= ~PCIE_STAT_DEV;
stat |= nr << 16;
- writel(stat, port->base + PCIE_STAT_OFF);
+ mvebu_writel(port, stat, PCIE_STAT_OFF);
}
/*
@@ -181,33 +191,34 @@ static void mvebu_pcie_setup_wins(struct mvebu_pcie_port *port)
/* First, disable and clear BARs and windows. */
for (i = 1; i < 3; i++) {
- writel(0, port->base + PCIE_BAR_CTRL_OFF(i));
- writel(0, port->base + PCIE_BAR_LO_OFF(i));
- writel(0, port->base + PCIE_BAR_HI_OFF(i));
+ mvebu_writel(port, 0, PCIE_BAR_CTRL_OFF(i));
+ mvebu_writel(port, 0, PCIE_BAR_LO_OFF(i));
+ mvebu_writel(port, 0, PCIE_BAR_HI_OFF(i));
}
for (i = 0; i < 5; i++) {
- writel(0, port->base + PCIE_WIN04_CTRL_OFF(i));
- writel(0, port->base + PCIE_WIN04_BASE_OFF(i));
- writel(0, port->base + PCIE_WIN04_REMAP_OFF(i));
+ mvebu_writel(port, 0, PCIE_WIN04_CTRL_OFF(i));
+ mvebu_writel(port, 0, PCIE_WIN04_BASE_OFF(i));
+ mvebu_writel(port, 0, PCIE_WIN04_REMAP_OFF(i));
}
- writel(0, port->base + PCIE_WIN5_CTRL_OFF);
- writel(0, port->base + PCIE_WIN5_BASE_OFF);
- writel(0, port->base + PCIE_WIN5_REMAP_OFF);
+ mvebu_writel(port, 0, PCIE_WIN5_CTRL_OFF);
+ mvebu_writel(port, 0, PCIE_WIN5_BASE_OFF);
+ mvebu_writel(port, 0, PCIE_WIN5_REMAP_OFF);
/* Setup windows for DDR banks. Count total DDR size on the fly. */
size = 0;
for (i = 0; i < dram->num_cs; i++) {
const struct mbus_dram_window *cs = dram->cs + i;
- writel(cs->base & 0xffff0000,
- port->base + PCIE_WIN04_BASE_OFF(i));
- writel(0, port->base + PCIE_WIN04_REMAP_OFF(i));
- writel(((cs->size - 1) & 0xffff0000) |
- (cs->mbus_attr << 8) |
- (dram->mbus_dram_target_id << 4) | 1,
- port->base + PCIE_WIN04_CTRL_OFF(i));
+ mvebu_writel(port, cs->base & 0xffff0000,
+ PCIE_WIN04_BASE_OFF(i));
+ mvebu_writel(port, 0, PCIE_WIN04_REMAP_OFF(i));
+ mvebu_writel(port,
+ ((cs->size - 1) & 0xffff0000) |
+ (cs->mbus_attr << 8) |
+ (dram->mbus_dram_target_id << 4) | 1,
+ PCIE_WIN04_CTRL_OFF(i));
size += cs->size;
}
@@ -217,41 +228,40 @@ static void mvebu_pcie_setup_wins(struct mvebu_pcie_port *port)
size = 1 << fls(size);
/* Setup BAR[1] to all DRAM banks. */
- writel(dram->cs[0].base, port->base + PCIE_BAR_LO_OFF(1));
- writel(0, port->base + PCIE_BAR_HI_OFF(1));
- writel(((size - 1) & 0xffff0000) | 1,
- port->base + PCIE_BAR_CTRL_OFF(1));
+ mvebu_writel(port, dram->cs[0].base, PCIE_BAR_LO_OFF(1));
+ mvebu_writel(port, 0, PCIE_BAR_HI_OFF(1));
+ mvebu_writel(port, ((size - 1) & 0xffff0000) | 1,
+ PCIE_BAR_CTRL_OFF(1));
}
static void mvebu_pcie_setup_hw(struct mvebu_pcie_port *port)
{
- u16 cmd;
- u32 mask;
+ u32 cmd, mask;
/* Point PCIe unit MBUS decode windows to DRAM space. */
mvebu_pcie_setup_wins(port);
/* Master + slave enable. */
- cmd = readw(port->base + PCIE_CMD_OFF);
+ cmd = mvebu_readl(port, PCIE_CMD_OFF);
cmd |= PCI_COMMAND_IO;
cmd |= PCI_COMMAND_MEMORY;
cmd |= PCI_COMMAND_MASTER;
- writew(cmd, port->base + PCIE_CMD_OFF);
+ mvebu_writel(port, cmd, PCIE_CMD_OFF);
/* Enable interrupt lines A-D. */
- mask = readl(port->base + PCIE_MASK_OFF);
+ mask = mvebu_readl(port, PCIE_MASK_OFF);
mask |= PCIE_MASK_ENABLE_INTS;
- writel(mask, port->base + PCIE_MASK_OFF);
+ mvebu_writel(port, mask, PCIE_MASK_OFF);
}
static int mvebu_pcie_hw_rd_conf(struct mvebu_pcie_port *port,
struct pci_bus *bus,
u32 devfn, int where, int size, u32 *val)
{
- writel(PCIE_CONF_ADDR(bus->number, devfn, where),
- port->base + PCIE_CONF_ADDR_OFF);
+ mvebu_writel(port, PCIE_CONF_ADDR(bus->number, devfn, where),
+ PCIE_CONF_ADDR_OFF);
- *val = readl(port->base + PCIE_CONF_DATA_OFF);
+ *val = mvebu_readl(port, PCIE_CONF_DATA_OFF);
if (size == 1)
*val = (*val >> (8 * (where & 3))) & 0xff;
@@ -265,21 +275,24 @@ static int mvebu_pcie_hw_wr_conf(struct mvebu_pcie_port *port,
struct pci_bus *bus,
u32 devfn, int where, int size, u32 val)
{
- int ret = PCIBIOS_SUCCESSFUL;
+ u32 _val, shift = 8 * (where & 3);
- writel(PCIE_CONF_ADDR(bus->number, devfn, where),
- port->base + PCIE_CONF_ADDR_OFF);
+ mvebu_writel(port, PCIE_CONF_ADDR(bus->number, devfn, where),
+ PCIE_CONF_ADDR_OFF);
+ _val = mvebu_readl(port, PCIE_CONF_DATA_OFF);
if (size == 4)
- writel(val, port->base + PCIE_CONF_DATA_OFF);
+ _val = val;
else if (size == 2)
- writew(val, port->base + PCIE_CONF_DATA_OFF + (where & 3));
+ _val = (_val & ~(0xffff << shift)) | ((val & 0xffff) << shift);
else if (size == 1)
- writeb(val, port->base + PCIE_CONF_DATA_OFF + (where & 3));
+ _val = (_val & ~(0xff << shift)) | ((val & 0xff) << shift);
else
- ret = PCIBIOS_BAD_REGISTER_NUMBER;
+ return PCIBIOS_BAD_REGISTER_NUMBER;
- return ret;
+ mvebu_writel(port, _val, PCIE_CONF_DATA_OFF);
+
+ return PCIBIOS_SUCCESSFUL;
}
static void mvebu_pcie_handle_iobase_change(struct mvebu_pcie_port *port)
--
1.7.0.4
^ permalink raw reply related [flat|nested] 7+ messages in thread* Re: [PATCH v2 3/3] PCI: mvebu: add wrapped I/O access functions
2013-08-29 12:36 ` [PATCH v2 " Seungwon Jeon
@ 2013-08-29 20:11 ` Bjorn Helgaas
0 siblings, 0 replies; 7+ messages in thread
From: Bjorn Helgaas @ 2013-08-29 20:11 UTC (permalink / raw)
To: Seungwon Jeon; +Cc: linux-pci@vger.kernel.org, Thomas Petazzoni, Jason Cooper
On Thu, Aug 29, 2013 at 6:36 AM, Seungwon Jeon <tgih.jun@samsung.com> wrote:
> read/write operation for I/O mem is wrapped with hiding
> base address inside in order to simplify the usage.
>
> Signed-off-by: Seungwon Jeon <tgih.jun@samsung.com>
This depends on some mvebu changes that aren't in my tree. If you
want me to apply it, please obtain an ack from Thomas and resend it
after v3.12-rc1.
^ permalink raw reply [flat|nested] 7+ messages in thread
* [PATCH v3] PCI: mvebu: add I/O access wrappers
2013-08-28 12:14 ` Thomas Petazzoni
2013-08-29 9:35 ` Seungwon Jeon
2013-08-29 12:36 ` [PATCH v2 " Seungwon Jeon
@ 2013-10-04 9:58 ` Seungwon Jeon
2013-10-08 17:25 ` Jason Cooper
2 siblings, 1 reply; 7+ messages in thread
From: Seungwon Jeon @ 2013-10-04 9:58 UTC (permalink / raw)
To: linux-pci
Cc: 'Thomas Petazzoni', 'Bjorn Helgaas',
'Jason Cooper'
This change adds wrapper functions for MMIO access to PCIe IP block.
And some 8/16-bit access are replaced by 32-bit.
Signed-off-by: Seungwon Jeon <tgih.jun@samsung.com>
---
Changes in v3:
- Just rebased
- Modified commit message
Changes in v2:
- Only 32-bit accessors are kept(from Thomas Petazzoni)
drivers/pci/host/pci-mvebu.c | 97 ++++++++++++++++++++++++------------------
1 files changed, 55 insertions(+), 42 deletions(-)
diff --git a/drivers/pci/host/pci-mvebu.c b/drivers/pci/host/pci-mvebu.c
index 729d5a1..584db1c 100644
--- a/drivers/pci/host/pci-mvebu.c
+++ b/drivers/pci/host/pci-mvebu.c
@@ -133,29 +133,39 @@ struct mvebu_pcie_port {
size_t iowin_size;
};
+static inline void mvebu_writel(struct mvebu_pcie_port *port, u32 val, u32 reg)
+{
+ writel(val, port->base + reg);
+}
+
+static inline u32 mvebu_readl(struct mvebu_pcie_port *port, u32 reg)
+{
+ return readl(port->base + reg);
+}
+
static bool mvebu_pcie_link_up(struct mvebu_pcie_port *port)
{
- return !(readl(port->base + PCIE_STAT_OFF) & PCIE_STAT_LINK_DOWN);
+ return !(mvebu_readl(port, PCIE_STAT_OFF) & PCIE_STAT_LINK_DOWN);
}
static void mvebu_pcie_set_local_bus_nr(struct mvebu_pcie_port *port, int nr)
{
u32 stat;
- stat = readl(port->base + PCIE_STAT_OFF);
+ stat = mvebu_readl(port, PCIE_STAT_OFF);
stat &= ~PCIE_STAT_BUS;
stat |= nr << 8;
- writel(stat, port->base + PCIE_STAT_OFF);
+ mvebu_writel(port, stat, PCIE_STAT_OFF);
}
static void mvebu_pcie_set_local_dev_nr(struct mvebu_pcie_port *port, int nr)
{
u32 stat;
- stat = readl(port->base + PCIE_STAT_OFF);
+ stat = mvebu_readl(port, PCIE_STAT_OFF);
stat &= ~PCIE_STAT_DEV;
stat |= nr << 16;
- writel(stat, port->base + PCIE_STAT_OFF);
+ mvebu_writel(port, stat, PCIE_STAT_OFF);
}
/*
@@ -173,33 +183,34 @@ static void __init mvebu_pcie_setup_wins(struct mvebu_pcie_port *port)
/* First, disable and clear BARs and windows. */
for (i = 1; i < 3; i++) {
- writel(0, port->base + PCIE_BAR_CTRL_OFF(i));
- writel(0, port->base + PCIE_BAR_LO_OFF(i));
- writel(0, port->base + PCIE_BAR_HI_OFF(i));
+ mvebu_writel(port, 0, PCIE_BAR_CTRL_OFF(i));
+ mvebu_writel(port, 0, PCIE_BAR_LO_OFF(i));
+ mvebu_writel(port, 0, PCIE_BAR_HI_OFF(i));
}
for (i = 0; i < 5; i++) {
- writel(0, port->base + PCIE_WIN04_CTRL_OFF(i));
- writel(0, port->base + PCIE_WIN04_BASE_OFF(i));
- writel(0, port->base + PCIE_WIN04_REMAP_OFF(i));
+ mvebu_writel(port, 0, PCIE_WIN04_CTRL_OFF(i));
+ mvebu_writel(port, 0, PCIE_WIN04_BASE_OFF(i));
+ mvebu_writel(port, 0, PCIE_WIN04_REMAP_OFF(i));
}
- writel(0, port->base + PCIE_WIN5_CTRL_OFF);
- writel(0, port->base + PCIE_WIN5_BASE_OFF);
- writel(0, port->base + PCIE_WIN5_REMAP_OFF);
+ mvebu_writel(port, 0, PCIE_WIN5_CTRL_OFF);
+ mvebu_writel(port, 0, PCIE_WIN5_BASE_OFF);
+ mvebu_writel(port, 0, PCIE_WIN5_REMAP_OFF);
/* Setup windows for DDR banks. Count total DDR size on the fly. */
size = 0;
for (i = 0; i < dram->num_cs; i++) {
const struct mbus_dram_window *cs = dram->cs + i;
- writel(cs->base & 0xffff0000,
- port->base + PCIE_WIN04_BASE_OFF(i));
- writel(0, port->base + PCIE_WIN04_REMAP_OFF(i));
- writel(((cs->size - 1) & 0xffff0000) |
- (cs->mbus_attr << 8) |
- (dram->mbus_dram_target_id << 4) | 1,
- port->base + PCIE_WIN04_CTRL_OFF(i));
+ mvebu_writel(port, cs->base & 0xffff0000,
+ PCIE_WIN04_BASE_OFF(i));
+ mvebu_writel(port, 0, PCIE_WIN04_REMAP_OFF(i));
+ mvebu_writel(port,
+ ((cs->size - 1) & 0xffff0000) |
+ (cs->mbus_attr << 8) |
+ (dram->mbus_dram_target_id << 4) | 1,
+ PCIE_WIN04_CTRL_OFF(i));
size += cs->size;
}
@@ -209,41 +220,40 @@ static void __init mvebu_pcie_setup_wins(struct mvebu_pcie_port *port)
size = 1 << fls(size);
/* Setup BAR[1] to all DRAM banks. */
- writel(dram->cs[0].base, port->base + PCIE_BAR_LO_OFF(1));
- writel(0, port->base + PCIE_BAR_HI_OFF(1));
- writel(((size - 1) & 0xffff0000) | 1,
- port->base + PCIE_BAR_CTRL_OFF(1));
+ mvebu_writel(port, dram->cs[0].base, PCIE_BAR_LO_OFF(1));
+ mvebu_writel(port, 0, PCIE_BAR_HI_OFF(1));
+ mvebu_writel(port, ((size - 1) & 0xffff0000) | 1,
+ PCIE_BAR_CTRL_OFF(1));
}
static void __init mvebu_pcie_setup_hw(struct mvebu_pcie_port *port)
{
- u16 cmd;
- u32 mask;
+ u32 cmd, mask;
/* Point PCIe unit MBUS decode windows to DRAM space. */
mvebu_pcie_setup_wins(port);
/* Master + slave enable. */
- cmd = readw(port->base + PCIE_CMD_OFF);
+ cmd = mvebu_readl(port, PCIE_CMD_OFF);
cmd |= PCI_COMMAND_IO;
cmd |= PCI_COMMAND_MEMORY;
cmd |= PCI_COMMAND_MASTER;
- writew(cmd, port->base + PCIE_CMD_OFF);
+ mvebu_writel(port, cmd, PCIE_CMD_OFF);
/* Enable interrupt lines A-D. */
- mask = readl(port->base + PCIE_MASK_OFF);
+ mask = mvebu_readl(port, PCIE_MASK_OFF);
mask |= PCIE_MASK_ENABLE_INTS;
- writel(mask, port->base + PCIE_MASK_OFF);
+ mvebu_writel(port, mask, PCIE_MASK_OFF);
}
static int mvebu_pcie_hw_rd_conf(struct mvebu_pcie_port *port,
struct pci_bus *bus,
u32 devfn, int where, int size, u32 *val)
{
- writel(PCIE_CONF_ADDR(bus->number, devfn, where),
- port->base + PCIE_CONF_ADDR_OFF);
+ mvebu_writel(port, PCIE_CONF_ADDR(bus->number, devfn, where),
+ PCIE_CONF_ADDR_OFF);
- *val = readl(port->base + PCIE_CONF_DATA_OFF);
+ *val = mvebu_readl(port, PCIE_CONF_DATA_OFF);
if (size == 1)
*val = (*val >> (8 * (where & 3))) & 0xff;
@@ -257,21 +267,24 @@ static int mvebu_pcie_hw_wr_conf(struct mvebu_pcie_port *port,
struct pci_bus *bus,
u32 devfn, int where, int size, u32 val)
{
- int ret = PCIBIOS_SUCCESSFUL;
+ u32 _val, shift = 8 * (where & 3);
- writel(PCIE_CONF_ADDR(bus->number, devfn, where),
- port->base + PCIE_CONF_ADDR_OFF);
+ mvebu_writel(port, PCIE_CONF_ADDR(bus->number, devfn, where),
+ PCIE_CONF_ADDR_OFF);
+ _val = mvebu_readl(port, PCIE_CONF_DATA_OFF);
if (size == 4)
- writel(val, port->base + PCIE_CONF_DATA_OFF);
+ _val = val;
else if (size == 2)
- writew(val, port->base + PCIE_CONF_DATA_OFF + (where & 3));
+ _val = (_val & ~(0xffff << shift)) | ((val & 0xffff) << shift);
else if (size == 1)
- writeb(val, port->base + PCIE_CONF_DATA_OFF + (where & 3));
+ _val = (_val & ~(0xff << shift)) | ((val & 0xff) << shift);
else
- ret = PCIBIOS_BAD_REGISTER_NUMBER;
+ return PCIBIOS_BAD_REGISTER_NUMBER;
- return ret;
+ mvebu_writel(port, _val, PCIE_CONF_DATA_OFF);
+
+ return PCIBIOS_SUCCESSFUL;
}
static void mvebu_pcie_handle_iobase_change(struct mvebu_pcie_port *port)
--
1.7.0.4
^ permalink raw reply related [flat|nested] 7+ messages in thread* Re: [PATCH v3] PCI: mvebu: add I/O access wrappers
2013-10-04 9:58 ` [PATCH v3] PCI: mvebu: add I/O access wrappers Seungwon Jeon
@ 2013-10-08 17:25 ` Jason Cooper
0 siblings, 0 replies; 7+ messages in thread
From: Jason Cooper @ 2013-10-08 17:25 UTC (permalink / raw)
To: Seungwon Jeon
Cc: linux-pci, 'Thomas Petazzoni', 'Bjorn Helgaas'
On Fri, Oct 04, 2013 at 06:58:15PM +0900, Seungwon Jeon wrote:
> This change adds wrapper functions for MMIO access to PCIe IP block.
> And some 8/16-bit access are replaced by 32-bit.
>
> Signed-off-by: Seungwon Jeon <tgih.jun@samsung.com>
> ---
> Changes in v3:
> - Just rebased
> - Modified commit message
>
> Changes in v2:
> - Only 32-bit accessors are kept(from Thomas Petazzoni)
>
> drivers/pci/host/pci-mvebu.c | 97 ++++++++++++++++++++++++------------------
> 1 files changed, 55 insertions(+), 42 deletions(-)
Applied to mvebu/drivers
thx,
Jason.
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