From: Konrad Dybcio <konrad.dybcio@linaro.org>
To: Abel Vesa <abel.vesa@linaro.org>
Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>,
lpieralisi@kernel.org, kw@linux.com, andersson@kernel.org,
bhelgaas@google.com, linux-arm-msm@vger.kernel.org,
linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH] PCI: qcom: Add interconnect bandwidth for PCIe Gen4
Date: Mon, 25 Sep 2023 12:40:34 +0200 [thread overview]
Message-ID: <09058de7-e207-414b-ab4c-88f0cbde9c22@linaro.org> (raw)
In-Reply-To: <ZRFjAIYQQZnbNIdt@linaro.org>
On 25.09.2023 12:37, Abel Vesa wrote:
> On 23-09-25 12:34:53, Konrad Dybcio wrote:
>> On 25.09.2023 12:33, Abel Vesa wrote:
>>> On 23-09-25 10:57:47, Konrad Dybcio wrote:
>>>> On 24.09.2023 18:07, Manivannan Sadhasivam wrote:
>>>>> PCIe Gen4 supports the interconnect bandwidth of 1969 MBps. So let's add
>>>>> the bandwidth support in the driver. Otherwise, the default bandwidth of
>>>>> 985 MBps will be used.
>>>>>
>>>>> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
>>>>> ---
>>>>> drivers/pci/controller/dwc/pcie-qcom.c | 7 +++++--
>>>>> 1 file changed, 5 insertions(+), 2 deletions(-)
>>>>>
>>>>> diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
>>>>> index 297442c969b6..6853123f92c1 100644
>>>>> --- a/drivers/pci/controller/dwc/pcie-qcom.c
>>>>> +++ b/drivers/pci/controller/dwc/pcie-qcom.c
>>>>> @@ -1384,11 +1384,14 @@ static void qcom_pcie_icc_update(struct qcom_pcie *pcie)
>>>>> case 2:
>>>>> bw = MBps_to_icc(500);
>>>>> break;
>>>>> + case 3:
>>>>> + bw = MBps_to_icc(985);
>>>>> + break;
>>>>> default:
>>>>> WARN_ON_ONCE(1);
>>>>> fallthrough;
>>>>> - case 3:
>>>>> - bw = MBps_to_icc(985);
>>>>> + case 4:
>>>>> + bw = MBps_to_icc(1969);
>>>>> break;
>>>> Are you adding case 4 under `default`? That looks.. bizzare..
>>>
>>> That's intentional. You want it to use 1969MBps if there is a different
>>> gen value. AFAIU.
>> Gah right, then the commit message is wrong.
>
> Yep, should be: "Otherwise, the default bandwidth of 1969 MBps will be
> used."
>
> But maybe we should not default to that. Maybe we should still default
> to 985 MBps.
Perhaps we shouldn't have a default at all..
E.g. if the gen5 bus may get clogged if we exceed gen4
limits
Konrad
next prev parent reply other threads:[~2023-09-25 10:40 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-09-24 16:07 [PATCH] PCI: qcom: Add interconnect bandwidth for PCIe Gen4 Manivannan Sadhasivam
2023-09-25 8:57 ` Konrad Dybcio
2023-09-25 10:33 ` Abel Vesa
2023-09-25 10:34 ` Konrad Dybcio
2023-09-25 10:37 ` Abel Vesa
2023-09-25 10:40 ` Konrad Dybcio [this message]
2023-09-27 12:58 ` Manivannan Sadhasivam
2023-09-25 10:35 ` Abel Vesa
2023-09-26 21:08 ` Bjorn Helgaas
2023-09-27 13:04 ` Manivannan Sadhasivam
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