From: Manivannan Sadhasivam <mani@kernel.org>
To: frank.li@nxp.com, l.stach@pengutronix.de, lpieralisi@kernel.org,
kwilczynski@kernel.org, robh@kernel.org, bhelgaas@google.com,
shawnguo@kernel.org, s.hauer@pengutronix.de,
kernel@pengutronix.de, festevam@gmail.com,
Richard Zhu <hongxing.zhu@nxp.com>
Cc: linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
imx@lists.linux.dev, linux-kernel@vger.kernel.org,
Frank Li <Frank.Li@nxp.com>
Subject: Re: [PATCH v2] PCI: imx6: Correct the epc_features of i.MX8M chips
Date: Tue, 01 Jul 2025 19:57:23 +0530 [thread overview]
Message-ID: <175138004317.29152.1836707203802204355.b4-ty@kernel.org> (raw)
In-Reply-To: <20250617073441.3228400-1-hongxing.zhu@nxp.com>
On Tue, 17 Jun 2025 15:34:41 +0800, Richard Zhu wrote:
> i.MX8MQ PCIes have three 64-bit BAR0/2/4 capable and programmable BARs.
> But i.MX8MM and i.MX8MP PCIes only have BAR0/BAR2 64bit programmable
> BARs, and one 256 bytes size fixed BAR4.
>
> Correct the epc_features for i.MX8MM and i.MX8MP PCIes here. i.MX8MQ is
> the same as i.MX8QXP, so set i.MX8MQ's epc_features to
> imx8q_pcie_epc_features.
>
> [...]
Applied, thanks!
[1/1] PCI: imx6: Correct the epc_features of i.MX8M chips
commit: 66ee525537be816b2accf4ad28ad33cd299ea492
Best regards,
--
Manivannan Sadhasivam <mani@kernel.org>
next prev parent reply other threads:[~2025-07-01 14:27 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-06-17 7:34 [PATCH v2] PCI: imx6: Correct the epc_features of i.MX8M chips Richard Zhu
2025-07-01 14:27 ` Manivannan Sadhasivam [this message]
2025-07-07 19:34 ` Bjorn Helgaas
2025-07-08 7:34 ` Hongxing Zhu
2025-07-08 7:41 ` mani
2025-07-08 15:48 ` Bjorn Helgaas
2025-07-09 3:37 ` Hongxing Zhu
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