[PATCH v2] PCI: imx6: Correct the epc_features of i.MX8M chips

[PATCH v2] PCI: imx6: Correct the epc_features of i.MX8M chips

[Richard Zhu]

i.MX8MQ PCIes have three 64-bit BAR0/2/4 capable and programmable BARs.
But i.MX8MM and i.MX8MP PCIes only have BAR0/BAR2 64bit programmable
BARs, and one 256 bytes size fixed BAR4.

Correct the epc_features for i.MX8MM and i.MX8MP PCIes here. i.MX8MQ is
the same as i.MX8QXP, so set i.MX8MQ's epc_features to
imx8q_pcie_epc_features.

Fixes: 75c2f26da03f ("PCI: imx6: Add i.MX PCIe EP mode support")
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Reviewed-by: Frank Li <Frank.Li@nxp.com>
---
 drivers/pci/controller/dwc/pci-imx6.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c
index 5a38cfaf989b..9754cc6e09b9 100644
--- a/drivers/pci/controller/dwc/pci-imx6.c
+++ b/drivers/pci/controller/dwc/pci-imx6.c
@@ -1385,6 +1385,8 @@ static const struct pci_epc_features imx8m_pcie_epc_features = {
 	.msix_capable = false,
 	.bar[BAR_1] = { .type = BAR_RESERVED, },
 	.bar[BAR_3] = { .type = BAR_RESERVED, },
+	.bar[BAR_4] = { .type = BAR_FIXED, .fixed_size = SZ_256, },
+	.bar[BAR_5] = { .type = BAR_RESERVED, },
 	.align = SZ_64K,
 };
 
@@ -1912,7 +1914,7 @@ static const struct imx_pcie_drvdata drvdata[] = {
 		.mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE,
 		.mode_off[1] = IOMUXC_GPR12,
 		.mode_mask[1] = IMX8MQ_GPR12_PCIE2_CTRL_DEVICE_TYPE,
-		.epc_features = &imx8m_pcie_epc_features,
+		.epc_features = &imx8q_pcie_epc_features,
 		.init_phy = imx8mq_pcie_init_phy,
 		.enable_ref_clk = imx8mm_pcie_enable_ref_clk,
 	},
-- 
2.37.1

Re: [PATCH v2] PCI: imx6: Correct the epc_features of i.MX8M chips

[Manivannan Sadhasivam]

On Tue, 17 Jun 2025 15:34:41 +0800, Richard Zhu wrote:
> i.MX8MQ PCIes have three 64-bit BAR0/2/4 capable and programmable BARs.
> But i.MX8MM and i.MX8MP PCIes only have BAR0/BAR2 64bit programmable
> BARs, and one 256 bytes size fixed BAR4.
> 
> Correct the epc_features for i.MX8MM and i.MX8MP PCIes here. i.MX8MQ is
> the same as i.MX8QXP, so set i.MX8MQ's epc_features to
> imx8q_pcie_epc_features.
> 
> [...]

Applied, thanks!

[1/1] PCI: imx6: Correct the epc_features of i.MX8M chips
      commit: 66ee525537be816b2accf4ad28ad33cd299ea492

Best regards,
-- 
Manivannan Sadhasivam <mani@kernel.org>

Re: [PATCH v2] PCI: imx6: Correct the epc_features of i.MX8M chips

[Bjorn Helgaas]

On Tue, Jun 17, 2025 at 03:34:41PM +0800, Richard Zhu wrote:
> i.MX8MQ PCIes have three 64-bit BAR0/2/4 capable and programmable BARs.
> But i.MX8MM and i.MX8MP PCIes only have BAR0/BAR2 64bit programmable
> BARs, and one 256 bytes size fixed BAR4.
> 
> Correct the epc_features for i.MX8MM and i.MX8MP PCIes here. i.MX8MQ is
> the same as i.MX8QXP, so set i.MX8MQ's epc_features to
> imx8q_pcie_epc_features.
> 
> Fixes: 75c2f26da03f ("PCI: imx6: Add i.MX PCIe EP mode support")
> Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
> Reviewed-by: Frank Li <Frank.Li@nxp.com>

"Correct the epc_features" doesn't include any specific information,
and it's hard to extract the changes for a device from the commit log.

This is really two fixes that should be separated so the commit logs
can be specific:

  - For IMX8MQ_EP, use imx8q_pcie_epc_features (64-bit BARs 0, 2, 4)
    instead of imx8m_pcie_epc_features (64-bit BARs 0, 2).

  - For IMX8MM_EP and IMX8MP_EP, add fixed 256-byte BAR 4 in
    imx8m_pcie_epc_features.

> ---
>  drivers/pci/controller/dwc/pci-imx6.c | 4 +++-
>  1 file changed, 3 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c
> index 5a38cfaf989b..9754cc6e09b9 100644
> --- a/drivers/pci/controller/dwc/pci-imx6.c
> +++ b/drivers/pci/controller/dwc/pci-imx6.c
> @@ -1385,6 +1385,8 @@ static const struct pci_epc_features imx8m_pcie_epc_features = {
>  	.msix_capable = false,
>  	.bar[BAR_1] = { .type = BAR_RESERVED, },
>  	.bar[BAR_3] = { .type = BAR_RESERVED, },
> +	.bar[BAR_4] = { .type = BAR_FIXED, .fixed_size = SZ_256, },
> +	.bar[BAR_5] = { .type = BAR_RESERVED, },
>  	.align = SZ_64K,
>  };
>  
> @@ -1912,7 +1914,7 @@ static const struct imx_pcie_drvdata drvdata[] = {
>  		.mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE,
>  		.mode_off[1] = IOMUXC_GPR12,
>  		.mode_mask[1] = IMX8MQ_GPR12_PCIE2_CTRL_DEVICE_TYPE,
> -		.epc_features = &imx8m_pcie_epc_features,
> +		.epc_features = &imx8q_pcie_epc_features,
>  		.init_phy = imx8mq_pcie_init_phy,
>  		.enable_ref_clk = imx8mm_pcie_enable_ref_clk,
>  	},
> -- 
> 2.37.1
> 

RE: [PATCH v2] PCI: imx6: Correct the epc_features of i.MX8M chips

[Hongxing Zhu]

> -----Original Message-----
> From: Bjorn Helgaas <helgaas@kernel.org>
> Sent: 2025年7月8日 3:34
> To: Hongxing Zhu <hongxing.zhu@nxp.com>
> Cc: Frank Li <frank.li@nxp.com>; l.stach@pengutronix.de;
> lpieralisi@kernel.org; kwilczynski@kernel.org; mani@kernel.org;
> robh@kernel.org; bhelgaas@google.com; shawnguo@kernel.org;
> s.hauer@pengutronix.de; kernel@pengutronix.de; festevam@gmail.com;
> linux-pci@vger.kernel.org; linux-arm-kernel@lists.infradead.org;
> imx@lists.linux.dev; linux-kernel@vger.kernel.org
> Subject: Re: [PATCH v2] PCI: imx6: Correct the epc_features of i.MX8M chips
> 
> On Tue, Jun 17, 2025 at 03:34:41PM +0800, Richard Zhu wrote:
> > i.MX8MQ PCIes have three 64-bit BAR0/2/4 capable and programmable
> BARs.
> > But i.MX8MM and i.MX8MP PCIes only have BAR0/BAR2 64bit
> programmable
> > BARs, and one 256 bytes size fixed BAR4.
> >
> > Correct the epc_features for i.MX8MM and i.MX8MP PCIes here. i.MX8MQ
> > is the same as i.MX8QXP, so set i.MX8MQ's epc_features to
> > imx8q_pcie_epc_features.
> >
> > Fixes: 75c2f26da03f ("PCI: imx6: Add i.MX PCIe EP mode support")
> > Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
> > Reviewed-by: Frank Li <Frank.Li@nxp.com>
> 
> "Correct the epc_features" doesn't include any specific information, and it's
> hard to extract the changes for a device from the commit log.
> 
> This is really two fixes that should be separated so the commit logs can be
> specific:
Yes, it's right.
Since it's just one line change for i.MX8MQ. So, I combine the changes into
this commit for i.MX8M chips.

Hi Mani:
Since it had been applied, I don't know how to proceed.
Should I separate this commit into two patches, and re-send them again?
Thanks.

Best Regards
Richard Zhu
> 
>   - For IMX8MQ_EP, use imx8q_pcie_epc_features (64-bit BARs 0, 2, 4)
>     instead of imx8m_pcie_epc_features (64-bit BARs 0, 2).
> 
>   - For IMX8MM_EP and IMX8MP_EP, add fixed 256-byte BAR 4 in
>     imx8m_pcie_epc_features.
> 
> > ---
> >  drivers/pci/controller/dwc/pci-imx6.c | 4 +++-
> >  1 file changed, 3 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/pci/controller/dwc/pci-imx6.c
> > b/drivers/pci/controller/dwc/pci-imx6.c
> > index 5a38cfaf989b..9754cc6e09b9 100644
> > --- a/drivers/pci/controller/dwc/pci-imx6.c
> > +++ b/drivers/pci/controller/dwc/pci-imx6.c
> > @@ -1385,6 +1385,8 @@ static const struct pci_epc_features
> imx8m_pcie_epc_features = {
> >  	.msix_capable = false,
> >  	.bar[BAR_1] = { .type = BAR_RESERVED, },
> >  	.bar[BAR_3] = { .type = BAR_RESERVED, },
> > +	.bar[BAR_4] = { .type = BAR_FIXED, .fixed_size = SZ_256, },
> > +	.bar[BAR_5] = { .type = BAR_RESERVED, },
> >  	.align = SZ_64K,
> >  };
> >
> > @@ -1912,7 +1914,7 @@ static const struct imx_pcie_drvdata drvdata[] = {
> >  		.mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE,
> >  		.mode_off[1] = IOMUXC_GPR12,
> >  		.mode_mask[1] = IMX8MQ_GPR12_PCIE2_CTRL_DEVICE_TYPE,
> > -		.epc_features = &imx8m_pcie_epc_features,
> > +		.epc_features = &imx8q_pcie_epc_features,
> >  		.init_phy = imx8mq_pcie_init_phy,
> >  		.enable_ref_clk = imx8mm_pcie_enable_ref_clk,
> >  	},
> > --
> > 2.37.1
> >

Re: [PATCH v2] PCI: imx6: Correct the epc_features of i.MX8M chips

[mani]

On Tue, Jul 08, 2025 at 07:34:57AM GMT, Hongxing Zhu wrote:
> > -----Original Message-----
> > From: Bjorn Helgaas <helgaas@kernel.org>
> > Sent: 2025年7月8日 3:34
> > To: Hongxing Zhu <hongxing.zhu@nxp.com>
> > Cc: Frank Li <frank.li@nxp.com>; l.stach@pengutronix.de;
> > lpieralisi@kernel.org; kwilczynski@kernel.org; mani@kernel.org;
> > robh@kernel.org; bhelgaas@google.com; shawnguo@kernel.org;
> > s.hauer@pengutronix.de; kernel@pengutronix.de; festevam@gmail.com;
> > linux-pci@vger.kernel.org; linux-arm-kernel@lists.infradead.org;
> > imx@lists.linux.dev; linux-kernel@vger.kernel.org
> > Subject: Re: [PATCH v2] PCI: imx6: Correct the epc_features of i.MX8M chips
> > 
> > On Tue, Jun 17, 2025 at 03:34:41PM +0800, Richard Zhu wrote:
> > > i.MX8MQ PCIes have three 64-bit BAR0/2/4 capable and programmable
> > BARs.
> > > But i.MX8MM and i.MX8MP PCIes only have BAR0/BAR2 64bit
> > programmable
> > > BARs, and one 256 bytes size fixed BAR4.
> > >
> > > Correct the epc_features for i.MX8MM and i.MX8MP PCIes here. i.MX8MQ
> > > is the same as i.MX8QXP, so set i.MX8MQ's epc_features to
> > > imx8q_pcie_epc_features.
> > >
> > > Fixes: 75c2f26da03f ("PCI: imx6: Add i.MX PCIe EP mode support")
> > > Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
> > > Reviewed-by: Frank Li <Frank.Li@nxp.com>
> > 
> > "Correct the epc_features" doesn't include any specific information, and it's
> > hard to extract the changes for a device from the commit log.
> > 
> > This is really two fixes that should be separated so the commit logs can be
> > specific:
> Yes, it's right.
> Since it's just one line change for i.MX8MQ. So, I combine the changes into
> this commit for i.MX8M chips.
> 
> Hi Mani:
> Since it had been applied, I don't know how to proceed.
> Should I separate this commit into two patches, and re-send them again?
> Thanks.
> 

I've now dropped the patch from controller/imx6. Please resend them. Also, CC
the stable list with relevant Fixes tag.

- Mani

> Best Regards
> Richard Zhu
> > 
> >   - For IMX8MQ_EP, use imx8q_pcie_epc_features (64-bit BARs 0, 2, 4)
> >     instead of imx8m_pcie_epc_features (64-bit BARs 0, 2).
> > 
> >   - For IMX8MM_EP and IMX8MP_EP, add fixed 256-byte BAR 4 in
> >     imx8m_pcie_epc_features.
> > 
> > > ---
> > >  drivers/pci/controller/dwc/pci-imx6.c | 4 +++-
> > >  1 file changed, 3 insertions(+), 1 deletion(-)
> > >
> > > diff --git a/drivers/pci/controller/dwc/pci-imx6.c
> > > b/drivers/pci/controller/dwc/pci-imx6.c
> > > index 5a38cfaf989b..9754cc6e09b9 100644
> > > --- a/drivers/pci/controller/dwc/pci-imx6.c
> > > +++ b/drivers/pci/controller/dwc/pci-imx6.c
> > > @@ -1385,6 +1385,8 @@ static const struct pci_epc_features
> > imx8m_pcie_epc_features = {
> > >  	.msix_capable = false,
> > >  	.bar[BAR_1] = { .type = BAR_RESERVED, },
> > >  	.bar[BAR_3] = { .type = BAR_RESERVED, },
> > > +	.bar[BAR_4] = { .type = BAR_FIXED, .fixed_size = SZ_256, },
> > > +	.bar[BAR_5] = { .type = BAR_RESERVED, },
> > >  	.align = SZ_64K,
> > >  };
> > >
> > > @@ -1912,7 +1914,7 @@ static const struct imx_pcie_drvdata drvdata[] = {
> > >  		.mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE,
> > >  		.mode_off[1] = IOMUXC_GPR12,
> > >  		.mode_mask[1] = IMX8MQ_GPR12_PCIE2_CTRL_DEVICE_TYPE,
> > > -		.epc_features = &imx8m_pcie_epc_features,
> > > +		.epc_features = &imx8q_pcie_epc_features,
> > >  		.init_phy = imx8mq_pcie_init_phy,
> > >  		.enable_ref_clk = imx8mm_pcie_enable_ref_clk,
> > >  	},
> > > --
> > > 2.37.1
> > >

-- 
மணிவண்ணன் சதாசிவம்

Re: [PATCH v2] PCI: imx6: Correct the epc_features of i.MX8M chips

[Bjorn Helgaas]

On Tue, Jul 08, 2025 at 07:34:57AM +0000, Hongxing Zhu wrote:
> > -----Original Message-----
> > From: Bjorn Helgaas <helgaas@kernel.org>
> ...
> > On Tue, Jun 17, 2025 at 03:34:41PM +0800, Richard Zhu wrote:
> > > i.MX8MQ PCIes have three 64-bit BAR0/2/4 capable and
> > > programmable BARs.  But i.MX8MM and i.MX8MP PCIes only have
> > > BAR0/BAR2 64bit programmable BARs, and one 256 bytes size fixed
> > > BAR4.
> > >
> > > Correct the epc_features for i.MX8MM and i.MX8MP PCIes here.
> > > i.MX8MQ is the same as i.MX8QXP, so set i.MX8MQ's epc_features
> > > to imx8q_pcie_epc_features.
> > >
> > > Fixes: 75c2f26da03f ("PCI: imx6: Add i.MX PCIe EP mode support")
> > > Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
> > > Reviewed-by: Frank Li <Frank.Li@nxp.com>
> > 
> > "Correct the epc_features" doesn't include any specific
> > information, and it's hard to extract the changes for a device
> > from the commit log.
> > 
> > This is really two fixes that should be separated so the commit
> > logs can be specific:
>
> Yes, it's right.
> Since it's just one line change for i.MX8MQ. So, I combine the changes into
> this commit for i.MX8M chips.

I want to split them to make it easy for users to understand which
changes are relevant to them.  E.g., I have an i.MX8MQ system; do I
need this change and what does it mean for me?  Is it going to fix a
problem I've been seeing?

> >   - For IMX8MQ_EP, use imx8q_pcie_epc_features (64-bit BARs 0, 2, 4)
> >     instead of imx8m_pcie_epc_features (64-bit BARs 0, 2).
> > 
> >   - For IMX8MM_EP and IMX8MP_EP, add fixed 256-byte BAR 4 in
> >     imx8m_pcie_epc_features.

RE: [PATCH v2] PCI: imx6: Correct the epc_features of i.MX8M chips

[Hongxing Zhu]

> -----Original Message-----
> From: Bjorn Helgaas <helgaas@kernel.org>
> Sent: 2025年7月8日 23:48
> To: Hongxing Zhu <hongxing.zhu@nxp.com>
> Cc: mani@kernel.org; Frank Li <frank.li@nxp.com>; l.stach@pengutronix.de;
> lpieralisi@kernel.org; kwilczynski@kernel.org; robh@kernel.org;
> bhelgaas@google.com; shawnguo@kernel.org; s.hauer@pengutronix.de;
> kernel@pengutronix.de; festevam@gmail.com; linux-pci@vger.kernel.org;
> linux-arm-kernel@lists.infradead.org; imx@lists.linux.dev;
> linux-kernel@vger.kernel.org
> Subject: Re: [PATCH v2] PCI: imx6: Correct the epc_features of i.MX8M chips
> 
> On Tue, Jul 08, 2025 at 07:34:57AM +0000, Hongxing Zhu wrote:
> > > -----Original Message-----
> > > From: Bjorn Helgaas <helgaas@kernel.org>
> > ...
> > > On Tue, Jun 17, 2025 at 03:34:41PM +0800, Richard Zhu wrote:
> > > > i.MX8MQ PCIes have three 64-bit BAR0/2/4 capable and programmable
> > > > BARs.  But i.MX8MM and i.MX8MP PCIes only have
> > > > BAR0/BAR2 64bit programmable BARs, and one 256 bytes size fixed
> > > > BAR4.
> > > >
> > > > Correct the epc_features for i.MX8MM and i.MX8MP PCIes here.
> > > > i.MX8MQ is the same as i.MX8QXP, so set i.MX8MQ's epc_features to
> > > > imx8q_pcie_epc_features.
> > > >
> > > > Fixes: 75c2f26da03f ("PCI: imx6: Add i.MX PCIe EP mode support")
> > > > Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
> > > > Reviewed-by: Frank Li <Frank.Li@nxp.com>
> > >
> > > "Correct the epc_features" doesn't include any specific information,
> > > and it's hard to extract the changes for a device from the commit
> > > log.
> > >
> > > This is really two fixes that should be separated so the commit logs
> > > can be specific:
> >
> > Yes, it's right.
> > Since it's just one line change for i.MX8MQ. So, I combine the changes
> > into this commit for i.MX8M chips.
> 
> I want to split them to make it easy for users to understand which changes are
> relevant to them.  E.g., I have an i.MX8MQ system; do I need this change and
> what does it mean for me?  Is it going to fix a problem I've been seeing?
Understood. Thanks for your comments.
Due to the ambiguous information, the previous epc_feature was wrongly
 defined.

Best Regards
Richard Zhu
> 
> > >   - For IMX8MQ_EP, use imx8q_pcie_epc_features (64-bit BARs 0, 2, 4)
> > >     instead of imx8m_pcie_epc_features (64-bit BARs 0, 2).
> > >
> > >   - For IMX8MM_EP and IMX8MP_EP, add fixed 256-byte BAR 4 in
> > >     imx8m_pcie_epc_features.