From: Manivannan Sadhasivam <mani@kernel.org>
To: linux-pci@vger.kernel.org,
Marek Vasut <marek.vasut+renesas@mailbox.org>
Cc: "Krzysztof Wilczyński" <kwilczynski@kernel.org>,
"Bjorn Helgaas" <bhelgaas@google.com>,
"Geert Uytterhoeven" <geert+renesas@glider.be>,
"Lorenzo Pieralisi" <lpieralisi@kernel.org>,
"Magnus Damm" <magnus.damm@gmail.com>,
"Rob Herring" <robh@kernel.org>,
"Yoshihiro Shimoda" <yoshihiro.shimoda.uh@renesas.com>,
linux-renesas-soc@vger.kernel.org
Subject: Re: [PATCH] PCI: rcar-gen4: Fix inverted break condition in PHY initialization
Date: Thu, 25 Sep 2025 22:06:10 +0530 [thread overview]
Message-ID: <175881817052.390261.13246190993626330141.b4-ty@kernel.org> (raw)
In-Reply-To: <20250915235910.47768-1-marek.vasut+renesas@mailbox.org>
On Tue, 16 Sep 2025 01:58:40 +0200, Marek Vasut wrote:
> R-Car V4H Reference Manual R19UH0186EJ0130 Rev.1.30 Apr. 21, 2025 page 4581
> Figure 104.3b Initial Setting of PCIEC(example), third quarter of the figure
> indicates that register 0xf8 should be polled until bit 18 becomes set to 1.
>
> Register 0xf8 bit 18 is 0 immediately after write to PCIERSTCTRL1 and is set
> to 1 in less than 1 ms afterward. The current readl_poll_timeout() break
> condition is inverted and returns when register 0xf8 bit 18 is set to 0,
> which in most cases means immediately. In case CONFIG_DEBUG_LOCK_ALLOC=y ,
> the timing changes just enough for the first readl_poll_timeout() poll to
> already read register 0xf8 bit 18 as 1 and afterward never read register
> 0xf8 bit 18 as 0, which leads to timeout and failure to start the PCIe
> controller.
>
> [...]
Applied, thanks!
[1/1] PCI: rcar-gen4: Fix inverted break condition in PHY initialization
commit: d0bf8864a2fe2120a5da51e4bca3e11747a8e797
Best regards,
--
Manivannan Sadhasivam <mani@kernel.org>
prev parent reply other threads:[~2025-09-25 16:36 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-09-15 23:58 [PATCH] PCI: rcar-gen4: Fix inverted break condition in PHY initialization Marek Vasut
2025-09-16 9:59 ` Geert Uytterhoeven
2025-09-16 13:39 ` Marek Vasut
2025-09-16 13:57 ` Geert Uytterhoeven
2025-09-16 16:31 ` Marek Vasut
2025-09-16 17:13 ` Bjorn Helgaas
2025-09-16 17:39 ` Marek Vasut
2025-09-16 18:15 ` Bjorn Helgaas
2025-09-16 22:09 ` Marek Vasut
2025-09-17 8:00 ` Geert Uytterhoeven
2025-09-17 13:44 ` Marek Vasut
2025-09-17 7:23 ` Geert Uytterhoeven
2025-09-18 3:16 ` Marek Vasut
2025-09-22 10:10 ` Geert Uytterhoeven
2025-09-22 15:17 ` Marek Vasut
2025-09-22 15:33 ` Geert Uytterhoeven
2025-09-22 15:49 ` Marek Vasut
2025-09-23 7:04 ` Geert Uytterhoeven
2025-09-25 16:36 ` Manivannan Sadhasivam [this message]
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