From: Aksh Garg <a-garg7@ti.com>
To: Hans Zhang <18255117159@163.com>, <bhelgaas@google.com>,
<lpieralisi@kernel.org>, <kwilczynski@kernel.org>,
<mani@kernel.org>, <hans.zhang@cixtech.com>
Cc: <robh@kernel.org>, <mpillai@cadence.com>,
<linux-pci@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
Siddharth Vadapalli <s-vadapalli@ti.com>
Subject: Re: [PATCH v4 2/2] PCI: cadence: Add debugfs property to provide LTSSM status of the PCIe link
Date: Wed, 13 May 2026 13:55:33 +0530 [thread overview]
Message-ID: <1e5b0f09-c04d-47e2-9657-70eab3d0e415@ti.com> (raw)
In-Reply-To: <75d71086-4d44-4dfa-b685-e18888c0c471@163.com>
On 13/05/26 12:07, Hans Zhang wrote:
>
>
> On 5/13/26 13:23, Aksh Garg wrote:
>>
>>
>> On 08/05/26 09:11, Hans Zhang wrote:
>>> Add the debugfs property to provide a view of the current link's LTSSM
>>> status from the Root Port device.
>>>
>>> Test example:
>>> # cat /sys/kernel/debug/cdns_pcie_a0c0000.pcie/ltssm_status
>>> L0_STATE (0x29)
>>>
>>> Signed-off-by: Hans Zhang <18255117159@163.com>
>>> ---
>>> Documentation/ABI/testing/debugfs-cdns-pcie | 5 +
>>> drivers/pci/controller/cadence/Kconfig | 9 +
>>> drivers/pci/controller/cadence/Makefile | 1 +
>>> drivers/pci/controller/cadence/pci-sky1.c | 3 +
>>> .../controller/cadence/pcie-cadence-debugfs.c | 208 ++++++++++++++++++
>>> .../pci/controller/cadence/pcie-cadence-ep.c | 3 +
>>> .../cadence/pcie-cadence-host-hpa.c | 20 +-
>>> .../controller/cadence/pcie-cadence-host.c | 9 +-
>>> drivers/pci/controller/cadence/pcie-cadence.h | 150 +++++++++++++
>>> 9 files changed, 406 insertions(+), 2 deletions(-)
>>> create mode 100644 Documentation/ABI/testing/debugfs-cdns-pcie
>>> create mode 100644 drivers/pci/controller/cadence/pcie-cadence-
>>> debugfs.c
>>>
>>> diff --git a/Documentation/ABI/testing/debugfs-cdns-pcie b/
>>> Documentation/ABI/testing/debugfs-cdns-pcie
>>> new file mode 100644
>>> index 000000000000..659ad2ab70e4
>>> --- /dev/null
>>> +++ b/Documentation/ABI/testing/debugfs-cdns-pcie
>>> @@ -0,0 +1,5 @@
>>> +What: /sys/kernel/debug/cdns_pcie_<dev>/ltssm_status
>>> +Date: March 2026
>>> +Contact: Hans Zhang <18255117159@163.com>
>>> +Description: (RO) Read will return the current PCIe LTSSM state
>>> in both
>>> + string and raw value.
>>> diff --git a/drivers/pci/controller/cadence/Kconfig b/drivers/pci/
>>> controller/cadence/Kconfig
>>> index 9e651d545973..cb010bc97aad 100644
>>> --- a/drivers/pci/controller/cadence/Kconfig
>>> +++ b/drivers/pci/controller/cadence/Kconfig
>>> @@ -6,6 +6,15 @@ menu "Cadence-based PCIe controllers"
>>> config PCIE_CADENCE
>>> tristate
>>> +config PCIE_CADENCE_DEBUGFS
>>> + tristate "Cadence PCIe debugfs entries"
>>> + depends on DEBUG_FS
>>> + depends on PCIE_CADENCE_HOST || PCIE_CADENCE_EP
>>> + help
>>> + Say Y here to enable debugfs entries for the PCIe controller.
>>> These
>>> + entries provide various debug features related to the
>>> controller and
>>> + the LTSSM status of link can be displayed.
>>> +
>>> config PCIE_CADENCE_HOST
>>> tristate
>>> depends on OF
>>
>> [...]
>>
>>> diff --git a/drivers/pci/controller/cadence/pcie-cadence.h b/drivers/
>>> pci/controller/cadence/pcie-cadence.h
>>> index 9a464cbaf073..a1c531fd2061 100644
>>> --- a/drivers/pci/controller/cadence/pcie-cadence.h
>>> +++ b/drivers/pci/controller/cadence/pcie-cadence.h
>>> @@ -42,6 +42,137 @@ enum cdns_pcie_reg_bank {
>>> REG_BANKS_MAX,
>>> };
>>> +enum cdns_pcie_ltssm {
>>> + CDNS_PCIE_LTSSM_DETECT_QUIET = 0,
>>> + CDNS_PCIE_LTSSM_DETECT_QUIET_ENTRY = 1,
>>> + CDNS_PCIE_LTSSM_DETECT_ACTIVE = 2,
>>> + CDNS_PCIE_LTSSM_DETECT_ACTIVE_1 = 3,
>>> + CDNS_PCIE_LTSSM_DETECT_ACTIVE_2 = 4,
>>> + CDNS_PCIE_LTSSM_DETECT_ACTIVE_3 = 5,
>>> + CDNS_PCIE_LTSSM_RCVR_DETECTED_ST = 6,
>>> + CDNS_PCIE_LTSSM_RCVR_DETECTED_1 = 7,
>>> + CDNS_PCIE_LTSSM_POLLING_ACTIVE = 8,
>>> + CDNS_PCIE_LTSSM_POLLING_ACTIVE_1 = 9,
>>> + CDNS_PCIE_LTSSM_POLLING_ACTIVE_2 = 10,
>>> + CDNS_PCIE_LTSSM_POLLING_ACTIVE_3 = 11,
>>> + CDNS_PCIE_LTSSM_POLLING_COMPLIANCE = 12,
>>> + CDNS_PCIE_LTSSM_POLLING_COMPLIANCE_1 = 13,
>>> + CDNS_PCIE_LTSSM_POLLING_CONFIG = 14,
>>> + CDNS_PCIE_LTSSM_POLLING_CONFIG_1 = 15,
>>> + CDNS_PCIE_LTSSM_POLLING_CONFIG_2 = 16,
>>> + CDNS_PCIE_LTSSM_CONFIG_LW_START_RC = 17,
>>> + CDNS_PCIE_LTSSM_CONFIG_LW_START_RC_1 = 18,
>>> + CDNS_PCIE_LTSSM_CONFIG_LW_START_RC_2 = 19,
>>> + CDNS_PCIE_LTSSM_CONFIG_LW_ACC_RC = 20,
>>> + CDNS_PCIE_LTSSM_CONFIG_LANENUM_WAIT_RC = 21,
>>> + CDNS_PCIE_LTSSM_CONFIG_LANENUM_WAIT_RC_1 = 22,
>>> + CDNS_PCIE_LTSSM_CONFIG_LANENUM_ACC_RC = 23,
>>> + CDNS_PCIE_LTSSM_CONFIG_LW_START_EP = 24,
>>> + CDNS_PCIE_LTSSM_CONFIG_LW_START_EP_1 = 25,
>>> + CDNS_PCIE_LTSSM_CONFIG_LW_START_EP_2 = 26,
>>> + CDNS_PCIE_LTSSM_CONFIG_LW_ACC_EP = 27,
>>> + CDNS_PCIE_LTSSM_CONFIG_LANENUM_WAIT_EP = 28,
>>> + CDNS_PCIE_LTSSM_CONFIG_LANENUM_WAIT_EP_1 = 29,
>>> + CDNS_PCIE_LTSSM_CONFIG_LANENUM_ACC_EP = 30,
>>> + CDNS_PCIE_LTSSM_CONFIG_LANENUM_ACC_EP_1 = 31,
>>> + CDNS_PCIE_LTSSM_DUMMY_STATE_1 = 32,
>>> + CDNS_PCIE_LTSSM_CONFIG_COMPLETE = 33,
>>> + CDNS_PCIE_LTSSM_CONFIG_COMPLETE_1 = 34,
>>> + CDNS_PCIE_LTSSM_CONFIG_COMPLETE_2 = 35,
>>> + CDNS_PCIE_LTSSM_CONFIG_IDLE = 36,
>>> + CDNS_PCIE_LTSSM_CONFIG_IDLE_1 = 37,
>>> + CDNS_PCIE_LTSSM_DUMMY_STATE_2 = 38,
>>> + CDNS_PCIE_LTSSM_DUMMY_STATE_3 = 39,
>>> + CDNS_PCIE_LTSSM_DUMMY_STATE_4 = 40,
>>> + CDNS_PCIE_LTSSM_L0_STATE = 41,
>>> + CDNS_PCIE_LTSSM_RECOVERY_RCVR_LOCK = 42,
>>> + CDNS_PCIE_LTSSM_RECOVERY_RCVR_LOCK_1 = 43,
>>> + CDNS_PCIE_LTSSM_RECOVERY_RCVR_CFG = 44,
>>> + CDNS_PCIE_LTSSM_RECOVERY_RCVR_CFG_1 = 45,
>>> + CDNS_PCIE_LTSSM_RECOVERY_IDLE = 46,
>>> + CDNS_PCIE_LTSSM_RECOVERY_IDLE_1 = 47,
>>> + CDNS_PCIE_LTSSM_DISABLE_LINK = 48,
>>> + CDNS_PCIE_LTSSM_DISABLE_LINK_1 = 49,
>>> + CDNS_PCIE_LTSSM_DISABLE_LINK_2 = 50,
>>> + CDNS_PCIE_LTSSM_DISABLE_LINK_3 = 51,
>>> + CDNS_PCIE_LTSSM_DISABLE_LINK_4 = 52,
>>> + CDNS_PCIE_LTSSM_DISABLE_LINK_5 = 53,
>>> + CDNS_PCIE_LTSSM_DISABLE_LINK_6 = 54,
>>> + CDNS_PCIE_LTSSM_DISABLE_LINK_7 = 55,
>>> + CDNS_PCIE_LTSSM_HOT_RESET = 56,
>>> + CDNS_PCIE_LTSSM_HOT_RESET_1 = 57,
>>> + CDNS_PCIE_LTSSM_HOT_RESET_2 = 58,
>>> + CDNS_PCIE_LTSSM_HOT_RESET_3 = 59,
>>> + CDNS_PCIE_LTSSM_L0S_ENTRY = 60,
>>> + CDNS_PCIE_LTSSM_L0S_1 = 61,
>>> + CDNS_PCIE_LTSSM_L0S_2 = 62,
>>> + CDNS_PCIE_LTSSM_L0S_3 = 63,
>>> + CDNS_PCIE_LTSSM_L0S_4 = 64,
>>> + CDNS_PCIE_LTSSM_L0S_5 = 65,
>>> + CDNS_PCIE_LTSSM_WAIT_FOR_LINK_TX = 66,
>>> + CDNS_PCIE_LTSSM_TX_FTS_ENTRY = 67,
>>> + CDNS_PCIE_LTSSM_TX_FTS_1 = 68,
>>> + CDNS_PCIE_LTSSM_TX_FTS_2 = 69,
>>> + CDNS_PCIE_LTSSM_TX_ELEC_IDLE_ST = 70,
>>> + CDNS_PCIE_LTSSM_TX_ELEC_IDLE_1 = 71,
>>> + CDNS_PCIE_LTSSM_TX_ELEC_IDLE_2 = 72,
>>> + CDNS_PCIE_LTSSM_TX_ELEC_IDLE_3 = 73,
>>> + CDNS_PCIE_LTSSM_RECOVERY_SPEED = 74,
>>> + CDNS_PCIE_LTSSM_RECOVERY_SPEED_1 = 75,
>>> + CDNS_PCIE_LTSSM_RECOVERY_SPEED_2 = 76,
>>> + CDNS_PCIE_LTSSM_RECOVERY_SPEED_3 = 77,
>>> + CDNS_PCIE_LTSSM_POLLING_COMPLIANCE_GEN23 = 78,
>>> + CDNS_PCIE_LTSSM_POLLING_COMPLIANCE_GEN23_1 = 79,
>>> + CDNS_PCIE_LTSSM_POLLING_COMPLIANCE_GEN23_2 = 80,
>>> + CDNS_PCIE_LTSSM_POLLING_COMPLIANCE_GEN23_3 = 81,
>>> + CDNS_PCIE_LTSSM_POLLING_COMPLIANCE_GEN23_4 = 82,
>>> + CDNS_PCIE_LTSSM_POLLING_COMPLIANCE_GEN23_5 = 83,
>>> + CDNS_PCIE_LTSSM_POLLING_COMPLIANCE_GEN23_6 = 84,
>>> + CDNS_PCIE_LTSSM_POLLING_COMPLIANCE_GEN23_7 = 85,
>>> + CDNS_PCIE_LTSSM_POLLING_COMPLIANCE_GEN23_8 = 86,
>>> + CDNS_PCIE_LTSSM_LOOPBACK_SLAVE_ENTRY = 87,
>>> + CDNS_PCIE_LTSSM_LOOPBACK_SLAVE_ENTRY_FROM_RECOVERY = 88,
>>> + CDNS_PCIE_LTSSM_LOOPBACK_SLAVE_EXIT_1 = 89,
>>> + CDNS_PCIE_LTSSM_LOOPBACK_SLAVE_EXIT = 90,
>>> + CDNS_PCIE_LTSSM_LOOPBACK_SLAVE_GEN2_1 = 91,
>>> + CDNS_PCIE_LTSSM_LOOPBACK_SLAVE_GEN2_2 = 92,
>>> + CDNS_PCIE_LTSSM_LOOPBACK_SLAVE_GEN2_3 = 93,
>>> + CDNS_PCIE_LTSSM_LOOPBACK_SLAVE_GEN2_4 = 94,
>>> + CDNS_PCIE_LTSSM_LOOPBACK_SLAVE_GEN2_5 = 95,
>>> + CDNS_PCIE_LTSSM_LOOPBACK_SLAVE_ACTIVE = 96,
>>> + CDNS_PCIE_LTSSM_L1_ENTRY = 97,
>>> + CDNS_PCIE_LTSSM_L1_1 = 98,
>>> + CDNS_PCIE_LTSSM_L1_2 = 99,
>>> + CDNS_PCIE_LTSSM_L1_3 = 100,
>>> + CDNS_PCIE_LTSSM_L1_4 = 101,
>>> + CDNS_PCIE_LTSSM_L1_IDLE = 102,
>>> + CDNS_PCIE_LTSSM_L1_EXIT = 103,
>>> + CDNS_PCIE_LTSSM_L2_ENTRY = 104,
>>> + CDNS_PCIE_LTSSM_L2_1 = 105,
>>> + CDNS_PCIE_LTSSM_L2_2 = 106,
>>> + CDNS_PCIE_LTSSM_L2_3 = 107,
>>> + CDNS_PCIE_LTSSM_L2_4 = 108,
>>> + CDNS_PCIE_LTSSM_L2_5 = 109,
>>> + CDNS_PCIE_LTSSM_L2_IDLE = 110,
>>> + CDNS_PCIE_LTSSM_LOOPBACK_MASTER_ENTRY = 111,
>>> + CDNS_PCIE_LTSSM_LOOPBACK_MASTER_ENTRY_1 = 112,
>>> + CDNS_PCIE_LTSSM_LOOPBACK_MASTER_ENTRY_2 = 113,
>>> + CDNS_PCIE_LTSSM_LOOPBACK_MASTER_ENTRY_3 = 114,
>>> + CDNS_PCIE_LTSSM_LOOPBACK_MASTER_ENTRY_4 = 115,
>>> + CDNS_PCIE_LTSSM_LOOPBACK_MASTER_ENTRY_5 = 116,
>>> + CDNS_PCIE_LTSSM_LOOPBACK_MASTER_ENTRY_FROM_RECOVERY = 117,
>>> + CDNS_PCIE_LTSSM_LOOPBACK_MASTER_ACTIVE = 118,
>>> + CDNS_PCIE_LTSSM_LOOPBACK_MASTER_EXIT = 119,
>>> + CDNS_PCIE_LTSSM_LOOPBACK_MASTER_EXIT_1 = 120,
>>> + CDNS_PCIE_LTSSM_LOOPBACK_MASTER_EXIT_2 = 121,
>>> + CDNS_PCIE_LTSSM_RECOVERY_EQUALIZATION_PHASE0 = 122,
>>> + CDNS_PCIE_LTSSM_RECOVERY_EQUALIZATION_PHASE1 = 123,
>>> + CDNS_PCIE_LTSSM_RECOVERY_EQUALIZATION_PHASE2_1 = 124,
>>> + CDNS_PCIE_LTSSM_RECOVERY_EQUALIZATION_PHASE2_2 = 125,
>>> + CDNS_PCIE_LTSSM_RECOVERY_EQUALIZATION_PHASE3_1 = 126,
>>> + CDNS_PCIE_LTSSM_RECOVERY_EQUALIZATION_PHASE3_2 = 127,
>>> +};
>>
>> Hi Hans,
>>
>> The LTSSM state encoding in your patches do not align with the state
>> encodings for LGA IP. TI SoCs have LGA IP of Cadence PCIe, and when I
>> applied your patches, the LTSSM value in the debugfs for the PCIe
>> subsystem (which have an EP connected to it) came out to be 0x10, which
>> points to the state "PCIE_L0". However, the debugfs prints the state as
>> "POLLING_CONFIG_2 (0x10)", which seems to be incorrect.
>>
>> The LTSSM state encodings for TI SoCs using Cadence PCIe IP is
>> provided in the J7200 TRM section 12.2.3.4.14 at:
>> https://www.ti.com/lit/pdf/spruiu1
>
> Hi Aksh,
>
> Thank you for the information you provided. Could you please tell me how
> to read this register? Then I will incorporate it into the next version.
The code to read the LTSSM state for LGA IPs in your patch:
```
reg = cdns_pcie_readl(pci, CDNS_PCIE_LM_BASE);
ltssm = FIELD_GET(CDNS_PCIE_LGA_LTSSM_STATUS_MASK, reg);
```
correctly reads the LTSSM state for TI SoCs which uses LGA IP.
>
> Best regards,
> Hans
>
>>
>> Regards,
>> Aksh Garg
>>
>>
>>> +
>>> struct cdns_pcie_ops {
>>
>
next prev parent reply other threads:[~2026-05-13 8:25 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-05-08 3:40 [PATCH v4 0/2] PCI: cadence: Add LTSSM debugfs Hans Zhang
2026-05-08 3:41 ` [PATCH v4 1/2] PCI: cadence: Add HPA architecture flag Hans Zhang
2026-05-08 3:41 ` [PATCH v4 2/2] PCI: cadence: Add debugfs property to provide LTSSM status of the PCIe link Hans Zhang
2026-05-08 4:19 ` sashiko-bot
2026-05-08 4:31 ` Hans Zhang
2026-05-13 5:23 ` Aksh Garg
2026-05-13 6:11 ` Manikandan Karunakaran Pillai
2026-05-13 6:39 ` Hans Zhang
2026-05-13 7:08 ` Manikandan Karunakaran Pillai
2026-05-13 8:34 ` Aksh Garg
2026-05-13 8:55 ` Hans Zhang
2026-05-13 11:30 ` Aksh Garg
2026-05-13 12:04 ` Hans Zhang
2026-05-14 1:39 ` Manikandan Karunakaran Pillai
2026-05-14 1:46 ` Hans Zhang
2026-05-14 4:25 ` Manikandan Karunakaran Pillai
2026-05-13 6:37 ` Hans Zhang
2026-05-13 8:25 ` Aksh Garg [this message]
2026-05-13 8:29 ` Hans Zhang
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