From: Hans Zhang <18255117159@163.com>
To: Aksh Garg <a-garg7@ti.com>,
Manikandan Karunakaran Pillai <mpillai@cadence.com>,
"bhelgaas@google.com" <bhelgaas@google.com>,
"lpieralisi@kernel.org" <lpieralisi@kernel.org>,
"kwilczynski@kernel.org" <kwilczynski@kernel.org>,
"mani@kernel.org" <mani@kernel.org>,
"hans.zhang@cixtech.com" <hans.zhang@cixtech.com>
Cc: "robh@kernel.org" <robh@kernel.org>,
"linux-pci@vger.kernel.org" <linux-pci@vger.kernel.org>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
Siddharth Vadapalli <s-vadapalli@ti.com>
Subject: Re: [PATCH v4 2/2] PCI: cadence: Add debugfs property to provide LTSSM status of the PCIe link
Date: Wed, 13 May 2026 16:55:37 +0800 [thread overview]
Message-ID: <c0bd820d-9716-4109-9d5e-7e72e0716cf1@163.com> (raw)
In-Reply-To: <f8ada2e3-15c2-43b1-b013-2f3fd263f25f@ti.com>
On 5/13/26 16:34, Aksh Garg wrote:
>>>
>>
>> The above LTSSM states are internal LTSSM encoding states and may not
>> be available for software to use.
>> The LTSSM states in the document pointed by Aksh (TI Soc) are the
>> states available in all cadence controllers.
>
> Is this true for HPA IPs as well? The test performed by Hans:
> root@orangepi6plus:~# cat /sys/kernel/debug/cdns_pcie_a0*/ltss*
> L0_STATE (0x29)
> L0_STATE (0x29)
> L0_STATE (0x29)
>
> This implies that the L0_STATE LTSSM state is mapped to 0x29 (41) there,
> which according to your response is internal LTSSM encoding, and hence
> the register read should have resulted in 0x10 instead of 0x29.
>
Hi Aksh,
For HPA, my view is similar to that of DWC - it requires a common
internal LTSSM state. For each of its own Root Port drivers, a callback
can be used to implement the reading of LTSSM. This part can be referred
to as the implementation of the function in DWC.
static inline enum dw_pcie_ltssm dw_pcie_get_ltssm(struct dw_pcie *pci)
{
u32 val;
if (pci->ops && pci->ops->get_ltssm)
return pci->ops->get_ltssm(pci);
val = dw_pcie_readl_dbi(pci, PCIE_PORT_DEBUG0);
return (enum dw_pcie_ltssm)FIELD_GET(PORT_LOGIC_LTSSM_STATE_MASK, val);
}
static int ltssm_status_show(struct seq_file *s, void *v)
{
struct dw_pcie *pci = s->private;
enum dw_pcie_ltssm val;
val = dw_pcie_get_ltssm(pci);
seq_printf(s, "%s (0x%02x)\n", dw_pcie_ltssm_status_string(val), val);
return 0;
}
For example, it can be modified as follows. Of course, the function name
will start with "cdns".
For LGA IP, currently we will allow each Root Port driver to implement
the corresponding ops::get_ltssm() by itself.
static int ltssm_status_show(struct seq_file *s, void *v)
{
struct dw_pcie *pci = s->private;
enum dw_pcie_ltssm val;
if (pci->ops && pci->ops->get_ltssm)
val = pci->ops->get_ltssm(pci);
else
val = dw_pcie_get_ltssm(pci);
seq_printf(s, "%s (0x%02x)\n", dw_pcie_ltssm_status_string(val), val);
return 0;
}
Best regards,
Hans
next prev parent reply other threads:[~2026-05-13 8:56 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-05-08 3:40 [PATCH v4 0/2] PCI: cadence: Add LTSSM debugfs Hans Zhang
2026-05-08 3:41 ` [PATCH v4 1/2] PCI: cadence: Add HPA architecture flag Hans Zhang
2026-05-08 3:41 ` [PATCH v4 2/2] PCI: cadence: Add debugfs property to provide LTSSM status of the PCIe link Hans Zhang
2026-05-08 4:19 ` sashiko-bot
2026-05-08 4:31 ` Hans Zhang
2026-05-13 5:23 ` Aksh Garg
2026-05-13 6:11 ` Manikandan Karunakaran Pillai
2026-05-13 6:39 ` Hans Zhang
2026-05-13 7:08 ` Manikandan Karunakaran Pillai
2026-05-13 8:34 ` Aksh Garg
2026-05-13 8:55 ` Hans Zhang [this message]
2026-05-13 11:30 ` Aksh Garg
2026-05-13 12:04 ` Hans Zhang
2026-05-14 1:39 ` Manikandan Karunakaran Pillai
2026-05-14 1:46 ` Hans Zhang
2026-05-14 4:25 ` Manikandan Karunakaran Pillai
2026-05-13 6:37 ` Hans Zhang
2026-05-13 8:25 ` Aksh Garg
2026-05-13 8:29 ` Hans Zhang
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