From: Bjorn Helgaas <bhelgaas@google.com>
To: linux-pci@vger.kernel.org
Cc: Lee Jones <lee.jones@linaro.org>, Samuel Ortiz <sameo@linux.intel.com>
Subject: [PATCH 5/5] PCI: Add offsets of PCIe capability registers
Date: Tue, 27 Aug 2013 13:00:56 -0600 [thread overview]
Message-ID: <20130827190056.16595.97322.stgit@bhelgaas-glaptop> (raw)
In-Reply-To: <20130827185731.16595.52864.stgit@bhelgaas-glaptop>
These offsets are not used, and in some cases are completely reserved
even in the spec, but I'm adding them for completeness just to match
the diagrams in the spec, e.g., PCIe spec r3.0, sec 7.8.
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
---
include/uapi/linux/pci_regs.h | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h
index 28c83ec..baa7852 100644
--- a/include/uapi/linux/pci_regs.h
+++ b/include/uapi/linux/pci_regs.h
@@ -565,15 +565,18 @@
#define PCI_EXP_DEVCTL2_OBFF_MSGA_EN 0x2000 /* Enable OBFF Message type A */
#define PCI_EXP_DEVCTL2_OBFF_MSGB_EN 0x4000 /* Enable OBFF Message type B */
#define PCI_EXP_DEVCTL2_OBFF_WAKE_EN 0x6000 /* OBFF using WAKE# signaling */
+#define PCI_EXP_DEVSTA2 42 /* Device Status 2 */
#define PCI_CAP_EXP_ENDPOINT_SIZEOF_V2 44 /* v2 endpoints end here */
-#define PCI_EXP_LNKCAP2 44 /* Link Capability 2 */
+#define PCI_EXP_LNKCAP2 44 /* Link Capabilities 2 */
#define PCI_EXP_LNKCAP2_SLS_2_5GB 0x00000002 /* Supported Speed 2.5GT/s */
#define PCI_EXP_LNKCAP2_SLS_5_0GB 0x00000004 /* Supported Speed 5.0GT/s */
#define PCI_EXP_LNKCAP2_SLS_8_0GB 0x00000008 /* Supported Speed 8.0GT/s */
#define PCI_EXP_LNKCAP2_CROSSLINK 0x00000100 /* Crosslink supported */
#define PCI_EXP_LNKCTL2 48 /* Link Control 2 */
#define PCI_EXP_LNKSTA2 50 /* Link Status 2 */
+#define PCI_EXP_SLTCAP2 52 /* Slot Capabilities 2 */
#define PCI_EXP_SLTCTL2 56 /* Slot Control 2 */
+#define PCI_EXP_SLTSTA2 58 /* Slot Status 2 */
/* Extended Capabilities (PCI-X 2.0 and Express) */
#define PCI_EXT_CAP_ID(header) (header & 0x0000ffff)
next prev parent reply other threads:[~2013-08-27 19:00 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-08-27 19:00 [PATCH 0/5] PCIe capability #define tidyup Bjorn Helgaas
2013-08-27 19:00 ` [PATCH 1/5] PCI: Rename PCIe capability definitions to follow convention Bjorn Helgaas
2013-08-27 22:05 ` Samuel Ortiz
2013-08-27 19:00 ` [PATCH 2/5] PCI: Clarify PCI_EXP_TYPE_PCI_BRIDGE comment Bjorn Helgaas
2013-08-27 19:00 ` [PATCH 3/5] PCI: Remove obsolete comment reference to pci_pcie_cap2() Bjorn Helgaas
2013-08-27 19:00 ` [PATCH 4/5] PCI: Tidy bitmasks and spacing of PCIe capability definitions Bjorn Helgaas
2013-08-27 19:00 ` Bjorn Helgaas [this message]
2013-08-29 3:15 ` [PATCH 0/5] PCIe capability #define tidyup Bjorn Helgaas
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