* [PATCH 1/6] PCI: keystone: Name private struct pointer "keystone" consistently
@ 2016-10-07 16:40 Bjorn Helgaas
2016-10-07 16:40 ` [PATCH 2/6] PCI: keystone: Pass keystone_pcie, not address, to IRQ functions Bjorn Helgaas
` (5 more replies)
0 siblings, 6 replies; 9+ messages in thread
From: Bjorn Helgaas @ 2016-10-07 16:40 UTC (permalink / raw)
To: Murali Karicheri; +Cc: linux-pci
Use a device-specific name, "keystone", for struct keystone_pcie pointers
to hint that this is device-specific information. No functional change
intended.
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
---
drivers/pci/host/pci-keystone-dw.c | 122 ++++++++++++++++++-----------------
drivers/pci/host/pci-keystone.c | 125 ++++++++++++++++++------------------
drivers/pci/host/pci-keystone.h | 12 ++-
3 files changed, 129 insertions(+), 130 deletions(-)
diff --git a/drivers/pci/host/pci-keystone-dw.c b/drivers/pci/host/pci-keystone-dw.c
index 4151509..d09e3c6 100644
--- a/drivers/pci/host/pci-keystone-dw.c
+++ b/drivers/pci/host/pci-keystone-dw.c
@@ -83,18 +83,18 @@ static inline void update_reg_offset_bit_pos(u32 offset, u32 *reg_offset,
phys_addr_t ks_dw_pcie_get_msi_addr(struct pcie_port *pp)
{
- struct keystone_pcie *ks_pcie = to_keystone_pcie(pp);
+ struct keystone_pcie *keystone = to_keystone_pcie(pp);
- return ks_pcie->app.start + MSI_IRQ;
+ return keystone->app.start + MSI_IRQ;
}
-void ks_dw_pcie_handle_msi_irq(struct keystone_pcie *ks_pcie, int offset)
+void ks_dw_pcie_handle_msi_irq(struct keystone_pcie *keystone, int offset)
{
- struct pcie_port *pp = &ks_pcie->pp;
+ struct pcie_port *pp = &keystone->pp;
u32 pending, vector;
int src, virq;
- pending = readl(ks_pcie->va_app_base + MSI0_IRQ_STATUS + (offset << 4));
+ pending = readl(keystone->va_app_base + MSI0_IRQ_STATUS + (offset << 4));
/*
* MSI0 status bit 0-3 shows vectors 0, 8, 16, 24, MSI1 status bit
@@ -114,51 +114,51 @@ void ks_dw_pcie_handle_msi_irq(struct keystone_pcie *ks_pcie, int offset)
static void ks_dw_pcie_msi_irq_ack(struct irq_data *d)
{
u32 offset, reg_offset, bit_pos;
- struct keystone_pcie *ks_pcie;
+ struct keystone_pcie *keystone;
struct msi_desc *msi;
struct pcie_port *pp;
msi = irq_data_get_msi_desc(d);
pp = (struct pcie_port *) msi_desc_to_pci_sysdata(msi);
- ks_pcie = to_keystone_pcie(pp);
+ keystone = to_keystone_pcie(pp);
offset = d->irq - irq_linear_revmap(pp->irq_domain, 0);
update_reg_offset_bit_pos(offset, ®_offset, &bit_pos);
writel(BIT(bit_pos),
- ks_pcie->va_app_base + MSI0_IRQ_STATUS + (reg_offset << 4));
- writel(reg_offset + MSI_IRQ_OFFSET, ks_pcie->va_app_base + IRQ_EOI);
+ keystone->va_app_base + MSI0_IRQ_STATUS + (reg_offset << 4));
+ writel(reg_offset + MSI_IRQ_OFFSET, keystone->va_app_base + IRQ_EOI);
}
void ks_dw_pcie_msi_set_irq(struct pcie_port *pp, int irq)
{
u32 reg_offset, bit_pos;
- struct keystone_pcie *ks_pcie = to_keystone_pcie(pp);
+ struct keystone_pcie *keystone = to_keystone_pcie(pp);
update_reg_offset_bit_pos(irq, ®_offset, &bit_pos);
writel(BIT(bit_pos),
- ks_pcie->va_app_base + MSI0_IRQ_ENABLE_SET + (reg_offset << 4));
+ keystone->va_app_base + MSI0_IRQ_ENABLE_SET + (reg_offset << 4));
}
void ks_dw_pcie_msi_clear_irq(struct pcie_port *pp, int irq)
{
u32 reg_offset, bit_pos;
- struct keystone_pcie *ks_pcie = to_keystone_pcie(pp);
+ struct keystone_pcie *keystone = to_keystone_pcie(pp);
update_reg_offset_bit_pos(irq, ®_offset, &bit_pos);
writel(BIT(bit_pos),
- ks_pcie->va_app_base + MSI0_IRQ_ENABLE_CLR + (reg_offset << 4));
+ keystone->va_app_base + MSI0_IRQ_ENABLE_CLR + (reg_offset << 4));
}
static void ks_dw_pcie_msi_irq_mask(struct irq_data *d)
{
- struct keystone_pcie *ks_pcie;
+ struct keystone_pcie *keystone;
struct msi_desc *msi;
struct pcie_port *pp;
u32 offset;
msi = irq_data_get_msi_desc(d);
pp = (struct pcie_port *) msi_desc_to_pci_sysdata(msi);
- ks_pcie = to_keystone_pcie(pp);
+ keystone = to_keystone_pcie(pp);
offset = d->irq - irq_linear_revmap(pp->irq_domain, 0);
/* Mask the end point if PVM implemented */
@@ -172,14 +172,14 @@ static void ks_dw_pcie_msi_irq_mask(struct irq_data *d)
static void ks_dw_pcie_msi_irq_unmask(struct irq_data *d)
{
- struct keystone_pcie *ks_pcie;
+ struct keystone_pcie *keystone;
struct msi_desc *msi;
struct pcie_port *pp;
u32 offset;
msi = irq_data_get_msi_desc(d);
pp = (struct pcie_port *) msi_desc_to_pci_sysdata(msi);
- ks_pcie = to_keystone_pcie(pp);
+ keystone = to_keystone_pcie(pp);
offset = d->irq - irq_linear_revmap(pp->irq_domain, 0);
/* Mask the end point if PVM implemented */
@@ -214,10 +214,10 @@ static const struct irq_domain_ops ks_dw_pcie_msi_domain_ops = {
int ks_dw_pcie_msi_host_init(struct pcie_port *pp, struct msi_controller *chip)
{
- struct keystone_pcie *ks_pcie = to_keystone_pcie(pp);
+ struct keystone_pcie *keystone = to_keystone_pcie(pp);
int i;
- pp->irq_domain = irq_domain_add_linear(ks_pcie->msi_intc_np,
+ pp->irq_domain = irq_domain_add_linear(keystone->msi_intc_np,
MAX_MSI_IRQS,
&ks_dw_pcie_msi_domain_ops,
chip);
@@ -232,31 +232,31 @@ int ks_dw_pcie_msi_host_init(struct pcie_port *pp, struct msi_controller *chip)
return 0;
}
-void ks_dw_pcie_enable_legacy_irqs(struct keystone_pcie *ks_pcie)
+void ks_dw_pcie_enable_legacy_irqs(struct keystone_pcie *keystone)
{
int i;
for (i = 0; i < MAX_LEGACY_IRQS; i++)
- writel(0x1, ks_pcie->va_app_base + IRQ_ENABLE_SET + (i << 4));
+ writel(0x1, keystone->va_app_base + IRQ_ENABLE_SET + (i << 4));
}
-void ks_dw_pcie_handle_legacy_irq(struct keystone_pcie *ks_pcie, int offset)
+void ks_dw_pcie_handle_legacy_irq(struct keystone_pcie *keystone, int offset)
{
- struct pcie_port *pp = &ks_pcie->pp;
+ struct pcie_port *pp = &keystone->pp;
u32 pending;
int virq;
- pending = readl(ks_pcie->va_app_base + IRQ_STATUS + (offset << 4));
+ pending = readl(keystone->va_app_base + IRQ_STATUS + (offset << 4));
if (BIT(0) & pending) {
- virq = irq_linear_revmap(ks_pcie->legacy_irq_domain, offset);
+ virq = irq_linear_revmap(keystone->legacy_irq_domain, offset);
dev_dbg(pp->dev, ": irq: irq_offset %d, virq %d\n", offset,
virq);
generic_handle_irq(virq);
}
/* EOI the INTx interrupt */
- writel(offset, ks_pcie->va_app_base + IRQ_EOI);
+ writel(offset, keystone->va_app_base + IRQ_EOI);
}
void ks_dw_pcie_enable_error_irq(void __iomem *reg_base)
@@ -352,39 +352,39 @@ static void ks_dw_pcie_clear_dbi_mode(void __iomem *reg_virt)
} while (val & DBI_CS2_EN_VAL);
}
-void ks_dw_pcie_setup_rc_app_regs(struct keystone_pcie *ks_pcie)
+void ks_dw_pcie_setup_rc_app_regs(struct keystone_pcie *keystone)
{
- struct pcie_port *pp = &ks_pcie->pp;
+ struct pcie_port *pp = &keystone->pp;
u32 start = pp->mem->start, end = pp->mem->end;
int i, tr_size;
/* Disable BARs for inbound access */
- ks_dw_pcie_set_dbi_mode(ks_pcie->va_app_base);
+ ks_dw_pcie_set_dbi_mode(keystone->va_app_base);
writel(0, pp->dbi_base + PCI_BASE_ADDRESS_0);
writel(0, pp->dbi_base + PCI_BASE_ADDRESS_1);
- ks_dw_pcie_clear_dbi_mode(ks_pcie->va_app_base);
+ ks_dw_pcie_clear_dbi_mode(keystone->va_app_base);
/* Set outbound translation size per window division */
- writel(CFG_PCIM_WIN_SZ_IDX & 0x7, ks_pcie->va_app_base + OB_SIZE);
+ writel(CFG_PCIM_WIN_SZ_IDX & 0x7, keystone->va_app_base + OB_SIZE);
tr_size = (1 << (CFG_PCIM_WIN_SZ_IDX & 0x7)) * SZ_1M;
/* Using Direct 1:1 mapping of RC <-> PCI memory space */
for (i = 0; (i < CFG_PCIM_WIN_CNT) && (start < end); i++) {
- writel(start | 1, ks_pcie->va_app_base + OB_OFFSET_INDEX(i));
- writel(0, ks_pcie->va_app_base + OB_OFFSET_HI(i));
+ writel(start | 1, keystone->va_app_base + OB_OFFSET_INDEX(i));
+ writel(0, keystone->va_app_base + OB_OFFSET_HI(i));
start += tr_size;
}
/* Enable OB translation */
- writel(OB_XLAT_EN_VAL | readl(ks_pcie->va_app_base + CMD_STATUS),
- ks_pcie->va_app_base + CMD_STATUS);
+ writel(OB_XLAT_EN_VAL | readl(keystone->va_app_base + CMD_STATUS),
+ keystone->va_app_base + CMD_STATUS);
}
/**
* ks_pcie_cfg_setup() - Set up configuration space address for a device
*
- * @ks_pcie: ptr to keystone_pcie structure
+ * @keystone: ptr to keystone_pcie structure
* @bus: Bus number the device is residing on
* @devfn: device, function number info
*
@@ -398,11 +398,11 @@ void ks_dw_pcie_setup_rc_app_regs(struct keystone_pcie *ks_pcie)
* we will do TYPE 0 access as it will be on our secondary bus (logical).
* CFG_SETUP is needed only for remote configuration access.
*/
-static void __iomem *ks_pcie_cfg_setup(struct keystone_pcie *ks_pcie, u8 bus,
+static void __iomem *ks_pcie_cfg_setup(struct keystone_pcie *keystone, u8 bus,
unsigned int devfn)
{
u8 device = PCI_SLOT(devfn), function = PCI_FUNC(devfn);
- struct pcie_port *pp = &ks_pcie->pp;
+ struct pcie_port *pp = &keystone->pp;
u32 regval;
if (bus == 0)
@@ -418,18 +418,18 @@ static void __iomem *ks_pcie_cfg_setup(struct keystone_pcie *ks_pcie, u8 bus,
if (bus != 1)
regval |= BIT(24);
- writel(regval, ks_pcie->va_app_base + CFG_SETUP);
+ writel(regval, keystone->va_app_base + CFG_SETUP);
return pp->va_cfg0_base;
}
int ks_dw_pcie_rd_other_conf(struct pcie_port *pp, struct pci_bus *bus,
unsigned int devfn, int where, int size, u32 *val)
{
- struct keystone_pcie *ks_pcie = to_keystone_pcie(pp);
+ struct keystone_pcie *keystone = to_keystone_pcie(pp);
u8 bus_num = bus->number;
void __iomem *addr;
- addr = ks_pcie_cfg_setup(ks_pcie, bus_num, devfn);
+ addr = ks_pcie_cfg_setup(keystone, bus_num, devfn);
return dw_pcie_cfg_read(addr + where, size, val);
}
@@ -437,11 +437,11 @@ int ks_dw_pcie_rd_other_conf(struct pcie_port *pp, struct pci_bus *bus,
int ks_dw_pcie_wr_other_conf(struct pcie_port *pp, struct pci_bus *bus,
unsigned int devfn, int where, int size, u32 val)
{
- struct keystone_pcie *ks_pcie = to_keystone_pcie(pp);
+ struct keystone_pcie *keystone = to_keystone_pcie(pp);
u8 bus_num = bus->number;
void __iomem *addr;
- addr = ks_pcie_cfg_setup(ks_pcie, bus_num, devfn);
+ addr = ks_pcie_cfg_setup(keystone, bus_num, devfn);
return dw_pcie_cfg_write(addr + where, size, val);
}
@@ -453,22 +453,22 @@ int ks_dw_pcie_wr_other_conf(struct pcie_port *pp, struct pci_bus *bus,
*/
void ks_dw_pcie_v3_65_scan_bus(struct pcie_port *pp)
{
- struct keystone_pcie *ks_pcie = to_keystone_pcie(pp);
+ struct keystone_pcie *keystone = to_keystone_pcie(pp);
/* Configure and set up BAR0 */
- ks_dw_pcie_set_dbi_mode(ks_pcie->va_app_base);
+ ks_dw_pcie_set_dbi_mode(keystone->va_app_base);
/* Enable BAR0 */
writel(1, pp->dbi_base + PCI_BASE_ADDRESS_0);
writel(SZ_4K - 1, pp->dbi_base + PCI_BASE_ADDRESS_0);
- ks_dw_pcie_clear_dbi_mode(ks_pcie->va_app_base);
+ ks_dw_pcie_clear_dbi_mode(keystone->va_app_base);
/*
* For BAR0, just setting bus address for inbound writes (MSI) should
* be sufficient. Use physical address to avoid any conflicts.
*/
- writel(ks_pcie->app.start, pp->dbi_base + PCI_BASE_ADDRESS_0);
+ writel(keystone->app.start, pp->dbi_base + PCI_BASE_ADDRESS_0);
}
/**
@@ -481,18 +481,18 @@ int ks_dw_pcie_link_up(struct pcie_port *pp)
return (val & LTSSM_STATE_MASK) == LTSSM_STATE_L0;
}
-void ks_dw_pcie_initiate_link_train(struct keystone_pcie *ks_pcie)
+void ks_dw_pcie_initiate_link_train(struct keystone_pcie *keystone)
{
u32 val;
/* Disable Link training */
- val = readl(ks_pcie->va_app_base + CMD_STATUS);
+ val = readl(keystone->va_app_base + CMD_STATUS);
val &= ~LTSSM_EN_VAL;
- writel(LTSSM_EN_VAL | val, ks_pcie->va_app_base + CMD_STATUS);
+ writel(LTSSM_EN_VAL | val, keystone->va_app_base + CMD_STATUS);
/* Initiate Link Training */
- val = readl(ks_pcie->va_app_base + CMD_STATUS);
- writel(LTSSM_EN_VAL | val, ks_pcie->va_app_base + CMD_STATUS);
+ val = readl(keystone->va_app_base + CMD_STATUS);
+ writel(LTSSM_EN_VAL | val, keystone->va_app_base + CMD_STATUS);
}
/**
@@ -502,10 +502,10 @@ void ks_dw_pcie_initiate_link_train(struct keystone_pcie *ks_pcie)
* and call dw_pcie_v3_65_host_init() API to initialize the Keystone
* PCI host controller.
*/
-int __init ks_dw_pcie_host_init(struct keystone_pcie *ks_pcie,
+int __init ks_dw_pcie_host_init(struct keystone_pcie *keystone,
struct device_node *msi_intc_np)
{
- struct pcie_port *pp = &ks_pcie->pp;
+ struct pcie_port *pp = &keystone->pp;
struct platform_device *pdev = to_platform_device(pp->dev);
struct resource *res;
@@ -524,19 +524,19 @@ int __init ks_dw_pcie_host_init(struct keystone_pcie *ks_pcie,
/* Index 1 is the application reg. space address */
res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
- ks_pcie->va_app_base = devm_ioremap_resource(pp->dev, res);
- if (IS_ERR(ks_pcie->va_app_base))
- return PTR_ERR(ks_pcie->va_app_base);
+ keystone->va_app_base = devm_ioremap_resource(pp->dev, res);
+ if (IS_ERR(keystone->va_app_base))
+ return PTR_ERR(keystone->va_app_base);
- ks_pcie->app = *res;
+ keystone->app = *res;
/* Create legacy IRQ domain */
- ks_pcie->legacy_irq_domain =
- irq_domain_add_linear(ks_pcie->legacy_intc_np,
+ keystone->legacy_irq_domain =
+ irq_domain_add_linear(keystone->legacy_intc_np,
MAX_LEGACY_IRQS,
&ks_dw_pcie_legacy_irq_domain_ops,
NULL);
- if (!ks_pcie->legacy_irq_domain) {
+ if (!keystone->legacy_irq_domain) {
dev_err(pp->dev, "Failed to add irq domain for legacy irqs\n");
return -EINVAL;
}
diff --git a/drivers/pci/host/pci-keystone.c b/drivers/pci/host/pci-keystone.c
index 82b461b..55b2be7 100644
--- a/drivers/pci/host/pci-keystone.c
+++ b/drivers/pci/host/pci-keystone.c
@@ -86,9 +86,9 @@ static void quirk_limit_mrrs(struct pci_dev *dev)
}
DECLARE_PCI_FIXUP_ENABLE(PCI_ANY_ID, PCI_ANY_ID, quirk_limit_mrrs);
-static int ks_pcie_establish_link(struct keystone_pcie *ks_pcie)
+static int ks_pcie_establish_link(struct keystone_pcie *keystone)
{
- struct pcie_port *pp = &ks_pcie->pp;
+ struct pcie_port *pp = &keystone->pp;
unsigned int retries;
dw_pcie_setup_rc(pp);
@@ -100,7 +100,7 @@ static int ks_pcie_establish_link(struct keystone_pcie *ks_pcie)
/* check if the link is up or not */
for (retries = 0; retries < 5; retries++) {
- ks_dw_pcie_initiate_link_train(ks_pcie);
+ ks_dw_pcie_initiate_link_train(keystone);
if (!dw_pcie_wait_for_link(pp))
return 0;
}
@@ -112,9 +112,9 @@ static int ks_pcie_establish_link(struct keystone_pcie *ks_pcie)
static void ks_pcie_msi_irq_handler(struct irq_desc *desc)
{
unsigned int irq = irq_desc_get_irq(desc);
- struct keystone_pcie *ks_pcie = irq_desc_get_handler_data(desc);
- u32 offset = irq - ks_pcie->msi_host_irqs[0];
- struct pcie_port *pp = &ks_pcie->pp;
+ struct keystone_pcie *keystone = irq_desc_get_handler_data(desc);
+ u32 offset = irq - keystone->msi_host_irqs[0];
+ struct pcie_port *pp = &keystone->pp;
struct irq_chip *chip = irq_desc_get_chip(desc);
dev_dbg(pp->dev, "%s, irq %d\n", __func__, irq);
@@ -125,7 +125,7 @@ static void ks_pcie_msi_irq_handler(struct irq_desc *desc)
* ack operation.
*/
chained_irq_enter(chip, desc);
- ks_dw_pcie_handle_msi_irq(ks_pcie, offset);
+ ks_dw_pcie_handle_msi_irq(keystone, offset);
chained_irq_exit(chip, desc);
}
@@ -140,9 +140,9 @@ static void ks_pcie_msi_irq_handler(struct irq_desc *desc)
static void ks_pcie_legacy_irq_handler(struct irq_desc *desc)
{
unsigned int irq = irq_desc_get_irq(desc);
- struct keystone_pcie *ks_pcie = irq_desc_get_handler_data(desc);
- struct pcie_port *pp = &ks_pcie->pp;
- u32 irq_offset = irq - ks_pcie->legacy_host_irqs[0];
+ struct keystone_pcie *keystone = irq_desc_get_handler_data(desc);
+ struct pcie_port *pp = &keystone->pp;
+ u32 irq_offset = irq - keystone->legacy_host_irqs[0];
struct irq_chip *chip = irq_desc_get_chip(desc);
dev_dbg(pp->dev, ": Handling legacy irq %d\n", irq);
@@ -153,28 +153,28 @@ static void ks_pcie_legacy_irq_handler(struct irq_desc *desc)
* ack operation.
*/
chained_irq_enter(chip, desc);
- ks_dw_pcie_handle_legacy_irq(ks_pcie, irq_offset);
+ ks_dw_pcie_handle_legacy_irq(keystone, irq_offset);
chained_irq_exit(chip, desc);
}
-static int ks_pcie_get_irq_controller_info(struct keystone_pcie *ks_pcie,
+static int ks_pcie_get_irq_controller_info(struct keystone_pcie *keystone,
char *controller, int *num_irqs)
{
int temp, max_host_irqs, legacy = 1, *host_irqs;
- struct device *dev = ks_pcie->pp.dev;
+ struct device *dev = keystone->pp.dev;
struct device_node *np_pcie = dev->of_node, **np_temp;
if (!strcmp(controller, "msi-interrupt-controller"))
legacy = 0;
if (legacy) {
- np_temp = &ks_pcie->legacy_intc_np;
+ np_temp = &keystone->legacy_intc_np;
max_host_irqs = MAX_LEGACY_HOST_IRQS;
- host_irqs = &ks_pcie->legacy_host_irqs[0];
+ host_irqs = &keystone->legacy_host_irqs[0];
} else {
- np_temp = &ks_pcie->msi_intc_np;
+ np_temp = &keystone->msi_intc_np;
max_host_irqs = MAX_MSI_HOST_IRQS;
- host_irqs = &ks_pcie->msi_host_irqs[0];
+ host_irqs = &keystone->msi_host_irqs[0];
}
/* interrupt controller is in a child node */
@@ -212,29 +212,29 @@ static int ks_pcie_get_irq_controller_info(struct keystone_pcie *ks_pcie,
return -EINVAL;
}
-static void ks_pcie_setup_interrupts(struct keystone_pcie *ks_pcie)
+static void ks_pcie_setup_interrupts(struct keystone_pcie *keystone)
{
int i;
/* Legacy IRQ */
- for (i = 0; i < ks_pcie->num_legacy_host_irqs; i++) {
- irq_set_chained_handler_and_data(ks_pcie->legacy_host_irqs[i],
+ for (i = 0; i < keystone->num_legacy_host_irqs; i++) {
+ irq_set_chained_handler_and_data(keystone->legacy_host_irqs[i],
ks_pcie_legacy_irq_handler,
- ks_pcie);
+ keystone);
}
- ks_dw_pcie_enable_legacy_irqs(ks_pcie);
+ ks_dw_pcie_enable_legacy_irqs(keystone);
/* MSI IRQ */
if (IS_ENABLED(CONFIG_PCI_MSI)) {
- for (i = 0; i < ks_pcie->num_msi_host_irqs; i++) {
- irq_set_chained_handler_and_data(ks_pcie->msi_host_irqs[i],
+ for (i = 0; i < keystone->num_msi_host_irqs; i++) {
+ irq_set_chained_handler_and_data(keystone->msi_host_irqs[i],
ks_pcie_msi_irq_handler,
- ks_pcie);
+ keystone);
}
}
- if (ks_pcie->error_irq > 0)
- ks_dw_pcie_enable_error_irq(ks_pcie->va_app_base);
+ if (keystone->error_irq > 0)
+ ks_dw_pcie_enable_error_irq(keystone->va_app_base);
}
/*
@@ -259,17 +259,17 @@ static int keystone_pcie_fault(unsigned long addr, unsigned int fsr,
static void __init ks_pcie_host_init(struct pcie_port *pp)
{
- struct keystone_pcie *ks_pcie = to_keystone_pcie(pp);
+ struct keystone_pcie *keystone = to_keystone_pcie(pp);
u32 val;
- ks_pcie_establish_link(ks_pcie);
- ks_dw_pcie_setup_rc_app_regs(ks_pcie);
- ks_pcie_setup_interrupts(ks_pcie);
+ ks_pcie_establish_link(keystone);
+ ks_dw_pcie_setup_rc_app_regs(keystone);
+ ks_pcie_setup_interrupts(keystone);
writew(PCI_IO_RANGE_TYPE_32 | (PCI_IO_RANGE_TYPE_32 << 8),
pp->dbi_base + PCI_IO_BASE);
/* update the Vendor ID */
- writew(ks_pcie->device_id, pp->dbi_base + PCI_DEVICE_ID);
+ writew(keystone->device_id, pp->dbi_base + PCI_DEVICE_ID);
/* update the DEV_STAT_CTRL to publish right mrrs */
val = readl(pp->dbi_base + PCIE_CAP_BASE + PCI_EXP_DEVCTL);
@@ -300,28 +300,28 @@ static struct pcie_host_ops keystone_pcie_host_ops = {
static irqreturn_t pcie_err_irq_handler(int irq, void *priv)
{
- struct keystone_pcie *ks_pcie = priv;
+ struct keystone_pcie *keystone = priv;
- return ks_dw_pcie_handle_error_irq(ks_pcie->pp.dev,
- ks_pcie->va_app_base);
+ return ks_dw_pcie_handle_error_irq(keystone->pp.dev,
+ keystone->va_app_base);
}
-static int __init ks_add_pcie_port(struct keystone_pcie *ks_pcie,
+static int __init ks_add_pcie_port(struct keystone_pcie *keystone,
struct platform_device *pdev)
{
- struct pcie_port *pp = &ks_pcie->pp;
+ struct pcie_port *pp = &keystone->pp;
int ret;
- ret = ks_pcie_get_irq_controller_info(ks_pcie,
+ ret = ks_pcie_get_irq_controller_info(keystone,
"legacy-interrupt-controller",
- &ks_pcie->num_legacy_host_irqs);
+ &keystone->num_legacy_host_irqs);
if (ret)
return ret;
if (IS_ENABLED(CONFIG_PCI_MSI)) {
- ret = ks_pcie_get_irq_controller_info(ks_pcie,
+ ret = ks_pcie_get_irq_controller_info(keystone,
"msi-interrupt-controller",
- &ks_pcie->num_msi_host_irqs);
+ &keystone->num_msi_host_irqs);
if (ret)
return ret;
}
@@ -330,22 +330,22 @@ static int __init ks_add_pcie_port(struct keystone_pcie *ks_pcie,
* Index 0 is the platform interrupt for error interrupt
* from RC. This is optional.
*/
- ks_pcie->error_irq = irq_of_parse_and_map(ks_pcie->np, 0);
- if (ks_pcie->error_irq <= 0)
+ keystone->error_irq = irq_of_parse_and_map(keystone->np, 0);
+ if (keystone->error_irq <= 0)
dev_info(&pdev->dev, "no error IRQ defined\n");
else {
- ret = request_irq(ks_pcie->error_irq, pcie_err_irq_handler,
- IRQF_SHARED, "pcie-error-irq", ks_pcie);
+ ret = request_irq(keystone->error_irq, pcie_err_irq_handler,
+ IRQF_SHARED, "pcie-error-irq", keystone);
if (ret < 0) {
dev_err(&pdev->dev, "failed to request error IRQ %d\n",
- ks_pcie->error_irq);
+ keystone->error_irq);
return ret;
}
}
pp->root_bus_nr = -1;
pp->ops = &keystone_pcie_host_ops;
- ret = ks_dw_pcie_host_init(ks_pcie, ks_pcie->msi_intc_np);
+ ret = ks_dw_pcie_host_init(keystone, keystone->msi_intc_np);
if (ret) {
dev_err(&pdev->dev, "failed to initialize host\n");
return ret;
@@ -364,9 +364,9 @@ static const struct of_device_id ks_pcie_of_match[] = {
static int __exit ks_pcie_remove(struct platform_device *pdev)
{
- struct keystone_pcie *ks_pcie = platform_get_drvdata(pdev);
+ struct keystone_pcie *keystone = platform_get_drvdata(pdev);
- clk_disable_unprepare(ks_pcie->clk);
+ clk_disable_unprepare(keystone->clk);
return 0;
}
@@ -374,19 +374,18 @@ static int __exit ks_pcie_remove(struct platform_device *pdev)
static int __init ks_pcie_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
- struct keystone_pcie *ks_pcie;
+ struct keystone_pcie *keystone;
struct pcie_port *pp;
struct resource *res;
void __iomem *reg_p;
struct phy *phy;
int ret;
- ks_pcie = devm_kzalloc(&pdev->dev, sizeof(*ks_pcie),
- GFP_KERNEL);
- if (!ks_pcie)
+ keystone = devm_kzalloc(&pdev->dev, sizeof(*keystone), GFP_KERNEL);
+ if (!keystone)
return -ENOMEM;
- pp = &ks_pcie->pp;
+ pp = &keystone->pp;
/* initialize SerDes Phy if present */
phy = devm_phy_get(dev, "pcie-phy");
@@ -404,29 +403,29 @@ static int __init ks_pcie_probe(struct platform_device *pdev)
reg_p = devm_ioremap_resource(dev, res);
if (IS_ERR(reg_p))
return PTR_ERR(reg_p);
- ks_pcie->device_id = readl(reg_p) >> 16;
+ keystone->device_id = readl(reg_p) >> 16;
devm_iounmap(dev, reg_p);
devm_release_mem_region(dev, res->start, resource_size(res));
pp->dev = dev;
- ks_pcie->np = dev->of_node;
- platform_set_drvdata(pdev, ks_pcie);
- ks_pcie->clk = devm_clk_get(dev, "pcie");
- if (IS_ERR(ks_pcie->clk)) {
+ keystone->np = dev->of_node;
+ platform_set_drvdata(pdev, keystone);
+ keystone->clk = devm_clk_get(dev, "pcie");
+ if (IS_ERR(keystone->clk)) {
dev_err(dev, "Failed to get pcie rc clock\n");
- return PTR_ERR(ks_pcie->clk);
+ return PTR_ERR(keystone->clk);
}
- ret = clk_prepare_enable(ks_pcie->clk);
+ ret = clk_prepare_enable(keystone->clk);
if (ret)
return ret;
- ret = ks_add_pcie_port(ks_pcie, pdev);
+ ret = ks_add_pcie_port(keystone, pdev);
if (ret < 0)
goto fail_clk;
return 0;
fail_clk:
- clk_disable_unprepare(ks_pcie->clk);
+ clk_disable_unprepare(keystone->clk);
return ret;
}
diff --git a/drivers/pci/host/pci-keystone.h b/drivers/pci/host/pci-keystone.h
index a5b0cb2..379213c 100644
--- a/drivers/pci/host/pci-keystone.h
+++ b/drivers/pci/host/pci-keystone.h
@@ -39,24 +39,24 @@ struct keystone_pcie {
};
/* Keystone DW specific MSI controller APIs/definitions */
-void ks_dw_pcie_handle_msi_irq(struct keystone_pcie *ks_pcie, int offset);
+void ks_dw_pcie_handle_msi_irq(struct keystone_pcie *keystone, int offset);
phys_addr_t ks_dw_pcie_get_msi_addr(struct pcie_port *pp);
/* Keystone specific PCI controller APIs */
-void ks_dw_pcie_enable_legacy_irqs(struct keystone_pcie *ks_pcie);
-void ks_dw_pcie_handle_legacy_irq(struct keystone_pcie *ks_pcie, int offset);
+void ks_dw_pcie_enable_legacy_irqs(struct keystone_pcie *keystone);
+void ks_dw_pcie_handle_legacy_irq(struct keystone_pcie *keystone, int offset);
void ks_dw_pcie_enable_error_irq(void __iomem *reg_base);
irqreturn_t ks_dw_pcie_handle_error_irq(struct device *dev,
void __iomem *reg_base);
-int ks_dw_pcie_host_init(struct keystone_pcie *ks_pcie,
+int ks_dw_pcie_host_init(struct keystone_pcie *keystone,
struct device_node *msi_intc_np);
int ks_dw_pcie_wr_other_conf(struct pcie_port *pp, struct pci_bus *bus,
unsigned int devfn, int where, int size, u32 val);
int ks_dw_pcie_rd_other_conf(struct pcie_port *pp, struct pci_bus *bus,
unsigned int devfn, int where, int size, u32 *val);
-void ks_dw_pcie_setup_rc_app_regs(struct keystone_pcie *ks_pcie);
+void ks_dw_pcie_setup_rc_app_regs(struct keystone_pcie *keystone);
int ks_dw_pcie_link_up(struct pcie_port *pp);
-void ks_dw_pcie_initiate_link_train(struct keystone_pcie *ks_pcie);
+void ks_dw_pcie_initiate_link_train(struct keystone_pcie *keystone);
void ks_dw_pcie_msi_set_irq(struct pcie_port *pp, int irq);
void ks_dw_pcie_msi_clear_irq(struct pcie_port *pp, int irq);
void ks_dw_pcie_v3_65_scan_bus(struct pcie_port *pp);
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH 2/6] PCI: keystone: Pass keystone_pcie, not address, to IRQ functions
2016-10-07 16:40 [PATCH 1/6] PCI: keystone: Name private struct pointer "keystone" consistently Bjorn Helgaas
@ 2016-10-07 16:40 ` Bjorn Helgaas
2016-10-07 16:40 ` [PATCH 3/6] PCI: keystone: Pass keystone_pcie, not address, to DBI functions Bjorn Helgaas
` (4 subsequent siblings)
5 siblings, 0 replies; 9+ messages in thread
From: Bjorn Helgaas @ 2016-10-07 16:40 UTC (permalink / raw)
To: Murali Karicheri; +Cc: linux-pci
Instead of passing the application register base to IRQ functions,
pass the struct keystone_pcie. This will allow them to use register
accessors. No functional change intended.
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
---
drivers/pci/host/pci-keystone-dw.c | 15 ++++++++-------
drivers/pci/host/pci-keystone.c | 5 ++---
drivers/pci/host/pci-keystone.h | 5 ++---
3 files changed, 12 insertions(+), 13 deletions(-)
diff --git a/drivers/pci/host/pci-keystone-dw.c b/drivers/pci/host/pci-keystone-dw.c
index d09e3c6..5c67d54 100644
--- a/drivers/pci/host/pci-keystone-dw.c
+++ b/drivers/pci/host/pci-keystone-dw.c
@@ -259,25 +259,26 @@ void ks_dw_pcie_handle_legacy_irq(struct keystone_pcie *keystone, int offset)
writel(offset, keystone->va_app_base + IRQ_EOI);
}
-void ks_dw_pcie_enable_error_irq(void __iomem *reg_base)
+void ks_dw_pcie_enable_error_irq(struct keystone_pcie *keystone)
{
- writel(ERR_IRQ_ALL, reg_base + ERR_IRQ_ENABLE_SET);
+ writel(ERR_IRQ_ALL, keystone->va_app_base + ERR_IRQ_ENABLE_SET);
}
-irqreturn_t ks_dw_pcie_handle_error_irq(struct device *dev,
- void __iomem *reg_base)
+irqreturn_t ks_dw_pcie_handle_error_irq(struct keystone_pcie *keystone)
{
u32 status;
- status = readl(reg_base + ERR_IRQ_STATUS_RAW) & ERR_IRQ_ALL;
+ status = readl(keystone->va_app_base + ERR_IRQ_STATUS_RAW) &
+ ERR_IRQ_ALL;
if (!status)
return IRQ_NONE;
if (status & ERR_FATAL_IRQ)
- dev_err(dev, "fatal error (status %#010x)\n", status);
+ dev_err(keystone->pp.dev, "fatal error (status %#010x)\n",
+ status);
/* Ack the IRQ; status bits are RW1C */
- writel(status, reg_base + ERR_IRQ_STATUS);
+ writel(status, keystone->va_app_base + ERR_IRQ_STATUS);
return IRQ_HANDLED;
}
diff --git a/drivers/pci/host/pci-keystone.c b/drivers/pci/host/pci-keystone.c
index 55b2be7..6b1cb14 100644
--- a/drivers/pci/host/pci-keystone.c
+++ b/drivers/pci/host/pci-keystone.c
@@ -234,7 +234,7 @@ static void ks_pcie_setup_interrupts(struct keystone_pcie *keystone)
}
if (keystone->error_irq > 0)
- ks_dw_pcie_enable_error_irq(keystone->va_app_base);
+ ks_dw_pcie_enable_error_irq(keystone);
}
/*
@@ -302,8 +302,7 @@ static irqreturn_t pcie_err_irq_handler(int irq, void *priv)
{
struct keystone_pcie *keystone = priv;
- return ks_dw_pcie_handle_error_irq(keystone->pp.dev,
- keystone->va_app_base);
+ return ks_dw_pcie_handle_error_irq(keystone);
}
static int __init ks_add_pcie_port(struct keystone_pcie *keystone,
diff --git a/drivers/pci/host/pci-keystone.h b/drivers/pci/host/pci-keystone.h
index 379213c..2a81e05 100644
--- a/drivers/pci/host/pci-keystone.h
+++ b/drivers/pci/host/pci-keystone.h
@@ -45,9 +45,8 @@ phys_addr_t ks_dw_pcie_get_msi_addr(struct pcie_port *pp);
/* Keystone specific PCI controller APIs */
void ks_dw_pcie_enable_legacy_irqs(struct keystone_pcie *keystone);
void ks_dw_pcie_handle_legacy_irq(struct keystone_pcie *keystone, int offset);
-void ks_dw_pcie_enable_error_irq(void __iomem *reg_base);
-irqreturn_t ks_dw_pcie_handle_error_irq(struct device *dev,
- void __iomem *reg_base);
+void ks_dw_pcie_enable_error_irq(struct keystone_pcie *keystone);
+irqreturn_t ks_dw_pcie_handle_error_irq(struct keystone_pcie *keystone);
int ks_dw_pcie_host_init(struct keystone_pcie *keystone,
struct device_node *msi_intc_np);
int ks_dw_pcie_wr_other_conf(struct pcie_port *pp, struct pci_bus *bus,
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH 3/6] PCI: keystone: Pass keystone_pcie, not address, to DBI functions
2016-10-07 16:40 [PATCH 1/6] PCI: keystone: Name private struct pointer "keystone" consistently Bjorn Helgaas
2016-10-07 16:40 ` [PATCH 2/6] PCI: keystone: Pass keystone_pcie, not address, to IRQ functions Bjorn Helgaas
@ 2016-10-07 16:40 ` Bjorn Helgaas
2016-10-07 16:40 ` [PATCH 4/6] PCI: keystone: Add app register accessors Bjorn Helgaas
` (3 subsequent siblings)
5 siblings, 0 replies; 9+ messages in thread
From: Bjorn Helgaas @ 2016-10-07 16:40 UTC (permalink / raw)
To: Murali Karicheri; +Cc: linux-pci
Instead of passing the application register base to DBI mode functions,
pass the struct keystone_pcie. This will allow them to use register
accessors. No functional change intended.
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
---
drivers/pci/host/pci-keystone-dw.c | 24 ++++++++++++------------
1 file changed, 12 insertions(+), 12 deletions(-)
diff --git a/drivers/pci/host/pci-keystone-dw.c b/drivers/pci/host/pci-keystone-dw.c
index 5c67d54..aeb08e8 100644
--- a/drivers/pci/host/pci-keystone-dw.c
+++ b/drivers/pci/host/pci-keystone-dw.c
@@ -323,15 +323,15 @@ static const struct irq_domain_ops ks_dw_pcie_legacy_irq_domain_ops = {
* Since modification of dbi_cs2 involves different clock domain, read the
* status back to ensure the transition is complete.
*/
-static void ks_dw_pcie_set_dbi_mode(void __iomem *reg_virt)
+static void ks_dw_pcie_set_dbi_mode(struct keystone_pcie *keystone)
{
u32 val;
- writel(DBI_CS2_EN_VAL | readl(reg_virt + CMD_STATUS),
- reg_virt + CMD_STATUS);
+ writel(DBI_CS2_EN_VAL | readl(keystone->va_app_base + CMD_STATUS),
+ keystone->va_app_base + CMD_STATUS);
do {
- val = readl(reg_virt + CMD_STATUS);
+ val = readl(keystone->va_app_base + CMD_STATUS);
} while (!(val & DBI_CS2_EN_VAL));
}
@@ -341,15 +341,15 @@ static void ks_dw_pcie_set_dbi_mode(void __iomem *reg_virt)
* Since modification of dbi_cs2 involves different clock domain, read the
* status back to ensure the transition is complete.
*/
-static void ks_dw_pcie_clear_dbi_mode(void __iomem *reg_virt)
+static void ks_dw_pcie_clear_dbi_mode(struct keystone_pcie *keystone)
{
u32 val;
- writel(~DBI_CS2_EN_VAL & readl(reg_virt + CMD_STATUS),
- reg_virt + CMD_STATUS);
+ writel(~DBI_CS2_EN_VAL & readl(keystone->va_app_base + CMD_STATUS),
+ keystone->va_app_base + CMD_STATUS);
do {
- val = readl(reg_virt + CMD_STATUS);
+ val = readl(keystone->va_app_base + CMD_STATUS);
} while (val & DBI_CS2_EN_VAL);
}
@@ -360,10 +360,10 @@ void ks_dw_pcie_setup_rc_app_regs(struct keystone_pcie *keystone)
int i, tr_size;
/* Disable BARs for inbound access */
- ks_dw_pcie_set_dbi_mode(keystone->va_app_base);
+ ks_dw_pcie_set_dbi_mode(keystone);
writel(0, pp->dbi_base + PCI_BASE_ADDRESS_0);
writel(0, pp->dbi_base + PCI_BASE_ADDRESS_1);
- ks_dw_pcie_clear_dbi_mode(keystone->va_app_base);
+ ks_dw_pcie_clear_dbi_mode(keystone);
/* Set outbound translation size per window division */
writel(CFG_PCIM_WIN_SZ_IDX & 0x7, keystone->va_app_base + OB_SIZE);
@@ -457,13 +457,13 @@ void ks_dw_pcie_v3_65_scan_bus(struct pcie_port *pp)
struct keystone_pcie *keystone = to_keystone_pcie(pp);
/* Configure and set up BAR0 */
- ks_dw_pcie_set_dbi_mode(keystone->va_app_base);
+ ks_dw_pcie_set_dbi_mode(keystone);
/* Enable BAR0 */
writel(1, pp->dbi_base + PCI_BASE_ADDRESS_0);
writel(SZ_4K - 1, pp->dbi_base + PCI_BASE_ADDRESS_0);
- ks_dw_pcie_clear_dbi_mode(keystone->va_app_base);
+ ks_dw_pcie_clear_dbi_mode(keystone);
/*
* For BAR0, just setting bus address for inbound writes (MSI) should
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH 4/6] PCI: keystone: Add app register accessors
2016-10-07 16:40 [PATCH 1/6] PCI: keystone: Name private struct pointer "keystone" consistently Bjorn Helgaas
2016-10-07 16:40 ` [PATCH 2/6] PCI: keystone: Pass keystone_pcie, not address, to IRQ functions Bjorn Helgaas
2016-10-07 16:40 ` [PATCH 3/6] PCI: keystone: Pass keystone_pcie, not address, to DBI functions Bjorn Helgaas
@ 2016-10-07 16:40 ` Bjorn Helgaas
2016-10-07 16:41 ` [PATCH 5/6] PCI: keystone: Reorder struct keystone_pcie Bjorn Helgaas
` (2 subsequent siblings)
5 siblings, 0 replies; 9+ messages in thread
From: Bjorn Helgaas @ 2016-10-07 16:40 UTC (permalink / raw)
To: Murali Karicheri; +Cc: linux-pci
Add device-specific register accessors for consistency across host drivers.
No functional change intended.
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
---
drivers/pci/host/pci-keystone-dw.c | 73 +++++++++++++++++++++---------------
1 file changed, 42 insertions(+), 31 deletions(-)
diff --git a/drivers/pci/host/pci-keystone-dw.c b/drivers/pci/host/pci-keystone-dw.c
index aeb08e8..5be7cf4 100644
--- a/drivers/pci/host/pci-keystone-dw.c
+++ b/drivers/pci/host/pci-keystone-dw.c
@@ -88,13 +88,24 @@ phys_addr_t ks_dw_pcie_get_msi_addr(struct pcie_port *pp)
return keystone->app.start + MSI_IRQ;
}
+static u32 ks_dw_app_readl(struct keystone_pcie *keystone, u32 offset)
+{
+ return readl(keystone->va_app_base + offset);
+}
+
+static void ks_dw_app_writel(struct keystone_pcie *keystone, u32 offset,
+ u32 val)
+{
+ writel(val, keystone->va_app_base + offset);
+}
+
void ks_dw_pcie_handle_msi_irq(struct keystone_pcie *keystone, int offset)
{
struct pcie_port *pp = &keystone->pp;
u32 pending, vector;
int src, virq;
- pending = readl(keystone->va_app_base + MSI0_IRQ_STATUS + (offset << 4));
+ pending = ks_dw_app_readl(keystone, MSI0_IRQ_STATUS + (offset << 4));
/*
* MSI0 status bit 0-3 shows vectors 0, 8, 16, 24, MSI1 status bit
@@ -124,9 +135,9 @@ static void ks_dw_pcie_msi_irq_ack(struct irq_data *d)
offset = d->irq - irq_linear_revmap(pp->irq_domain, 0);
update_reg_offset_bit_pos(offset, ®_offset, &bit_pos);
- writel(BIT(bit_pos),
- keystone->va_app_base + MSI0_IRQ_STATUS + (reg_offset << 4));
- writel(reg_offset + MSI_IRQ_OFFSET, keystone->va_app_base + IRQ_EOI);
+ ks_dw_app_writel(keystone, MSI0_IRQ_STATUS + (reg_offset << 4),
+ BIT(bit_pos));
+ ks_dw_app_writel(keystone, IRQ_EOI, reg_offset + MSI_IRQ_OFFSET);
}
void ks_dw_pcie_msi_set_irq(struct pcie_port *pp, int irq)
@@ -135,8 +146,8 @@ void ks_dw_pcie_msi_set_irq(struct pcie_port *pp, int irq)
struct keystone_pcie *keystone = to_keystone_pcie(pp);
update_reg_offset_bit_pos(irq, ®_offset, &bit_pos);
- writel(BIT(bit_pos),
- keystone->va_app_base + MSI0_IRQ_ENABLE_SET + (reg_offset << 4));
+ ks_dw_app_writel(keystone, MSI0_IRQ_ENABLE_SET + (reg_offset << 4),
+ BIT(bit_pos));
}
void ks_dw_pcie_msi_clear_irq(struct pcie_port *pp, int irq)
@@ -145,8 +156,8 @@ void ks_dw_pcie_msi_clear_irq(struct pcie_port *pp, int irq)
struct keystone_pcie *keystone = to_keystone_pcie(pp);
update_reg_offset_bit_pos(irq, ®_offset, &bit_pos);
- writel(BIT(bit_pos),
- keystone->va_app_base + MSI0_IRQ_ENABLE_CLR + (reg_offset << 4));
+ ks_dw_app_writel(keystone, MSI0_IRQ_ENABLE_CLR + (reg_offset << 4),
+ BIT(bit_pos));
}
static void ks_dw_pcie_msi_irq_mask(struct irq_data *d)
@@ -237,7 +248,7 @@ void ks_dw_pcie_enable_legacy_irqs(struct keystone_pcie *keystone)
int i;
for (i = 0; i < MAX_LEGACY_IRQS; i++)
- writel(0x1, keystone->va_app_base + IRQ_ENABLE_SET + (i << 4));
+ ks_dw_app_writel(keystone, IRQ_ENABLE_SET + (i << 4), 0x1);
}
void ks_dw_pcie_handle_legacy_irq(struct keystone_pcie *keystone, int offset)
@@ -246,7 +257,7 @@ void ks_dw_pcie_handle_legacy_irq(struct keystone_pcie *keystone, int offset)
u32 pending;
int virq;
- pending = readl(keystone->va_app_base + IRQ_STATUS + (offset << 4));
+ pending = ks_dw_app_readl(keystone, IRQ_STATUS + (offset << 4));
if (BIT(0) & pending) {
virq = irq_linear_revmap(keystone->legacy_irq_domain, offset);
@@ -256,20 +267,19 @@ void ks_dw_pcie_handle_legacy_irq(struct keystone_pcie *keystone, int offset)
}
/* EOI the INTx interrupt */
- writel(offset, keystone->va_app_base + IRQ_EOI);
+ ks_dw_app_writel(keystone, IRQ_EOI, offset);
}
void ks_dw_pcie_enable_error_irq(struct keystone_pcie *keystone)
{
- writel(ERR_IRQ_ALL, keystone->va_app_base + ERR_IRQ_ENABLE_SET);
+ ks_dw_app_writel(keystone, ERR_IRQ_ENABLE_SET, ERR_IRQ_ALL);
}
irqreturn_t ks_dw_pcie_handle_error_irq(struct keystone_pcie *keystone)
{
u32 status;
- status = readl(keystone->va_app_base + ERR_IRQ_STATUS_RAW) &
- ERR_IRQ_ALL;
+ status = ks_dw_app_readl(keystone, ERR_IRQ_STATUS_RAW) & ERR_IRQ_ALL;
if (!status)
return IRQ_NONE;
@@ -278,7 +288,7 @@ irqreturn_t ks_dw_pcie_handle_error_irq(struct keystone_pcie *keystone)
status);
/* Ack the IRQ; status bits are RW1C */
- writel(status, keystone->va_app_base + ERR_IRQ_STATUS);
+ ks_dw_app_writel(keystone, ERR_IRQ_STATUS, status);
return IRQ_HANDLED;
}
@@ -327,11 +337,11 @@ static void ks_dw_pcie_set_dbi_mode(struct keystone_pcie *keystone)
{
u32 val;
- writel(DBI_CS2_EN_VAL | readl(keystone->va_app_base + CMD_STATUS),
- keystone->va_app_base + CMD_STATUS);
+ val = ks_dw_app_readl(keystone, CMD_STATUS);
+ ks_dw_app_writel(keystone, CMD_STATUS, DBI_CS2_EN_VAL | val);
do {
- val = readl(keystone->va_app_base + CMD_STATUS);
+ val = ks_dw_app_readl(keystone, CMD_STATUS);
} while (!(val & DBI_CS2_EN_VAL));
}
@@ -345,11 +355,11 @@ static void ks_dw_pcie_clear_dbi_mode(struct keystone_pcie *keystone)
{
u32 val;
- writel(~DBI_CS2_EN_VAL & readl(keystone->va_app_base + CMD_STATUS),
- keystone->va_app_base + CMD_STATUS);
+ val = ks_dw_app_readl(keystone, CMD_STATUS);
+ ks_dw_app_writel(keystone, CMD_STATUS, ~DBI_CS2_EN_VAL & val);
do {
- val = readl(keystone->va_app_base + CMD_STATUS);
+ val = ks_dw_app_readl(keystone, CMD_STATUS);
} while (val & DBI_CS2_EN_VAL);
}
@@ -358,6 +368,7 @@ void ks_dw_pcie_setup_rc_app_regs(struct keystone_pcie *keystone)
struct pcie_port *pp = &keystone->pp;
u32 start = pp->mem->start, end = pp->mem->end;
int i, tr_size;
+ u32 val;
/* Disable BARs for inbound access */
ks_dw_pcie_set_dbi_mode(keystone);
@@ -366,20 +377,20 @@ void ks_dw_pcie_setup_rc_app_regs(struct keystone_pcie *keystone)
ks_dw_pcie_clear_dbi_mode(keystone);
/* Set outbound translation size per window division */
- writel(CFG_PCIM_WIN_SZ_IDX & 0x7, keystone->va_app_base + OB_SIZE);
+ ks_dw_app_writel(keystone, OB_SIZE, CFG_PCIM_WIN_SZ_IDX & 0x7);
tr_size = (1 << (CFG_PCIM_WIN_SZ_IDX & 0x7)) * SZ_1M;
/* Using Direct 1:1 mapping of RC <-> PCI memory space */
for (i = 0; (i < CFG_PCIM_WIN_CNT) && (start < end); i++) {
- writel(start | 1, keystone->va_app_base + OB_OFFSET_INDEX(i));
- writel(0, keystone->va_app_base + OB_OFFSET_HI(i));
+ ks_dw_app_writel(keystone, OB_OFFSET_INDEX(i), start | 1);
+ ks_dw_app_writel(keystone, OB_OFFSET_HI(i), 0);
start += tr_size;
}
/* Enable OB translation */
- writel(OB_XLAT_EN_VAL | readl(keystone->va_app_base + CMD_STATUS),
- keystone->va_app_base + CMD_STATUS);
+ val = ks_dw_app_readl(keystone, CMD_STATUS);
+ ks_dw_app_writel(keystone, CMD_STATUS, OB_XLAT_EN_VAL | val);
}
/**
@@ -419,7 +430,7 @@ static void __iomem *ks_pcie_cfg_setup(struct keystone_pcie *keystone, u8 bus,
if (bus != 1)
regval |= BIT(24);
- writel(regval, keystone->va_app_base + CFG_SETUP);
+ ks_dw_app_writel(keystone, CFG_SETUP, regval);
return pp->va_cfg0_base;
}
@@ -487,13 +498,13 @@ void ks_dw_pcie_initiate_link_train(struct keystone_pcie *keystone)
u32 val;
/* Disable Link training */
- val = readl(keystone->va_app_base + CMD_STATUS);
+ val = ks_dw_app_readl(keystone, CMD_STATUS);
val &= ~LTSSM_EN_VAL;
- writel(LTSSM_EN_VAL | val, keystone->va_app_base + CMD_STATUS);
+ ks_dw_app_writel(keystone, CMD_STATUS, LTSSM_EN_VAL | val);
/* Initiate Link Training */
- val = readl(keystone->va_app_base + CMD_STATUS);
- writel(LTSSM_EN_VAL | val, keystone->va_app_base + CMD_STATUS);
+ val = ks_dw_app_readl(keystone, CMD_STATUS);
+ ks_dw_app_writel(keystone, CMD_STATUS, LTSSM_EN_VAL | val);
}
/**
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH 5/6] PCI: keystone: Reorder struct keystone_pcie
2016-10-07 16:40 [PATCH 1/6] PCI: keystone: Name private struct pointer "keystone" consistently Bjorn Helgaas
` (2 preceding siblings ...)
2016-10-07 16:40 ` [PATCH 4/6] PCI: keystone: Add app register accessors Bjorn Helgaas
@ 2016-10-07 16:41 ` Bjorn Helgaas
2016-10-07 16:41 ` [PATCH 6/6] PCI: keystone: Use dw_pcie_readl_rc() and dw_pcie_pcie_writel_rc() Bjorn Helgaas
2016-10-07 16:53 ` [PATCH 1/6] PCI: keystone: Name private struct pointer "keystone" consistently Murali Karicheri
5 siblings, 0 replies; 9+ messages in thread
From: Bjorn Helgaas @ 2016-10-07 16:41 UTC (permalink / raw)
To: Murali Karicheri; +Cc: linux-pci
Reorder struct keystone_pcie to put generic fields first. No functional
change intended.
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
---
drivers/pci/host/pci-keystone.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/pci/host/pci-keystone.h b/drivers/pci/host/pci-keystone.h
index 2a81e05..be0ddc4 100644
--- a/drivers/pci/host/pci-keystone.h
+++ b/drivers/pci/host/pci-keystone.h
@@ -17,8 +17,8 @@
#define MAX_LEGACY_HOST_IRQS 4
struct keystone_pcie {
+ struct pcie_port pp; /* pp.dbi_base is DT 0th res */
struct clk *clk;
- struct pcie_port pp;
/* PCI Device ID */
u32 device_id;
int num_legacy_host_irqs;
@@ -34,7 +34,7 @@ struct keystone_pcie {
int error_irq;
/* Application register space */
- void __iomem *va_app_base;
+ void __iomem *va_app_base; /* DT 1st resource */
struct resource app;
};
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH 6/6] PCI: keystone: Use dw_pcie_readl_rc() and dw_pcie_pcie_writel_rc()
2016-10-07 16:40 [PATCH 1/6] PCI: keystone: Name private struct pointer "keystone" consistently Bjorn Helgaas
` (3 preceding siblings ...)
2016-10-07 16:41 ` [PATCH 5/6] PCI: keystone: Reorder struct keystone_pcie Bjorn Helgaas
@ 2016-10-07 16:41 ` Bjorn Helgaas
2016-10-07 16:53 ` [PATCH 1/6] PCI: keystone: Name private struct pointer "keystone" consistently Murali Karicheri
5 siblings, 0 replies; 9+ messages in thread
From: Bjorn Helgaas @ 2016-10-07 16:41 UTC (permalink / raw)
To: Murali Karicheri; +Cc: linux-pci
Use the DesignWare-generic register accessors instead of doing readl() and
writel() directly. No functional change intended.
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
---
drivers/pci/host/pci-keystone-dw.c | 13 +++++++------
1 file changed, 7 insertions(+), 6 deletions(-)
diff --git a/drivers/pci/host/pci-keystone-dw.c b/drivers/pci/host/pci-keystone-dw.c
index 5be7cf4..e8dee7b 100644
--- a/drivers/pci/host/pci-keystone-dw.c
+++ b/drivers/pci/host/pci-keystone-dw.c
@@ -372,8 +372,8 @@ void ks_dw_pcie_setup_rc_app_regs(struct keystone_pcie *keystone)
/* Disable BARs for inbound access */
ks_dw_pcie_set_dbi_mode(keystone);
- writel(0, pp->dbi_base + PCI_BASE_ADDRESS_0);
- writel(0, pp->dbi_base + PCI_BASE_ADDRESS_1);
+ dw_pcie_writel_rc(pp, PCI_BASE_ADDRESS_0, 0);
+ dw_pcie_writel_rc(pp, PCI_BASE_ADDRESS_1, 0);
ks_dw_pcie_clear_dbi_mode(keystone);
/* Set outbound translation size per window division */
@@ -471,8 +471,8 @@ void ks_dw_pcie_v3_65_scan_bus(struct pcie_port *pp)
ks_dw_pcie_set_dbi_mode(keystone);
/* Enable BAR0 */
- writel(1, pp->dbi_base + PCI_BASE_ADDRESS_0);
- writel(SZ_4K - 1, pp->dbi_base + PCI_BASE_ADDRESS_0);
+ dw_pcie_writel_rc(pp, PCI_BASE_ADDRESS_0, 1);
+ dw_pcie_writel_rc(pp, PCI_BASE_ADDRESS_0, SZ_4K - 1);
ks_dw_pcie_clear_dbi_mode(keystone);
@@ -480,7 +480,7 @@ void ks_dw_pcie_v3_65_scan_bus(struct pcie_port *pp)
* For BAR0, just setting bus address for inbound writes (MSI) should
* be sufficient. Use physical address to avoid any conflicts.
*/
- writel(keystone->app.start, pp->dbi_base + PCI_BASE_ADDRESS_0);
+ dw_pcie_writel_rc(pp, PCI_BASE_ADDRESS_0, keystone->app.start);
}
/**
@@ -488,8 +488,9 @@ void ks_dw_pcie_v3_65_scan_bus(struct pcie_port *pp)
*/
int ks_dw_pcie_link_up(struct pcie_port *pp)
{
- u32 val = readl(pp->dbi_base + DEBUG0);
+ u32 val;
+ val = dw_pcie_readl_rc(pp, DEBUG0);
return (val & LTSSM_STATE_MASK) == LTSSM_STATE_L0;
}
^ permalink raw reply related [flat|nested] 9+ messages in thread
* Re: [PATCH 1/6] PCI: keystone: Name private struct pointer "keystone" consistently
2016-10-07 16:40 [PATCH 1/6] PCI: keystone: Name private struct pointer "keystone" consistently Bjorn Helgaas
` (4 preceding siblings ...)
2016-10-07 16:41 ` [PATCH 6/6] PCI: keystone: Use dw_pcie_readl_rc() and dw_pcie_pcie_writel_rc() Bjorn Helgaas
@ 2016-10-07 16:53 ` Murali Karicheri
2016-10-07 16:56 ` Murali Karicheri
2016-10-07 18:09 ` Bjorn Helgaas
5 siblings, 2 replies; 9+ messages in thread
From: Murali Karicheri @ 2016-10-07 16:53 UTC (permalink / raw)
To: Bjorn Helgaas; +Cc: linux-pci
On 10/07/2016 12:40 PM, Bjorn Helgaas wrote:
> Use a device-specific name, "keystone", for struct keystone_pcie pointers
referring to keystone pcie as keystone is not right. keystone_pcie make sense.
To use a short name ks_pcie was used. So what is wrong with the naming?
I believe this patch is unnecessary.
Murali
> to hint that this is device-specific information. No functional change
> intended.
>
> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
> ---
> drivers/pci/host/pci-keystone-dw.c | 122 ++++++++++++++++++-----------------
> drivers/pci/host/pci-keystone.c | 125 ++++++++++++++++++------------------
> drivers/pci/host/pci-keystone.h | 12 ++-
> 3 files changed, 129 insertions(+), 130 deletions(-)
>
> diff --git a/drivers/pci/host/pci-keystone-dw.c b/drivers/pci/host/pci-keystone-dw.c
> index 4151509..d09e3c6 100644
> --- a/drivers/pci/host/pci-keystone-dw.c
> +++ b/drivers/pci/host/pci-keystone-dw.c
> @@ -83,18 +83,18 @@ static inline void update_reg_offset_bit_pos(u32 offset, u32 *reg_offset,
>
> phys_addr_t ks_dw_pcie_get_msi_addr(struct pcie_port *pp)
> {
> - struct keystone_pcie *ks_pcie = to_keystone_pcie(pp);
> + struct keystone_pcie *keystone = to_keystone_pcie(pp);
>
> - return ks_pcie->app.start + MSI_IRQ;
> + return keystone->app.start + MSI_IRQ;
> }
>
> -void ks_dw_pcie_handle_msi_irq(struct keystone_pcie *ks_pcie, int offset)
> +void ks_dw_pcie_handle_msi_irq(struct keystone_pcie *keystone, int offset)
> {
> - struct pcie_port *pp = &ks_pcie->pp;
> + struct pcie_port *pp = &keystone->pp;
> u32 pending, vector;
> int src, virq;
>
> - pending = readl(ks_pcie->va_app_base + MSI0_IRQ_STATUS + (offset << 4));
> + pending = readl(keystone->va_app_base + MSI0_IRQ_STATUS + (offset << 4));
>
> /*
> * MSI0 status bit 0-3 shows vectors 0, 8, 16, 24, MSI1 status bit
> @@ -114,51 +114,51 @@ void ks_dw_pcie_handle_msi_irq(struct keystone_pcie *ks_pcie, int offset)
> static void ks_dw_pcie_msi_irq_ack(struct irq_data *d)
> {
> u32 offset, reg_offset, bit_pos;
> - struct keystone_pcie *ks_pcie;
> + struct keystone_pcie *keystone;
> struct msi_desc *msi;
> struct pcie_port *pp;
>
> msi = irq_data_get_msi_desc(d);
> pp = (struct pcie_port *) msi_desc_to_pci_sysdata(msi);
> - ks_pcie = to_keystone_pcie(pp);
> + keystone = to_keystone_pcie(pp);
> offset = d->irq - irq_linear_revmap(pp->irq_domain, 0);
> update_reg_offset_bit_pos(offset, ®_offset, &bit_pos);
>
> writel(BIT(bit_pos),
> - ks_pcie->va_app_base + MSI0_IRQ_STATUS + (reg_offset << 4));
> - writel(reg_offset + MSI_IRQ_OFFSET, ks_pcie->va_app_base + IRQ_EOI);
> + keystone->va_app_base + MSI0_IRQ_STATUS + (reg_offset << 4));
> + writel(reg_offset + MSI_IRQ_OFFSET, keystone->va_app_base + IRQ_EOI);
> }
>
> void ks_dw_pcie_msi_set_irq(struct pcie_port *pp, int irq)
> {
> u32 reg_offset, bit_pos;
> - struct keystone_pcie *ks_pcie = to_keystone_pcie(pp);
> + struct keystone_pcie *keystone = to_keystone_pcie(pp);
>
> update_reg_offset_bit_pos(irq, ®_offset, &bit_pos);
> writel(BIT(bit_pos),
> - ks_pcie->va_app_base + MSI0_IRQ_ENABLE_SET + (reg_offset << 4));
> + keystone->va_app_base + MSI0_IRQ_ENABLE_SET + (reg_offset << 4));
> }
>
> void ks_dw_pcie_msi_clear_irq(struct pcie_port *pp, int irq)
> {
> u32 reg_offset, bit_pos;
> - struct keystone_pcie *ks_pcie = to_keystone_pcie(pp);
> + struct keystone_pcie *keystone = to_keystone_pcie(pp);
>
> update_reg_offset_bit_pos(irq, ®_offset, &bit_pos);
> writel(BIT(bit_pos),
> - ks_pcie->va_app_base + MSI0_IRQ_ENABLE_CLR + (reg_offset << 4));
> + keystone->va_app_base + MSI0_IRQ_ENABLE_CLR + (reg_offset << 4));
> }
>
> static void ks_dw_pcie_msi_irq_mask(struct irq_data *d)
> {
> - struct keystone_pcie *ks_pcie;
> + struct keystone_pcie *keystone;
> struct msi_desc *msi;
> struct pcie_port *pp;
> u32 offset;
>
> msi = irq_data_get_msi_desc(d);
> pp = (struct pcie_port *) msi_desc_to_pci_sysdata(msi);
> - ks_pcie = to_keystone_pcie(pp);
> + keystone = to_keystone_pcie(pp);
> offset = d->irq - irq_linear_revmap(pp->irq_domain, 0);
>
> /* Mask the end point if PVM implemented */
> @@ -172,14 +172,14 @@ static void ks_dw_pcie_msi_irq_mask(struct irq_data *d)
>
> static void ks_dw_pcie_msi_irq_unmask(struct irq_data *d)
> {
> - struct keystone_pcie *ks_pcie;
> + struct keystone_pcie *keystone;
> struct msi_desc *msi;
> struct pcie_port *pp;
> u32 offset;
>
> msi = irq_data_get_msi_desc(d);
> pp = (struct pcie_port *) msi_desc_to_pci_sysdata(msi);
> - ks_pcie = to_keystone_pcie(pp);
> + keystone = to_keystone_pcie(pp);
> offset = d->irq - irq_linear_revmap(pp->irq_domain, 0);
>
> /* Mask the end point if PVM implemented */
> @@ -214,10 +214,10 @@ static const struct irq_domain_ops ks_dw_pcie_msi_domain_ops = {
>
> int ks_dw_pcie_msi_host_init(struct pcie_port *pp, struct msi_controller *chip)
> {
> - struct keystone_pcie *ks_pcie = to_keystone_pcie(pp);
> + struct keystone_pcie *keystone = to_keystone_pcie(pp);
> int i;
>
> - pp->irq_domain = irq_domain_add_linear(ks_pcie->msi_intc_np,
> + pp->irq_domain = irq_domain_add_linear(keystone->msi_intc_np,
> MAX_MSI_IRQS,
> &ks_dw_pcie_msi_domain_ops,
> chip);
> @@ -232,31 +232,31 @@ int ks_dw_pcie_msi_host_init(struct pcie_port *pp, struct msi_controller *chip)
> return 0;
> }
>
> -void ks_dw_pcie_enable_legacy_irqs(struct keystone_pcie *ks_pcie)
> +void ks_dw_pcie_enable_legacy_irqs(struct keystone_pcie *keystone)
> {
> int i;
>
> for (i = 0; i < MAX_LEGACY_IRQS; i++)
> - writel(0x1, ks_pcie->va_app_base + IRQ_ENABLE_SET + (i << 4));
> + writel(0x1, keystone->va_app_base + IRQ_ENABLE_SET + (i << 4));
> }
>
> -void ks_dw_pcie_handle_legacy_irq(struct keystone_pcie *ks_pcie, int offset)
> +void ks_dw_pcie_handle_legacy_irq(struct keystone_pcie *keystone, int offset)
> {
> - struct pcie_port *pp = &ks_pcie->pp;
> + struct pcie_port *pp = &keystone->pp;
> u32 pending;
> int virq;
>
> - pending = readl(ks_pcie->va_app_base + IRQ_STATUS + (offset << 4));
> + pending = readl(keystone->va_app_base + IRQ_STATUS + (offset << 4));
>
> if (BIT(0) & pending) {
> - virq = irq_linear_revmap(ks_pcie->legacy_irq_domain, offset);
> + virq = irq_linear_revmap(keystone->legacy_irq_domain, offset);
> dev_dbg(pp->dev, ": irq: irq_offset %d, virq %d\n", offset,
> virq);
> generic_handle_irq(virq);
> }
>
> /* EOI the INTx interrupt */
> - writel(offset, ks_pcie->va_app_base + IRQ_EOI);
> + writel(offset, keystone->va_app_base + IRQ_EOI);
> }
>
> void ks_dw_pcie_enable_error_irq(void __iomem *reg_base)
> @@ -352,39 +352,39 @@ static void ks_dw_pcie_clear_dbi_mode(void __iomem *reg_virt)
> } while (val & DBI_CS2_EN_VAL);
> }
>
> -void ks_dw_pcie_setup_rc_app_regs(struct keystone_pcie *ks_pcie)
> +void ks_dw_pcie_setup_rc_app_regs(struct keystone_pcie *keystone)
> {
> - struct pcie_port *pp = &ks_pcie->pp;
> + struct pcie_port *pp = &keystone->pp;
> u32 start = pp->mem->start, end = pp->mem->end;
> int i, tr_size;
>
> /* Disable BARs for inbound access */
> - ks_dw_pcie_set_dbi_mode(ks_pcie->va_app_base);
> + ks_dw_pcie_set_dbi_mode(keystone->va_app_base);
> writel(0, pp->dbi_base + PCI_BASE_ADDRESS_0);
> writel(0, pp->dbi_base + PCI_BASE_ADDRESS_1);
> - ks_dw_pcie_clear_dbi_mode(ks_pcie->va_app_base);
> + ks_dw_pcie_clear_dbi_mode(keystone->va_app_base);
>
> /* Set outbound translation size per window division */
> - writel(CFG_PCIM_WIN_SZ_IDX & 0x7, ks_pcie->va_app_base + OB_SIZE);
> + writel(CFG_PCIM_WIN_SZ_IDX & 0x7, keystone->va_app_base + OB_SIZE);
>
> tr_size = (1 << (CFG_PCIM_WIN_SZ_IDX & 0x7)) * SZ_1M;
>
> /* Using Direct 1:1 mapping of RC <-> PCI memory space */
> for (i = 0; (i < CFG_PCIM_WIN_CNT) && (start < end); i++) {
> - writel(start | 1, ks_pcie->va_app_base + OB_OFFSET_INDEX(i));
> - writel(0, ks_pcie->va_app_base + OB_OFFSET_HI(i));
> + writel(start | 1, keystone->va_app_base + OB_OFFSET_INDEX(i));
> + writel(0, keystone->va_app_base + OB_OFFSET_HI(i));
> start += tr_size;
> }
>
> /* Enable OB translation */
> - writel(OB_XLAT_EN_VAL | readl(ks_pcie->va_app_base + CMD_STATUS),
> - ks_pcie->va_app_base + CMD_STATUS);
> + writel(OB_XLAT_EN_VAL | readl(keystone->va_app_base + CMD_STATUS),
> + keystone->va_app_base + CMD_STATUS);
> }
>
> /**
> * ks_pcie_cfg_setup() - Set up configuration space address for a device
> *
> - * @ks_pcie: ptr to keystone_pcie structure
> + * @keystone: ptr to keystone_pcie structure
> * @bus: Bus number the device is residing on
> * @devfn: device, function number info
> *
> @@ -398,11 +398,11 @@ void ks_dw_pcie_setup_rc_app_regs(struct keystone_pcie *ks_pcie)
> * we will do TYPE 0 access as it will be on our secondary bus (logical).
> * CFG_SETUP is needed only for remote configuration access.
> */
> -static void __iomem *ks_pcie_cfg_setup(struct keystone_pcie *ks_pcie, u8 bus,
> +static void __iomem *ks_pcie_cfg_setup(struct keystone_pcie *keystone, u8 bus,
> unsigned int devfn)
> {
> u8 device = PCI_SLOT(devfn), function = PCI_FUNC(devfn);
> - struct pcie_port *pp = &ks_pcie->pp;
> + struct pcie_port *pp = &keystone->pp;
> u32 regval;
>
> if (bus == 0)
> @@ -418,18 +418,18 @@ static void __iomem *ks_pcie_cfg_setup(struct keystone_pcie *ks_pcie, u8 bus,
> if (bus != 1)
> regval |= BIT(24);
>
> - writel(regval, ks_pcie->va_app_base + CFG_SETUP);
> + writel(regval, keystone->va_app_base + CFG_SETUP);
> return pp->va_cfg0_base;
> }
>
> int ks_dw_pcie_rd_other_conf(struct pcie_port *pp, struct pci_bus *bus,
> unsigned int devfn, int where, int size, u32 *val)
> {
> - struct keystone_pcie *ks_pcie = to_keystone_pcie(pp);
> + struct keystone_pcie *keystone = to_keystone_pcie(pp);
> u8 bus_num = bus->number;
> void __iomem *addr;
>
> - addr = ks_pcie_cfg_setup(ks_pcie, bus_num, devfn);
> + addr = ks_pcie_cfg_setup(keystone, bus_num, devfn);
>
> return dw_pcie_cfg_read(addr + where, size, val);
> }
> @@ -437,11 +437,11 @@ int ks_dw_pcie_rd_other_conf(struct pcie_port *pp, struct pci_bus *bus,
> int ks_dw_pcie_wr_other_conf(struct pcie_port *pp, struct pci_bus *bus,
> unsigned int devfn, int where, int size, u32 val)
> {
> - struct keystone_pcie *ks_pcie = to_keystone_pcie(pp);
> + struct keystone_pcie *keystone = to_keystone_pcie(pp);
> u8 bus_num = bus->number;
> void __iomem *addr;
>
> - addr = ks_pcie_cfg_setup(ks_pcie, bus_num, devfn);
> + addr = ks_pcie_cfg_setup(keystone, bus_num, devfn);
>
> return dw_pcie_cfg_write(addr + where, size, val);
> }
> @@ -453,22 +453,22 @@ int ks_dw_pcie_wr_other_conf(struct pcie_port *pp, struct pci_bus *bus,
> */
> void ks_dw_pcie_v3_65_scan_bus(struct pcie_port *pp)
> {
> - struct keystone_pcie *ks_pcie = to_keystone_pcie(pp);
> + struct keystone_pcie *keystone = to_keystone_pcie(pp);
>
> /* Configure and set up BAR0 */
> - ks_dw_pcie_set_dbi_mode(ks_pcie->va_app_base);
> + ks_dw_pcie_set_dbi_mode(keystone->va_app_base);
>
> /* Enable BAR0 */
> writel(1, pp->dbi_base + PCI_BASE_ADDRESS_0);
> writel(SZ_4K - 1, pp->dbi_base + PCI_BASE_ADDRESS_0);
>
> - ks_dw_pcie_clear_dbi_mode(ks_pcie->va_app_base);
> + ks_dw_pcie_clear_dbi_mode(keystone->va_app_base);
>
> /*
> * For BAR0, just setting bus address for inbound writes (MSI) should
> * be sufficient. Use physical address to avoid any conflicts.
> */
> - writel(ks_pcie->app.start, pp->dbi_base + PCI_BASE_ADDRESS_0);
> + writel(keystone->app.start, pp->dbi_base + PCI_BASE_ADDRESS_0);
> }
>
> /**
> @@ -481,18 +481,18 @@ int ks_dw_pcie_link_up(struct pcie_port *pp)
> return (val & LTSSM_STATE_MASK) == LTSSM_STATE_L0;
> }
>
> -void ks_dw_pcie_initiate_link_train(struct keystone_pcie *ks_pcie)
> +void ks_dw_pcie_initiate_link_train(struct keystone_pcie *keystone)
> {
> u32 val;
>
> /* Disable Link training */
> - val = readl(ks_pcie->va_app_base + CMD_STATUS);
> + val = readl(keystone->va_app_base + CMD_STATUS);
> val &= ~LTSSM_EN_VAL;
> - writel(LTSSM_EN_VAL | val, ks_pcie->va_app_base + CMD_STATUS);
> + writel(LTSSM_EN_VAL | val, keystone->va_app_base + CMD_STATUS);
>
> /* Initiate Link Training */
> - val = readl(ks_pcie->va_app_base + CMD_STATUS);
> - writel(LTSSM_EN_VAL | val, ks_pcie->va_app_base + CMD_STATUS);
> + val = readl(keystone->va_app_base + CMD_STATUS);
> + writel(LTSSM_EN_VAL | val, keystone->va_app_base + CMD_STATUS);
> }
>
> /**
> @@ -502,10 +502,10 @@ void ks_dw_pcie_initiate_link_train(struct keystone_pcie *ks_pcie)
> * and call dw_pcie_v3_65_host_init() API to initialize the Keystone
> * PCI host controller.
> */
> -int __init ks_dw_pcie_host_init(struct keystone_pcie *ks_pcie,
> +int __init ks_dw_pcie_host_init(struct keystone_pcie *keystone,
> struct device_node *msi_intc_np)
> {
> - struct pcie_port *pp = &ks_pcie->pp;
> + struct pcie_port *pp = &keystone->pp;
> struct platform_device *pdev = to_platform_device(pp->dev);
> struct resource *res;
>
> @@ -524,19 +524,19 @@ int __init ks_dw_pcie_host_init(struct keystone_pcie *ks_pcie,
>
> /* Index 1 is the application reg. space address */
> res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
> - ks_pcie->va_app_base = devm_ioremap_resource(pp->dev, res);
> - if (IS_ERR(ks_pcie->va_app_base))
> - return PTR_ERR(ks_pcie->va_app_base);
> + keystone->va_app_base = devm_ioremap_resource(pp->dev, res);
> + if (IS_ERR(keystone->va_app_base))
> + return PTR_ERR(keystone->va_app_base);
>
> - ks_pcie->app = *res;
> + keystone->app = *res;
>
> /* Create legacy IRQ domain */
> - ks_pcie->legacy_irq_domain =
> - irq_domain_add_linear(ks_pcie->legacy_intc_np,
> + keystone->legacy_irq_domain =
> + irq_domain_add_linear(keystone->legacy_intc_np,
> MAX_LEGACY_IRQS,
> &ks_dw_pcie_legacy_irq_domain_ops,
> NULL);
> - if (!ks_pcie->legacy_irq_domain) {
> + if (!keystone->legacy_irq_domain) {
> dev_err(pp->dev, "Failed to add irq domain for legacy irqs\n");
> return -EINVAL;
> }
> diff --git a/drivers/pci/host/pci-keystone.c b/drivers/pci/host/pci-keystone.c
> index 82b461b..55b2be7 100644
> --- a/drivers/pci/host/pci-keystone.c
> +++ b/drivers/pci/host/pci-keystone.c
> @@ -86,9 +86,9 @@ static void quirk_limit_mrrs(struct pci_dev *dev)
> }
> DECLARE_PCI_FIXUP_ENABLE(PCI_ANY_ID, PCI_ANY_ID, quirk_limit_mrrs);
>
> -static int ks_pcie_establish_link(struct keystone_pcie *ks_pcie)
> +static int ks_pcie_establish_link(struct keystone_pcie *keystone)
> {
> - struct pcie_port *pp = &ks_pcie->pp;
> + struct pcie_port *pp = &keystone->pp;
> unsigned int retries;
>
> dw_pcie_setup_rc(pp);
> @@ -100,7 +100,7 @@ static int ks_pcie_establish_link(struct keystone_pcie *ks_pcie)
>
> /* check if the link is up or not */
> for (retries = 0; retries < 5; retries++) {
> - ks_dw_pcie_initiate_link_train(ks_pcie);
> + ks_dw_pcie_initiate_link_train(keystone);
> if (!dw_pcie_wait_for_link(pp))
> return 0;
> }
> @@ -112,9 +112,9 @@ static int ks_pcie_establish_link(struct keystone_pcie *ks_pcie)
> static void ks_pcie_msi_irq_handler(struct irq_desc *desc)
> {
> unsigned int irq = irq_desc_get_irq(desc);
> - struct keystone_pcie *ks_pcie = irq_desc_get_handler_data(desc);
> - u32 offset = irq - ks_pcie->msi_host_irqs[0];
> - struct pcie_port *pp = &ks_pcie->pp;
> + struct keystone_pcie *keystone = irq_desc_get_handler_data(desc);
> + u32 offset = irq - keystone->msi_host_irqs[0];
> + struct pcie_port *pp = &keystone->pp;
> struct irq_chip *chip = irq_desc_get_chip(desc);
>
> dev_dbg(pp->dev, "%s, irq %d\n", __func__, irq);
> @@ -125,7 +125,7 @@ static void ks_pcie_msi_irq_handler(struct irq_desc *desc)
> * ack operation.
> */
> chained_irq_enter(chip, desc);
> - ks_dw_pcie_handle_msi_irq(ks_pcie, offset);
> + ks_dw_pcie_handle_msi_irq(keystone, offset);
> chained_irq_exit(chip, desc);
> }
>
> @@ -140,9 +140,9 @@ static void ks_pcie_msi_irq_handler(struct irq_desc *desc)
> static void ks_pcie_legacy_irq_handler(struct irq_desc *desc)
> {
> unsigned int irq = irq_desc_get_irq(desc);
> - struct keystone_pcie *ks_pcie = irq_desc_get_handler_data(desc);
> - struct pcie_port *pp = &ks_pcie->pp;
> - u32 irq_offset = irq - ks_pcie->legacy_host_irqs[0];
> + struct keystone_pcie *keystone = irq_desc_get_handler_data(desc);
> + struct pcie_port *pp = &keystone->pp;
> + u32 irq_offset = irq - keystone->legacy_host_irqs[0];
> struct irq_chip *chip = irq_desc_get_chip(desc);
>
> dev_dbg(pp->dev, ": Handling legacy irq %d\n", irq);
> @@ -153,28 +153,28 @@ static void ks_pcie_legacy_irq_handler(struct irq_desc *desc)
> * ack operation.
> */
> chained_irq_enter(chip, desc);
> - ks_dw_pcie_handle_legacy_irq(ks_pcie, irq_offset);
> + ks_dw_pcie_handle_legacy_irq(keystone, irq_offset);
> chained_irq_exit(chip, desc);
> }
>
> -static int ks_pcie_get_irq_controller_info(struct keystone_pcie *ks_pcie,
> +static int ks_pcie_get_irq_controller_info(struct keystone_pcie *keystone,
> char *controller, int *num_irqs)
> {
> int temp, max_host_irqs, legacy = 1, *host_irqs;
> - struct device *dev = ks_pcie->pp.dev;
> + struct device *dev = keystone->pp.dev;
> struct device_node *np_pcie = dev->of_node, **np_temp;
>
> if (!strcmp(controller, "msi-interrupt-controller"))
> legacy = 0;
>
> if (legacy) {
> - np_temp = &ks_pcie->legacy_intc_np;
> + np_temp = &keystone->legacy_intc_np;
> max_host_irqs = MAX_LEGACY_HOST_IRQS;
> - host_irqs = &ks_pcie->legacy_host_irqs[0];
> + host_irqs = &keystone->legacy_host_irqs[0];
> } else {
> - np_temp = &ks_pcie->msi_intc_np;
> + np_temp = &keystone->msi_intc_np;
> max_host_irqs = MAX_MSI_HOST_IRQS;
> - host_irqs = &ks_pcie->msi_host_irqs[0];
> + host_irqs = &keystone->msi_host_irqs[0];
> }
>
> /* interrupt controller is in a child node */
> @@ -212,29 +212,29 @@ static int ks_pcie_get_irq_controller_info(struct keystone_pcie *ks_pcie,
> return -EINVAL;
> }
>
> -static void ks_pcie_setup_interrupts(struct keystone_pcie *ks_pcie)
> +static void ks_pcie_setup_interrupts(struct keystone_pcie *keystone)
> {
> int i;
>
> /* Legacy IRQ */
> - for (i = 0; i < ks_pcie->num_legacy_host_irqs; i++) {
> - irq_set_chained_handler_and_data(ks_pcie->legacy_host_irqs[i],
> + for (i = 0; i < keystone->num_legacy_host_irqs; i++) {
> + irq_set_chained_handler_and_data(keystone->legacy_host_irqs[i],
> ks_pcie_legacy_irq_handler,
> - ks_pcie);
> + keystone);
> }
> - ks_dw_pcie_enable_legacy_irqs(ks_pcie);
> + ks_dw_pcie_enable_legacy_irqs(keystone);
>
> /* MSI IRQ */
> if (IS_ENABLED(CONFIG_PCI_MSI)) {
> - for (i = 0; i < ks_pcie->num_msi_host_irqs; i++) {
> - irq_set_chained_handler_and_data(ks_pcie->msi_host_irqs[i],
> + for (i = 0; i < keystone->num_msi_host_irqs; i++) {
> + irq_set_chained_handler_and_data(keystone->msi_host_irqs[i],
> ks_pcie_msi_irq_handler,
> - ks_pcie);
> + keystone);
> }
> }
>
> - if (ks_pcie->error_irq > 0)
> - ks_dw_pcie_enable_error_irq(ks_pcie->va_app_base);
> + if (keystone->error_irq > 0)
> + ks_dw_pcie_enable_error_irq(keystone->va_app_base);
> }
>
> /*
> @@ -259,17 +259,17 @@ static int keystone_pcie_fault(unsigned long addr, unsigned int fsr,
>
> static void __init ks_pcie_host_init(struct pcie_port *pp)
> {
> - struct keystone_pcie *ks_pcie = to_keystone_pcie(pp);
> + struct keystone_pcie *keystone = to_keystone_pcie(pp);
> u32 val;
>
> - ks_pcie_establish_link(ks_pcie);
> - ks_dw_pcie_setup_rc_app_regs(ks_pcie);
> - ks_pcie_setup_interrupts(ks_pcie);
> + ks_pcie_establish_link(keystone);
> + ks_dw_pcie_setup_rc_app_regs(keystone);
> + ks_pcie_setup_interrupts(keystone);
> writew(PCI_IO_RANGE_TYPE_32 | (PCI_IO_RANGE_TYPE_32 << 8),
> pp->dbi_base + PCI_IO_BASE);
>
> /* update the Vendor ID */
> - writew(ks_pcie->device_id, pp->dbi_base + PCI_DEVICE_ID);
> + writew(keystone->device_id, pp->dbi_base + PCI_DEVICE_ID);
>
> /* update the DEV_STAT_CTRL to publish right mrrs */
> val = readl(pp->dbi_base + PCIE_CAP_BASE + PCI_EXP_DEVCTL);
> @@ -300,28 +300,28 @@ static struct pcie_host_ops keystone_pcie_host_ops = {
>
> static irqreturn_t pcie_err_irq_handler(int irq, void *priv)
> {
> - struct keystone_pcie *ks_pcie = priv;
> + struct keystone_pcie *keystone = priv;
>
> - return ks_dw_pcie_handle_error_irq(ks_pcie->pp.dev,
> - ks_pcie->va_app_base);
> + return ks_dw_pcie_handle_error_irq(keystone->pp.dev,
> + keystone->va_app_base);
> }
>
> -static int __init ks_add_pcie_port(struct keystone_pcie *ks_pcie,
> +static int __init ks_add_pcie_port(struct keystone_pcie *keystone,
> struct platform_device *pdev)
> {
> - struct pcie_port *pp = &ks_pcie->pp;
> + struct pcie_port *pp = &keystone->pp;
> int ret;
>
> - ret = ks_pcie_get_irq_controller_info(ks_pcie,
> + ret = ks_pcie_get_irq_controller_info(keystone,
> "legacy-interrupt-controller",
> - &ks_pcie->num_legacy_host_irqs);
> + &keystone->num_legacy_host_irqs);
> if (ret)
> return ret;
>
> if (IS_ENABLED(CONFIG_PCI_MSI)) {
> - ret = ks_pcie_get_irq_controller_info(ks_pcie,
> + ret = ks_pcie_get_irq_controller_info(keystone,
> "msi-interrupt-controller",
> - &ks_pcie->num_msi_host_irqs);
> + &keystone->num_msi_host_irqs);
> if (ret)
> return ret;
> }
> @@ -330,22 +330,22 @@ static int __init ks_add_pcie_port(struct keystone_pcie *ks_pcie,
> * Index 0 is the platform interrupt for error interrupt
> * from RC. This is optional.
> */
> - ks_pcie->error_irq = irq_of_parse_and_map(ks_pcie->np, 0);
> - if (ks_pcie->error_irq <= 0)
> + keystone->error_irq = irq_of_parse_and_map(keystone->np, 0);
> + if (keystone->error_irq <= 0)
> dev_info(&pdev->dev, "no error IRQ defined\n");
> else {
> - ret = request_irq(ks_pcie->error_irq, pcie_err_irq_handler,
> - IRQF_SHARED, "pcie-error-irq", ks_pcie);
> + ret = request_irq(keystone->error_irq, pcie_err_irq_handler,
> + IRQF_SHARED, "pcie-error-irq", keystone);
> if (ret < 0) {
> dev_err(&pdev->dev, "failed to request error IRQ %d\n",
> - ks_pcie->error_irq);
> + keystone->error_irq);
> return ret;
> }
> }
>
> pp->root_bus_nr = -1;
> pp->ops = &keystone_pcie_host_ops;
> - ret = ks_dw_pcie_host_init(ks_pcie, ks_pcie->msi_intc_np);
> + ret = ks_dw_pcie_host_init(keystone, keystone->msi_intc_np);
> if (ret) {
> dev_err(&pdev->dev, "failed to initialize host\n");
> return ret;
> @@ -364,9 +364,9 @@ static const struct of_device_id ks_pcie_of_match[] = {
>
> static int __exit ks_pcie_remove(struct platform_device *pdev)
> {
> - struct keystone_pcie *ks_pcie = platform_get_drvdata(pdev);
> + struct keystone_pcie *keystone = platform_get_drvdata(pdev);
>
> - clk_disable_unprepare(ks_pcie->clk);
> + clk_disable_unprepare(keystone->clk);
>
> return 0;
> }
> @@ -374,19 +374,18 @@ static int __exit ks_pcie_remove(struct platform_device *pdev)
> static int __init ks_pcie_probe(struct platform_device *pdev)
> {
> struct device *dev = &pdev->dev;
> - struct keystone_pcie *ks_pcie;
> + struct keystone_pcie *keystone;
> struct pcie_port *pp;
> struct resource *res;
> void __iomem *reg_p;
> struct phy *phy;
> int ret;
>
> - ks_pcie = devm_kzalloc(&pdev->dev, sizeof(*ks_pcie),
> - GFP_KERNEL);
> - if (!ks_pcie)
> + keystone = devm_kzalloc(&pdev->dev, sizeof(*keystone), GFP_KERNEL);
> + if (!keystone)
> return -ENOMEM;
>
> - pp = &ks_pcie->pp;
> + pp = &keystone->pp;
>
> /* initialize SerDes Phy if present */
> phy = devm_phy_get(dev, "pcie-phy");
> @@ -404,29 +403,29 @@ static int __init ks_pcie_probe(struct platform_device *pdev)
> reg_p = devm_ioremap_resource(dev, res);
> if (IS_ERR(reg_p))
> return PTR_ERR(reg_p);
> - ks_pcie->device_id = readl(reg_p) >> 16;
> + keystone->device_id = readl(reg_p) >> 16;
> devm_iounmap(dev, reg_p);
> devm_release_mem_region(dev, res->start, resource_size(res));
>
> pp->dev = dev;
> - ks_pcie->np = dev->of_node;
> - platform_set_drvdata(pdev, ks_pcie);
> - ks_pcie->clk = devm_clk_get(dev, "pcie");
> - if (IS_ERR(ks_pcie->clk)) {
> + keystone->np = dev->of_node;
> + platform_set_drvdata(pdev, keystone);
> + keystone->clk = devm_clk_get(dev, "pcie");
> + if (IS_ERR(keystone->clk)) {
> dev_err(dev, "Failed to get pcie rc clock\n");
> - return PTR_ERR(ks_pcie->clk);
> + return PTR_ERR(keystone->clk);
> }
> - ret = clk_prepare_enable(ks_pcie->clk);
> + ret = clk_prepare_enable(keystone->clk);
> if (ret)
> return ret;
>
> - ret = ks_add_pcie_port(ks_pcie, pdev);
> + ret = ks_add_pcie_port(keystone, pdev);
> if (ret < 0)
> goto fail_clk;
>
> return 0;
> fail_clk:
> - clk_disable_unprepare(ks_pcie->clk);
> + clk_disable_unprepare(keystone->clk);
>
> return ret;
> }
> diff --git a/drivers/pci/host/pci-keystone.h b/drivers/pci/host/pci-keystone.h
> index a5b0cb2..379213c 100644
> --- a/drivers/pci/host/pci-keystone.h
> +++ b/drivers/pci/host/pci-keystone.h
> @@ -39,24 +39,24 @@ struct keystone_pcie {
> };
>
> /* Keystone DW specific MSI controller APIs/definitions */
> -void ks_dw_pcie_handle_msi_irq(struct keystone_pcie *ks_pcie, int offset);
> +void ks_dw_pcie_handle_msi_irq(struct keystone_pcie *keystone, int offset);
> phys_addr_t ks_dw_pcie_get_msi_addr(struct pcie_port *pp);
>
> /* Keystone specific PCI controller APIs */
> -void ks_dw_pcie_enable_legacy_irqs(struct keystone_pcie *ks_pcie);
> -void ks_dw_pcie_handle_legacy_irq(struct keystone_pcie *ks_pcie, int offset);
> +void ks_dw_pcie_enable_legacy_irqs(struct keystone_pcie *keystone);
> +void ks_dw_pcie_handle_legacy_irq(struct keystone_pcie *keystone, int offset);
> void ks_dw_pcie_enable_error_irq(void __iomem *reg_base);
> irqreturn_t ks_dw_pcie_handle_error_irq(struct device *dev,
> void __iomem *reg_base);
> -int ks_dw_pcie_host_init(struct keystone_pcie *ks_pcie,
> +int ks_dw_pcie_host_init(struct keystone_pcie *keystone,
> struct device_node *msi_intc_np);
> int ks_dw_pcie_wr_other_conf(struct pcie_port *pp, struct pci_bus *bus,
> unsigned int devfn, int where, int size, u32 val);
> int ks_dw_pcie_rd_other_conf(struct pcie_port *pp, struct pci_bus *bus,
> unsigned int devfn, int where, int size, u32 *val);
> -void ks_dw_pcie_setup_rc_app_regs(struct keystone_pcie *ks_pcie);
> +void ks_dw_pcie_setup_rc_app_regs(struct keystone_pcie *keystone);
> int ks_dw_pcie_link_up(struct pcie_port *pp);
> -void ks_dw_pcie_initiate_link_train(struct keystone_pcie *ks_pcie);
> +void ks_dw_pcie_initiate_link_train(struct keystone_pcie *keystone);
> void ks_dw_pcie_msi_set_irq(struct pcie_port *pp, int irq);
> void ks_dw_pcie_msi_clear_irq(struct pcie_port *pp, int irq);
> void ks_dw_pcie_v3_65_scan_bus(struct pcie_port *pp);
>
--
Murali Karicheri
Linux Kernel, Keystone
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH 1/6] PCI: keystone: Name private struct pointer "keystone" consistently
2016-10-07 16:53 ` [PATCH 1/6] PCI: keystone: Name private struct pointer "keystone" consistently Murali Karicheri
@ 2016-10-07 16:56 ` Murali Karicheri
2016-10-07 18:09 ` Bjorn Helgaas
1 sibling, 0 replies; 9+ messages in thread
From: Murali Karicheri @ 2016-10-07 16:56 UTC (permalink / raw)
To: Bjorn Helgaas; +Cc: linux-pci
On 10/07/2016 12:53 PM, Murali Karicheri wrote:
> On 10/07/2016 12:40 PM, Bjorn Helgaas wrote:
>> Use a device-specific name, "keystone", for struct keystone_pcie pointers
> referring to keystone pcie as keystone is not right. keystone_pcie make sense.
> To use a short name ks_pcie was used. So what is wrong with the naming?
> I believe this patch is unnecessary.
Forgot to add. keystone is the SoC name.
>
> Murali
>> to hint that this is device-specific information. No functional change
>> intended.
>>
>> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
>> ---
>> drivers/pci/host/pci-keystone-dw.c | 122 ++++++++++++++++++-----------------
>> drivers/pci/host/pci-keystone.c | 125 ++++++++++++++++++------------------
>> drivers/pci/host/pci-keystone.h | 12 ++-
>> 3 files changed, 129 insertions(+), 130 deletions(-)
>>
>> diff --git a/drivers/pci/host/pci-keystone-dw.c b/drivers/pci/host/pci-keystone-dw.c
>> index 4151509..d09e3c6 100644
>> --- a/drivers/pci/host/pci-keystone-dw.c
>> +++ b/drivers/pci/host/pci-keystone-dw.c
>> @@ -83,18 +83,18 @@ static inline void update_reg_offset_bit_pos(u32 offset, u32 *reg_offset,
>>
>> phys_addr_t ks_dw_pcie_get_msi_addr(struct pcie_port *pp)
>> {
>> - struct keystone_pcie *ks_pcie = to_keystone_pcie(pp);
>> + struct keystone_pcie *keystone = to_keystone_pcie(pp);
>>
>> - return ks_pcie->app.start + MSI_IRQ;
>> + return keystone->app.start + MSI_IRQ;
>> }
>>
>> -void ks_dw_pcie_handle_msi_irq(struct keystone_pcie *ks_pcie, int offset)
>> +void ks_dw_pcie_handle_msi_irq(struct keystone_pcie *keystone, int offset)
>> {
>> - struct pcie_port *pp = &ks_pcie->pp;
>> + struct pcie_port *pp = &keystone->pp;
>> u32 pending, vector;
>> int src, virq;
>>
>> - pending = readl(ks_pcie->va_app_base + MSI0_IRQ_STATUS + (offset << 4));
>> + pending = readl(keystone->va_app_base + MSI0_IRQ_STATUS + (offset << 4));
>>
>> /*
>> * MSI0 status bit 0-3 shows vectors 0, 8, 16, 24, MSI1 status bit
>> @@ -114,51 +114,51 @@ void ks_dw_pcie_handle_msi_irq(struct keystone_pcie *ks_pcie, int offset)
>> static void ks_dw_pcie_msi_irq_ack(struct irq_data *d)
>> {
>> u32 offset, reg_offset, bit_pos;
>> - struct keystone_pcie *ks_pcie;
>> + struct keystone_pcie *keystone;
>> struct msi_desc *msi;
>> struct pcie_port *pp;
>>
>> msi = irq_data_get_msi_desc(d);
>> pp = (struct pcie_port *) msi_desc_to_pci_sysdata(msi);
>> - ks_pcie = to_keystone_pcie(pp);
>> + keystone = to_keystone_pcie(pp);
>> offset = d->irq - irq_linear_revmap(pp->irq_domain, 0);
>> update_reg_offset_bit_pos(offset, ®_offset, &bit_pos);
>>
>> writel(BIT(bit_pos),
>> - ks_pcie->va_app_base + MSI0_IRQ_STATUS + (reg_offset << 4));
>> - writel(reg_offset + MSI_IRQ_OFFSET, ks_pcie->va_app_base + IRQ_EOI);
>> + keystone->va_app_base + MSI0_IRQ_STATUS + (reg_offset << 4));
>> + writel(reg_offset + MSI_IRQ_OFFSET, keystone->va_app_base + IRQ_EOI);
>> }
>>
>> void ks_dw_pcie_msi_set_irq(struct pcie_port *pp, int irq)
>> {
>> u32 reg_offset, bit_pos;
>> - struct keystone_pcie *ks_pcie = to_keystone_pcie(pp);
>> + struct keystone_pcie *keystone = to_keystone_pcie(pp);
>>
>> update_reg_offset_bit_pos(irq, ®_offset, &bit_pos);
>> writel(BIT(bit_pos),
>> - ks_pcie->va_app_base + MSI0_IRQ_ENABLE_SET + (reg_offset << 4));
>> + keystone->va_app_base + MSI0_IRQ_ENABLE_SET + (reg_offset << 4));
>> }
>>
>> void ks_dw_pcie_msi_clear_irq(struct pcie_port *pp, int irq)
>> {
>> u32 reg_offset, bit_pos;
>> - struct keystone_pcie *ks_pcie = to_keystone_pcie(pp);
>> + struct keystone_pcie *keystone = to_keystone_pcie(pp);
>>
>> update_reg_offset_bit_pos(irq, ®_offset, &bit_pos);
>> writel(BIT(bit_pos),
>> - ks_pcie->va_app_base + MSI0_IRQ_ENABLE_CLR + (reg_offset << 4));
>> + keystone->va_app_base + MSI0_IRQ_ENABLE_CLR + (reg_offset << 4));
>> }
>>
>> static void ks_dw_pcie_msi_irq_mask(struct irq_data *d)
>> {
>> - struct keystone_pcie *ks_pcie;
>> + struct keystone_pcie *keystone;
>> struct msi_desc *msi;
>> struct pcie_port *pp;
>> u32 offset;
>>
>> msi = irq_data_get_msi_desc(d);
>> pp = (struct pcie_port *) msi_desc_to_pci_sysdata(msi);
>> - ks_pcie = to_keystone_pcie(pp);
>> + keystone = to_keystone_pcie(pp);
>> offset = d->irq - irq_linear_revmap(pp->irq_domain, 0);
>>
>> /* Mask the end point if PVM implemented */
>> @@ -172,14 +172,14 @@ static void ks_dw_pcie_msi_irq_mask(struct irq_data *d)
>>
>> static void ks_dw_pcie_msi_irq_unmask(struct irq_data *d)
>> {
>> - struct keystone_pcie *ks_pcie;
>> + struct keystone_pcie *keystone;
>> struct msi_desc *msi;
>> struct pcie_port *pp;
>> u32 offset;
>>
>> msi = irq_data_get_msi_desc(d);
>> pp = (struct pcie_port *) msi_desc_to_pci_sysdata(msi);
>> - ks_pcie = to_keystone_pcie(pp);
>> + keystone = to_keystone_pcie(pp);
>> offset = d->irq - irq_linear_revmap(pp->irq_domain, 0);
>>
>> /* Mask the end point if PVM implemented */
>> @@ -214,10 +214,10 @@ static const struct irq_domain_ops ks_dw_pcie_msi_domain_ops = {
>>
>> int ks_dw_pcie_msi_host_init(struct pcie_port *pp, struct msi_controller *chip)
>> {
>> - struct keystone_pcie *ks_pcie = to_keystone_pcie(pp);
>> + struct keystone_pcie *keystone = to_keystone_pcie(pp);
>> int i;
>>
>> - pp->irq_domain = irq_domain_add_linear(ks_pcie->msi_intc_np,
>> + pp->irq_domain = irq_domain_add_linear(keystone->msi_intc_np,
>> MAX_MSI_IRQS,
>> &ks_dw_pcie_msi_domain_ops,
>> chip);
>> @@ -232,31 +232,31 @@ int ks_dw_pcie_msi_host_init(struct pcie_port *pp, struct msi_controller *chip)
>> return 0;
>> }
>>
>> -void ks_dw_pcie_enable_legacy_irqs(struct keystone_pcie *ks_pcie)
>> +void ks_dw_pcie_enable_legacy_irqs(struct keystone_pcie *keystone)
>> {
>> int i;
>>
>> for (i = 0; i < MAX_LEGACY_IRQS; i++)
>> - writel(0x1, ks_pcie->va_app_base + IRQ_ENABLE_SET + (i << 4));
>> + writel(0x1, keystone->va_app_base + IRQ_ENABLE_SET + (i << 4));
>> }
>>
>> -void ks_dw_pcie_handle_legacy_irq(struct keystone_pcie *ks_pcie, int offset)
>> +void ks_dw_pcie_handle_legacy_irq(struct keystone_pcie *keystone, int offset)
>> {
>> - struct pcie_port *pp = &ks_pcie->pp;
>> + struct pcie_port *pp = &keystone->pp;
>> u32 pending;
>> int virq;
>>
>> - pending = readl(ks_pcie->va_app_base + IRQ_STATUS + (offset << 4));
>> + pending = readl(keystone->va_app_base + IRQ_STATUS + (offset << 4));
>>
>> if (BIT(0) & pending) {
>> - virq = irq_linear_revmap(ks_pcie->legacy_irq_domain, offset);
>> + virq = irq_linear_revmap(keystone->legacy_irq_domain, offset);
>> dev_dbg(pp->dev, ": irq: irq_offset %d, virq %d\n", offset,
>> virq);
>> generic_handle_irq(virq);
>> }
>>
>> /* EOI the INTx interrupt */
>> - writel(offset, ks_pcie->va_app_base + IRQ_EOI);
>> + writel(offset, keystone->va_app_base + IRQ_EOI);
>> }
>>
>> void ks_dw_pcie_enable_error_irq(void __iomem *reg_base)
>> @@ -352,39 +352,39 @@ static void ks_dw_pcie_clear_dbi_mode(void __iomem *reg_virt)
>> } while (val & DBI_CS2_EN_VAL);
>> }
>>
>> -void ks_dw_pcie_setup_rc_app_regs(struct keystone_pcie *ks_pcie)
>> +void ks_dw_pcie_setup_rc_app_regs(struct keystone_pcie *keystone)
>> {
>> - struct pcie_port *pp = &ks_pcie->pp;
>> + struct pcie_port *pp = &keystone->pp;
>> u32 start = pp->mem->start, end = pp->mem->end;
>> int i, tr_size;
>>
>> /* Disable BARs for inbound access */
>> - ks_dw_pcie_set_dbi_mode(ks_pcie->va_app_base);
>> + ks_dw_pcie_set_dbi_mode(keystone->va_app_base);
>> writel(0, pp->dbi_base + PCI_BASE_ADDRESS_0);
>> writel(0, pp->dbi_base + PCI_BASE_ADDRESS_1);
>> - ks_dw_pcie_clear_dbi_mode(ks_pcie->va_app_base);
>> + ks_dw_pcie_clear_dbi_mode(keystone->va_app_base);
>>
>> /* Set outbound translation size per window division */
>> - writel(CFG_PCIM_WIN_SZ_IDX & 0x7, ks_pcie->va_app_base + OB_SIZE);
>> + writel(CFG_PCIM_WIN_SZ_IDX & 0x7, keystone->va_app_base + OB_SIZE);
>>
>> tr_size = (1 << (CFG_PCIM_WIN_SZ_IDX & 0x7)) * SZ_1M;
>>
>> /* Using Direct 1:1 mapping of RC <-> PCI memory space */
>> for (i = 0; (i < CFG_PCIM_WIN_CNT) && (start < end); i++) {
>> - writel(start | 1, ks_pcie->va_app_base + OB_OFFSET_INDEX(i));
>> - writel(0, ks_pcie->va_app_base + OB_OFFSET_HI(i));
>> + writel(start | 1, keystone->va_app_base + OB_OFFSET_INDEX(i));
>> + writel(0, keystone->va_app_base + OB_OFFSET_HI(i));
>> start += tr_size;
>> }
>>
>> /* Enable OB translation */
>> - writel(OB_XLAT_EN_VAL | readl(ks_pcie->va_app_base + CMD_STATUS),
>> - ks_pcie->va_app_base + CMD_STATUS);
>> + writel(OB_XLAT_EN_VAL | readl(keystone->va_app_base + CMD_STATUS),
>> + keystone->va_app_base + CMD_STATUS);
>> }
>>
>> /**
>> * ks_pcie_cfg_setup() - Set up configuration space address for a device
>> *
>> - * @ks_pcie: ptr to keystone_pcie structure
>> + * @keystone: ptr to keystone_pcie structure
>> * @bus: Bus number the device is residing on
>> * @devfn: device, function number info
>> *
>> @@ -398,11 +398,11 @@ void ks_dw_pcie_setup_rc_app_regs(struct keystone_pcie *ks_pcie)
>> * we will do TYPE 0 access as it will be on our secondary bus (logical).
>> * CFG_SETUP is needed only for remote configuration access.
>> */
>> -static void __iomem *ks_pcie_cfg_setup(struct keystone_pcie *ks_pcie, u8 bus,
>> +static void __iomem *ks_pcie_cfg_setup(struct keystone_pcie *keystone, u8 bus,
>> unsigned int devfn)
>> {
>> u8 device = PCI_SLOT(devfn), function = PCI_FUNC(devfn);
>> - struct pcie_port *pp = &ks_pcie->pp;
>> + struct pcie_port *pp = &keystone->pp;
>> u32 regval;
>>
>> if (bus == 0)
>> @@ -418,18 +418,18 @@ static void __iomem *ks_pcie_cfg_setup(struct keystone_pcie *ks_pcie, u8 bus,
>> if (bus != 1)
>> regval |= BIT(24);
>>
>> - writel(regval, ks_pcie->va_app_base + CFG_SETUP);
>> + writel(regval, keystone->va_app_base + CFG_SETUP);
>> return pp->va_cfg0_base;
>> }
>>
>> int ks_dw_pcie_rd_other_conf(struct pcie_port *pp, struct pci_bus *bus,
>> unsigned int devfn, int where, int size, u32 *val)
>> {
>> - struct keystone_pcie *ks_pcie = to_keystone_pcie(pp);
>> + struct keystone_pcie *keystone = to_keystone_pcie(pp);
>> u8 bus_num = bus->number;
>> void __iomem *addr;
>>
>> - addr = ks_pcie_cfg_setup(ks_pcie, bus_num, devfn);
>> + addr = ks_pcie_cfg_setup(keystone, bus_num, devfn);
>>
>> return dw_pcie_cfg_read(addr + where, size, val);
>> }
>> @@ -437,11 +437,11 @@ int ks_dw_pcie_rd_other_conf(struct pcie_port *pp, struct pci_bus *bus,
>> int ks_dw_pcie_wr_other_conf(struct pcie_port *pp, struct pci_bus *bus,
>> unsigned int devfn, int where, int size, u32 val)
>> {
>> - struct keystone_pcie *ks_pcie = to_keystone_pcie(pp);
>> + struct keystone_pcie *keystone = to_keystone_pcie(pp);
>> u8 bus_num = bus->number;
>> void __iomem *addr;
>>
>> - addr = ks_pcie_cfg_setup(ks_pcie, bus_num, devfn);
>> + addr = ks_pcie_cfg_setup(keystone, bus_num, devfn);
>>
>> return dw_pcie_cfg_write(addr + where, size, val);
>> }
>> @@ -453,22 +453,22 @@ int ks_dw_pcie_wr_other_conf(struct pcie_port *pp, struct pci_bus *bus,
>> */
>> void ks_dw_pcie_v3_65_scan_bus(struct pcie_port *pp)
>> {
>> - struct keystone_pcie *ks_pcie = to_keystone_pcie(pp);
>> + struct keystone_pcie *keystone = to_keystone_pcie(pp);
>>
>> /* Configure and set up BAR0 */
>> - ks_dw_pcie_set_dbi_mode(ks_pcie->va_app_base);
>> + ks_dw_pcie_set_dbi_mode(keystone->va_app_base);
>>
>> /* Enable BAR0 */
>> writel(1, pp->dbi_base + PCI_BASE_ADDRESS_0);
>> writel(SZ_4K - 1, pp->dbi_base + PCI_BASE_ADDRESS_0);
>>
>> - ks_dw_pcie_clear_dbi_mode(ks_pcie->va_app_base);
>> + ks_dw_pcie_clear_dbi_mode(keystone->va_app_base);
>>
>> /*
>> * For BAR0, just setting bus address for inbound writes (MSI) should
>> * be sufficient. Use physical address to avoid any conflicts.
>> */
>> - writel(ks_pcie->app.start, pp->dbi_base + PCI_BASE_ADDRESS_0);
>> + writel(keystone->app.start, pp->dbi_base + PCI_BASE_ADDRESS_0);
>> }
>>
>> /**
>> @@ -481,18 +481,18 @@ int ks_dw_pcie_link_up(struct pcie_port *pp)
>> return (val & LTSSM_STATE_MASK) == LTSSM_STATE_L0;
>> }
>>
>> -void ks_dw_pcie_initiate_link_train(struct keystone_pcie *ks_pcie)
>> +void ks_dw_pcie_initiate_link_train(struct keystone_pcie *keystone)
>> {
>> u32 val;
>>
>> /* Disable Link training */
>> - val = readl(ks_pcie->va_app_base + CMD_STATUS);
>> + val = readl(keystone->va_app_base + CMD_STATUS);
>> val &= ~LTSSM_EN_VAL;
>> - writel(LTSSM_EN_VAL | val, ks_pcie->va_app_base + CMD_STATUS);
>> + writel(LTSSM_EN_VAL | val, keystone->va_app_base + CMD_STATUS);
>>
>> /* Initiate Link Training */
>> - val = readl(ks_pcie->va_app_base + CMD_STATUS);
>> - writel(LTSSM_EN_VAL | val, ks_pcie->va_app_base + CMD_STATUS);
>> + val = readl(keystone->va_app_base + CMD_STATUS);
>> + writel(LTSSM_EN_VAL | val, keystone->va_app_base + CMD_STATUS);
>> }
>>
>> /**
>> @@ -502,10 +502,10 @@ void ks_dw_pcie_initiate_link_train(struct keystone_pcie *ks_pcie)
>> * and call dw_pcie_v3_65_host_init() API to initialize the Keystone
>> * PCI host controller.
>> */
>> -int __init ks_dw_pcie_host_init(struct keystone_pcie *ks_pcie,
>> +int __init ks_dw_pcie_host_init(struct keystone_pcie *keystone,
>> struct device_node *msi_intc_np)
>> {
>> - struct pcie_port *pp = &ks_pcie->pp;
>> + struct pcie_port *pp = &keystone->pp;
>> struct platform_device *pdev = to_platform_device(pp->dev);
>> struct resource *res;
>>
>> @@ -524,19 +524,19 @@ int __init ks_dw_pcie_host_init(struct keystone_pcie *ks_pcie,
>>
>> /* Index 1 is the application reg. space address */
>> res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
>> - ks_pcie->va_app_base = devm_ioremap_resource(pp->dev, res);
>> - if (IS_ERR(ks_pcie->va_app_base))
>> - return PTR_ERR(ks_pcie->va_app_base);
>> + keystone->va_app_base = devm_ioremap_resource(pp->dev, res);
>> + if (IS_ERR(keystone->va_app_base))
>> + return PTR_ERR(keystone->va_app_base);
>>
>> - ks_pcie->app = *res;
>> + keystone->app = *res;
>>
>> /* Create legacy IRQ domain */
>> - ks_pcie->legacy_irq_domain =
>> - irq_domain_add_linear(ks_pcie->legacy_intc_np,
>> + keystone->legacy_irq_domain =
>> + irq_domain_add_linear(keystone->legacy_intc_np,
>> MAX_LEGACY_IRQS,
>> &ks_dw_pcie_legacy_irq_domain_ops,
>> NULL);
>> - if (!ks_pcie->legacy_irq_domain) {
>> + if (!keystone->legacy_irq_domain) {
>> dev_err(pp->dev, "Failed to add irq domain for legacy irqs\n");
>> return -EINVAL;
>> }
>> diff --git a/drivers/pci/host/pci-keystone.c b/drivers/pci/host/pci-keystone.c
>> index 82b461b..55b2be7 100644
>> --- a/drivers/pci/host/pci-keystone.c
>> +++ b/drivers/pci/host/pci-keystone.c
>> @@ -86,9 +86,9 @@ static void quirk_limit_mrrs(struct pci_dev *dev)
>> }
>> DECLARE_PCI_FIXUP_ENABLE(PCI_ANY_ID, PCI_ANY_ID, quirk_limit_mrrs);
>>
>> -static int ks_pcie_establish_link(struct keystone_pcie *ks_pcie)
>> +static int ks_pcie_establish_link(struct keystone_pcie *keystone)
>> {
>> - struct pcie_port *pp = &ks_pcie->pp;
>> + struct pcie_port *pp = &keystone->pp;
>> unsigned int retries;
>>
>> dw_pcie_setup_rc(pp);
>> @@ -100,7 +100,7 @@ static int ks_pcie_establish_link(struct keystone_pcie *ks_pcie)
>>
>> /* check if the link is up or not */
>> for (retries = 0; retries < 5; retries++) {
>> - ks_dw_pcie_initiate_link_train(ks_pcie);
>> + ks_dw_pcie_initiate_link_train(keystone);
>> if (!dw_pcie_wait_for_link(pp))
>> return 0;
>> }
>> @@ -112,9 +112,9 @@ static int ks_pcie_establish_link(struct keystone_pcie *ks_pcie)
>> static void ks_pcie_msi_irq_handler(struct irq_desc *desc)
>> {
>> unsigned int irq = irq_desc_get_irq(desc);
>> - struct keystone_pcie *ks_pcie = irq_desc_get_handler_data(desc);
>> - u32 offset = irq - ks_pcie->msi_host_irqs[0];
>> - struct pcie_port *pp = &ks_pcie->pp;
>> + struct keystone_pcie *keystone = irq_desc_get_handler_data(desc);
>> + u32 offset = irq - keystone->msi_host_irqs[0];
>> + struct pcie_port *pp = &keystone->pp;
>> struct irq_chip *chip = irq_desc_get_chip(desc);
>>
>> dev_dbg(pp->dev, "%s, irq %d\n", __func__, irq);
>> @@ -125,7 +125,7 @@ static void ks_pcie_msi_irq_handler(struct irq_desc *desc)
>> * ack operation.
>> */
>> chained_irq_enter(chip, desc);
>> - ks_dw_pcie_handle_msi_irq(ks_pcie, offset);
>> + ks_dw_pcie_handle_msi_irq(keystone, offset);
>> chained_irq_exit(chip, desc);
>> }
>>
>> @@ -140,9 +140,9 @@ static void ks_pcie_msi_irq_handler(struct irq_desc *desc)
>> static void ks_pcie_legacy_irq_handler(struct irq_desc *desc)
>> {
>> unsigned int irq = irq_desc_get_irq(desc);
>> - struct keystone_pcie *ks_pcie = irq_desc_get_handler_data(desc);
>> - struct pcie_port *pp = &ks_pcie->pp;
>> - u32 irq_offset = irq - ks_pcie->legacy_host_irqs[0];
>> + struct keystone_pcie *keystone = irq_desc_get_handler_data(desc);
>> + struct pcie_port *pp = &keystone->pp;
>> + u32 irq_offset = irq - keystone->legacy_host_irqs[0];
>> struct irq_chip *chip = irq_desc_get_chip(desc);
>>
>> dev_dbg(pp->dev, ": Handling legacy irq %d\n", irq);
>> @@ -153,28 +153,28 @@ static void ks_pcie_legacy_irq_handler(struct irq_desc *desc)
>> * ack operation.
>> */
>> chained_irq_enter(chip, desc);
>> - ks_dw_pcie_handle_legacy_irq(ks_pcie, irq_offset);
>> + ks_dw_pcie_handle_legacy_irq(keystone, irq_offset);
>> chained_irq_exit(chip, desc);
>> }
>>
>> -static int ks_pcie_get_irq_controller_info(struct keystone_pcie *ks_pcie,
>> +static int ks_pcie_get_irq_controller_info(struct keystone_pcie *keystone,
>> char *controller, int *num_irqs)
>> {
>> int temp, max_host_irqs, legacy = 1, *host_irqs;
>> - struct device *dev = ks_pcie->pp.dev;
>> + struct device *dev = keystone->pp.dev;
>> struct device_node *np_pcie = dev->of_node, **np_temp;
>>
>> if (!strcmp(controller, "msi-interrupt-controller"))
>> legacy = 0;
>>
>> if (legacy) {
>> - np_temp = &ks_pcie->legacy_intc_np;
>> + np_temp = &keystone->legacy_intc_np;
>> max_host_irqs = MAX_LEGACY_HOST_IRQS;
>> - host_irqs = &ks_pcie->legacy_host_irqs[0];
>> + host_irqs = &keystone->legacy_host_irqs[0];
>> } else {
>> - np_temp = &ks_pcie->msi_intc_np;
>> + np_temp = &keystone->msi_intc_np;
>> max_host_irqs = MAX_MSI_HOST_IRQS;
>> - host_irqs = &ks_pcie->msi_host_irqs[0];
>> + host_irqs = &keystone->msi_host_irqs[0];
>> }
>>
>> /* interrupt controller is in a child node */
>> @@ -212,29 +212,29 @@ static int ks_pcie_get_irq_controller_info(struct keystone_pcie *ks_pcie,
>> return -EINVAL;
>> }
>>
>> -static void ks_pcie_setup_interrupts(struct keystone_pcie *ks_pcie)
>> +static void ks_pcie_setup_interrupts(struct keystone_pcie *keystone)
>> {
>> int i;
>>
>> /* Legacy IRQ */
>> - for (i = 0; i < ks_pcie->num_legacy_host_irqs; i++) {
>> - irq_set_chained_handler_and_data(ks_pcie->legacy_host_irqs[i],
>> + for (i = 0; i < keystone->num_legacy_host_irqs; i++) {
>> + irq_set_chained_handler_and_data(keystone->legacy_host_irqs[i],
>> ks_pcie_legacy_irq_handler,
>> - ks_pcie);
>> + keystone);
>> }
>> - ks_dw_pcie_enable_legacy_irqs(ks_pcie);
>> + ks_dw_pcie_enable_legacy_irqs(keystone);
>>
>> /* MSI IRQ */
>> if (IS_ENABLED(CONFIG_PCI_MSI)) {
>> - for (i = 0; i < ks_pcie->num_msi_host_irqs; i++) {
>> - irq_set_chained_handler_and_data(ks_pcie->msi_host_irqs[i],
>> + for (i = 0; i < keystone->num_msi_host_irqs; i++) {
>> + irq_set_chained_handler_and_data(keystone->msi_host_irqs[i],
>> ks_pcie_msi_irq_handler,
>> - ks_pcie);
>> + keystone);
>> }
>> }
>>
>> - if (ks_pcie->error_irq > 0)
>> - ks_dw_pcie_enable_error_irq(ks_pcie->va_app_base);
>> + if (keystone->error_irq > 0)
>> + ks_dw_pcie_enable_error_irq(keystone->va_app_base);
>> }
>>
>> /*
>> @@ -259,17 +259,17 @@ static int keystone_pcie_fault(unsigned long addr, unsigned int fsr,
>>
>> static void __init ks_pcie_host_init(struct pcie_port *pp)
>> {
>> - struct keystone_pcie *ks_pcie = to_keystone_pcie(pp);
>> + struct keystone_pcie *keystone = to_keystone_pcie(pp);
>> u32 val;
>>
>> - ks_pcie_establish_link(ks_pcie);
>> - ks_dw_pcie_setup_rc_app_regs(ks_pcie);
>> - ks_pcie_setup_interrupts(ks_pcie);
>> + ks_pcie_establish_link(keystone);
>> + ks_dw_pcie_setup_rc_app_regs(keystone);
>> + ks_pcie_setup_interrupts(keystone);
>> writew(PCI_IO_RANGE_TYPE_32 | (PCI_IO_RANGE_TYPE_32 << 8),
>> pp->dbi_base + PCI_IO_BASE);
>>
>> /* update the Vendor ID */
>> - writew(ks_pcie->device_id, pp->dbi_base + PCI_DEVICE_ID);
>> + writew(keystone->device_id, pp->dbi_base + PCI_DEVICE_ID);
>>
>> /* update the DEV_STAT_CTRL to publish right mrrs */
>> val = readl(pp->dbi_base + PCIE_CAP_BASE + PCI_EXP_DEVCTL);
>> @@ -300,28 +300,28 @@ static struct pcie_host_ops keystone_pcie_host_ops = {
>>
>> static irqreturn_t pcie_err_irq_handler(int irq, void *priv)
>> {
>> - struct keystone_pcie *ks_pcie = priv;
>> + struct keystone_pcie *keystone = priv;
>>
>> - return ks_dw_pcie_handle_error_irq(ks_pcie->pp.dev,
>> - ks_pcie->va_app_base);
>> + return ks_dw_pcie_handle_error_irq(keystone->pp.dev,
>> + keystone->va_app_base);
>> }
>>
>> -static int __init ks_add_pcie_port(struct keystone_pcie *ks_pcie,
>> +static int __init ks_add_pcie_port(struct keystone_pcie *keystone,
>> struct platform_device *pdev)
>> {
>> - struct pcie_port *pp = &ks_pcie->pp;
>> + struct pcie_port *pp = &keystone->pp;
>> int ret;
>>
>> - ret = ks_pcie_get_irq_controller_info(ks_pcie,
>> + ret = ks_pcie_get_irq_controller_info(keystone,
>> "legacy-interrupt-controller",
>> - &ks_pcie->num_legacy_host_irqs);
>> + &keystone->num_legacy_host_irqs);
>> if (ret)
>> return ret;
>>
>> if (IS_ENABLED(CONFIG_PCI_MSI)) {
>> - ret = ks_pcie_get_irq_controller_info(ks_pcie,
>> + ret = ks_pcie_get_irq_controller_info(keystone,
>> "msi-interrupt-controller",
>> - &ks_pcie->num_msi_host_irqs);
>> + &keystone->num_msi_host_irqs);
>> if (ret)
>> return ret;
>> }
>> @@ -330,22 +330,22 @@ static int __init ks_add_pcie_port(struct keystone_pcie *ks_pcie,
>> * Index 0 is the platform interrupt for error interrupt
>> * from RC. This is optional.
>> */
>> - ks_pcie->error_irq = irq_of_parse_and_map(ks_pcie->np, 0);
>> - if (ks_pcie->error_irq <= 0)
>> + keystone->error_irq = irq_of_parse_and_map(keystone->np, 0);
>> + if (keystone->error_irq <= 0)
>> dev_info(&pdev->dev, "no error IRQ defined\n");
>> else {
>> - ret = request_irq(ks_pcie->error_irq, pcie_err_irq_handler,
>> - IRQF_SHARED, "pcie-error-irq", ks_pcie);
>> + ret = request_irq(keystone->error_irq, pcie_err_irq_handler,
>> + IRQF_SHARED, "pcie-error-irq", keystone);
>> if (ret < 0) {
>> dev_err(&pdev->dev, "failed to request error IRQ %d\n",
>> - ks_pcie->error_irq);
>> + keystone->error_irq);
>> return ret;
>> }
>> }
>>
>> pp->root_bus_nr = -1;
>> pp->ops = &keystone_pcie_host_ops;
>> - ret = ks_dw_pcie_host_init(ks_pcie, ks_pcie->msi_intc_np);
>> + ret = ks_dw_pcie_host_init(keystone, keystone->msi_intc_np);
>> if (ret) {
>> dev_err(&pdev->dev, "failed to initialize host\n");
>> return ret;
>> @@ -364,9 +364,9 @@ static const struct of_device_id ks_pcie_of_match[] = {
>>
>> static int __exit ks_pcie_remove(struct platform_device *pdev)
>> {
>> - struct keystone_pcie *ks_pcie = platform_get_drvdata(pdev);
>> + struct keystone_pcie *keystone = platform_get_drvdata(pdev);
>>
>> - clk_disable_unprepare(ks_pcie->clk);
>> + clk_disable_unprepare(keystone->clk);
>>
>> return 0;
>> }
>> @@ -374,19 +374,18 @@ static int __exit ks_pcie_remove(struct platform_device *pdev)
>> static int __init ks_pcie_probe(struct platform_device *pdev)
>> {
>> struct device *dev = &pdev->dev;
>> - struct keystone_pcie *ks_pcie;
>> + struct keystone_pcie *keystone;
>> struct pcie_port *pp;
>> struct resource *res;
>> void __iomem *reg_p;
>> struct phy *phy;
>> int ret;
>>
>> - ks_pcie = devm_kzalloc(&pdev->dev, sizeof(*ks_pcie),
>> - GFP_KERNEL);
>> - if (!ks_pcie)
>> + keystone = devm_kzalloc(&pdev->dev, sizeof(*keystone), GFP_KERNEL);
>> + if (!keystone)
>> return -ENOMEM;
>>
>> - pp = &ks_pcie->pp;
>> + pp = &keystone->pp;
>>
>> /* initialize SerDes Phy if present */
>> phy = devm_phy_get(dev, "pcie-phy");
>> @@ -404,29 +403,29 @@ static int __init ks_pcie_probe(struct platform_device *pdev)
>> reg_p = devm_ioremap_resource(dev, res);
>> if (IS_ERR(reg_p))
>> return PTR_ERR(reg_p);
>> - ks_pcie->device_id = readl(reg_p) >> 16;
>> + keystone->device_id = readl(reg_p) >> 16;
>> devm_iounmap(dev, reg_p);
>> devm_release_mem_region(dev, res->start, resource_size(res));
>>
>> pp->dev = dev;
>> - ks_pcie->np = dev->of_node;
>> - platform_set_drvdata(pdev, ks_pcie);
>> - ks_pcie->clk = devm_clk_get(dev, "pcie");
>> - if (IS_ERR(ks_pcie->clk)) {
>> + keystone->np = dev->of_node;
>> + platform_set_drvdata(pdev, keystone);
>> + keystone->clk = devm_clk_get(dev, "pcie");
>> + if (IS_ERR(keystone->clk)) {
>> dev_err(dev, "Failed to get pcie rc clock\n");
>> - return PTR_ERR(ks_pcie->clk);
>> + return PTR_ERR(keystone->clk);
>> }
>> - ret = clk_prepare_enable(ks_pcie->clk);
>> + ret = clk_prepare_enable(keystone->clk);
>> if (ret)
>> return ret;
>>
>> - ret = ks_add_pcie_port(ks_pcie, pdev);
>> + ret = ks_add_pcie_port(keystone, pdev);
>> if (ret < 0)
>> goto fail_clk;
>>
>> return 0;
>> fail_clk:
>> - clk_disable_unprepare(ks_pcie->clk);
>> + clk_disable_unprepare(keystone->clk);
>>
>> return ret;
>> }
>> diff --git a/drivers/pci/host/pci-keystone.h b/drivers/pci/host/pci-keystone.h
>> index a5b0cb2..379213c 100644
>> --- a/drivers/pci/host/pci-keystone.h
>> +++ b/drivers/pci/host/pci-keystone.h
>> @@ -39,24 +39,24 @@ struct keystone_pcie {
>> };
>>
>> /* Keystone DW specific MSI controller APIs/definitions */
>> -void ks_dw_pcie_handle_msi_irq(struct keystone_pcie *ks_pcie, int offset);
>> +void ks_dw_pcie_handle_msi_irq(struct keystone_pcie *keystone, int offset);
>> phys_addr_t ks_dw_pcie_get_msi_addr(struct pcie_port *pp);
>>
>> /* Keystone specific PCI controller APIs */
>> -void ks_dw_pcie_enable_legacy_irqs(struct keystone_pcie *ks_pcie);
>> -void ks_dw_pcie_handle_legacy_irq(struct keystone_pcie *ks_pcie, int offset);
>> +void ks_dw_pcie_enable_legacy_irqs(struct keystone_pcie *keystone);
>> +void ks_dw_pcie_handle_legacy_irq(struct keystone_pcie *keystone, int offset);
>> void ks_dw_pcie_enable_error_irq(void __iomem *reg_base);
>> irqreturn_t ks_dw_pcie_handle_error_irq(struct device *dev,
>> void __iomem *reg_base);
>> -int ks_dw_pcie_host_init(struct keystone_pcie *ks_pcie,
>> +int ks_dw_pcie_host_init(struct keystone_pcie *keystone,
>> struct device_node *msi_intc_np);
>> int ks_dw_pcie_wr_other_conf(struct pcie_port *pp, struct pci_bus *bus,
>> unsigned int devfn, int where, int size, u32 val);
>> int ks_dw_pcie_rd_other_conf(struct pcie_port *pp, struct pci_bus *bus,
>> unsigned int devfn, int where, int size, u32 *val);
>> -void ks_dw_pcie_setup_rc_app_regs(struct keystone_pcie *ks_pcie);
>> +void ks_dw_pcie_setup_rc_app_regs(struct keystone_pcie *keystone);
>> int ks_dw_pcie_link_up(struct pcie_port *pp);
>> -void ks_dw_pcie_initiate_link_train(struct keystone_pcie *ks_pcie);
>> +void ks_dw_pcie_initiate_link_train(struct keystone_pcie *keystone);
>> void ks_dw_pcie_msi_set_irq(struct pcie_port *pp, int irq);
>> void ks_dw_pcie_msi_clear_irq(struct pcie_port *pp, int irq);
>> void ks_dw_pcie_v3_65_scan_bus(struct pcie_port *pp);
>>
>
>
--
Murali Karicheri
Linux Kernel, Keystone
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH 1/6] PCI: keystone: Name private struct pointer "keystone" consistently
2016-10-07 16:53 ` [PATCH 1/6] PCI: keystone: Name private struct pointer "keystone" consistently Murali Karicheri
2016-10-07 16:56 ` Murali Karicheri
@ 2016-10-07 18:09 ` Bjorn Helgaas
1 sibling, 0 replies; 9+ messages in thread
From: Bjorn Helgaas @ 2016-10-07 18:09 UTC (permalink / raw)
To: Murali Karicheri; +Cc: Bjorn Helgaas, linux-pci
On Fri, Oct 07, 2016 at 12:53:45PM -0400, Murali Karicheri wrote:
> On 10/07/2016 12:40 PM, Bjorn Helgaas wrote:
> > Use a device-specific name, "keystone", for struct keystone_pcie pointers
> referring to keystone pcie as keystone is not right. keystone_pcie make sense.
> To use a short name ks_pcie was used. So what is wrong with the naming?
> I believe this patch is unnecessary.
Yeah, you're right. I'm sure that's the case for several of the other
drivers, too.
I think it's more wordy than necessary to include the "_pcie" part for
every mention in the file, but I guess we do that for all the function
names, too. I do like the fact that you included "ks_" already, which
gives us a hint that this is keystone-specific. I dropped this one
and re-pushed the branch. Thanks for taking a look.
> Murali
> > to hint that this is device-specific information. No functional change
> > intended.
> >
> > Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
> > ---
> > drivers/pci/host/pci-keystone-dw.c | 122 ++++++++++++++++++-----------------
> > drivers/pci/host/pci-keystone.c | 125 ++++++++++++++++++------------------
> > drivers/pci/host/pci-keystone.h | 12 ++-
> > 3 files changed, 129 insertions(+), 130 deletions(-)
> >
> > diff --git a/drivers/pci/host/pci-keystone-dw.c b/drivers/pci/host/pci-keystone-dw.c
> > index 4151509..d09e3c6 100644
> > --- a/drivers/pci/host/pci-keystone-dw.c
> > +++ b/drivers/pci/host/pci-keystone-dw.c
> > @@ -83,18 +83,18 @@ static inline void update_reg_offset_bit_pos(u32 offset, u32 *reg_offset,
> >
> > phys_addr_t ks_dw_pcie_get_msi_addr(struct pcie_port *pp)
> > {
> > - struct keystone_pcie *ks_pcie = to_keystone_pcie(pp);
> > + struct keystone_pcie *keystone = to_keystone_pcie(pp);
> >
> > - return ks_pcie->app.start + MSI_IRQ;
> > + return keystone->app.start + MSI_IRQ;
> > }
> >
> > -void ks_dw_pcie_handle_msi_irq(struct keystone_pcie *ks_pcie, int offset)
> > +void ks_dw_pcie_handle_msi_irq(struct keystone_pcie *keystone, int offset)
> > {
> > - struct pcie_port *pp = &ks_pcie->pp;
> > + struct pcie_port *pp = &keystone->pp;
> > u32 pending, vector;
> > int src, virq;
> >
> > - pending = readl(ks_pcie->va_app_base + MSI0_IRQ_STATUS + (offset << 4));
> > + pending = readl(keystone->va_app_base + MSI0_IRQ_STATUS + (offset << 4));
> >
> > /*
> > * MSI0 status bit 0-3 shows vectors 0, 8, 16, 24, MSI1 status bit
> > @@ -114,51 +114,51 @@ void ks_dw_pcie_handle_msi_irq(struct keystone_pcie *ks_pcie, int offset)
> > static void ks_dw_pcie_msi_irq_ack(struct irq_data *d)
> > {
> > u32 offset, reg_offset, bit_pos;
> > - struct keystone_pcie *ks_pcie;
> > + struct keystone_pcie *keystone;
> > struct msi_desc *msi;
> > struct pcie_port *pp;
> >
> > msi = irq_data_get_msi_desc(d);
> > pp = (struct pcie_port *) msi_desc_to_pci_sysdata(msi);
> > - ks_pcie = to_keystone_pcie(pp);
> > + keystone = to_keystone_pcie(pp);
> > offset = d->irq - irq_linear_revmap(pp->irq_domain, 0);
> > update_reg_offset_bit_pos(offset, ®_offset, &bit_pos);
> >
> > writel(BIT(bit_pos),
> > - ks_pcie->va_app_base + MSI0_IRQ_STATUS + (reg_offset << 4));
> > - writel(reg_offset + MSI_IRQ_OFFSET, ks_pcie->va_app_base + IRQ_EOI);
> > + keystone->va_app_base + MSI0_IRQ_STATUS + (reg_offset << 4));
> > + writel(reg_offset + MSI_IRQ_OFFSET, keystone->va_app_base + IRQ_EOI);
> > }
> >
> > void ks_dw_pcie_msi_set_irq(struct pcie_port *pp, int irq)
> > {
> > u32 reg_offset, bit_pos;
> > - struct keystone_pcie *ks_pcie = to_keystone_pcie(pp);
> > + struct keystone_pcie *keystone = to_keystone_pcie(pp);
> >
> > update_reg_offset_bit_pos(irq, ®_offset, &bit_pos);
> > writel(BIT(bit_pos),
> > - ks_pcie->va_app_base + MSI0_IRQ_ENABLE_SET + (reg_offset << 4));
> > + keystone->va_app_base + MSI0_IRQ_ENABLE_SET + (reg_offset << 4));
> > }
> >
> > void ks_dw_pcie_msi_clear_irq(struct pcie_port *pp, int irq)
> > {
> > u32 reg_offset, bit_pos;
> > - struct keystone_pcie *ks_pcie = to_keystone_pcie(pp);
> > + struct keystone_pcie *keystone = to_keystone_pcie(pp);
> >
> > update_reg_offset_bit_pos(irq, ®_offset, &bit_pos);
> > writel(BIT(bit_pos),
> > - ks_pcie->va_app_base + MSI0_IRQ_ENABLE_CLR + (reg_offset << 4));
> > + keystone->va_app_base + MSI0_IRQ_ENABLE_CLR + (reg_offset << 4));
> > }
> >
> > static void ks_dw_pcie_msi_irq_mask(struct irq_data *d)
> > {
> > - struct keystone_pcie *ks_pcie;
> > + struct keystone_pcie *keystone;
> > struct msi_desc *msi;
> > struct pcie_port *pp;
> > u32 offset;
> >
> > msi = irq_data_get_msi_desc(d);
> > pp = (struct pcie_port *) msi_desc_to_pci_sysdata(msi);
> > - ks_pcie = to_keystone_pcie(pp);
> > + keystone = to_keystone_pcie(pp);
> > offset = d->irq - irq_linear_revmap(pp->irq_domain, 0);
> >
> > /* Mask the end point if PVM implemented */
> > @@ -172,14 +172,14 @@ static void ks_dw_pcie_msi_irq_mask(struct irq_data *d)
> >
> > static void ks_dw_pcie_msi_irq_unmask(struct irq_data *d)
> > {
> > - struct keystone_pcie *ks_pcie;
> > + struct keystone_pcie *keystone;
> > struct msi_desc *msi;
> > struct pcie_port *pp;
> > u32 offset;
> >
> > msi = irq_data_get_msi_desc(d);
> > pp = (struct pcie_port *) msi_desc_to_pci_sysdata(msi);
> > - ks_pcie = to_keystone_pcie(pp);
> > + keystone = to_keystone_pcie(pp);
> > offset = d->irq - irq_linear_revmap(pp->irq_domain, 0);
> >
> > /* Mask the end point if PVM implemented */
> > @@ -214,10 +214,10 @@ static const struct irq_domain_ops ks_dw_pcie_msi_domain_ops = {
> >
> > int ks_dw_pcie_msi_host_init(struct pcie_port *pp, struct msi_controller *chip)
> > {
> > - struct keystone_pcie *ks_pcie = to_keystone_pcie(pp);
> > + struct keystone_pcie *keystone = to_keystone_pcie(pp);
> > int i;
> >
> > - pp->irq_domain = irq_domain_add_linear(ks_pcie->msi_intc_np,
> > + pp->irq_domain = irq_domain_add_linear(keystone->msi_intc_np,
> > MAX_MSI_IRQS,
> > &ks_dw_pcie_msi_domain_ops,
> > chip);
> > @@ -232,31 +232,31 @@ int ks_dw_pcie_msi_host_init(struct pcie_port *pp, struct msi_controller *chip)
> > return 0;
> > }
> >
> > -void ks_dw_pcie_enable_legacy_irqs(struct keystone_pcie *ks_pcie)
> > +void ks_dw_pcie_enable_legacy_irqs(struct keystone_pcie *keystone)
> > {
> > int i;
> >
> > for (i = 0; i < MAX_LEGACY_IRQS; i++)
> > - writel(0x1, ks_pcie->va_app_base + IRQ_ENABLE_SET + (i << 4));
> > + writel(0x1, keystone->va_app_base + IRQ_ENABLE_SET + (i << 4));
> > }
> >
> > -void ks_dw_pcie_handle_legacy_irq(struct keystone_pcie *ks_pcie, int offset)
> > +void ks_dw_pcie_handle_legacy_irq(struct keystone_pcie *keystone, int offset)
> > {
> > - struct pcie_port *pp = &ks_pcie->pp;
> > + struct pcie_port *pp = &keystone->pp;
> > u32 pending;
> > int virq;
> >
> > - pending = readl(ks_pcie->va_app_base + IRQ_STATUS + (offset << 4));
> > + pending = readl(keystone->va_app_base + IRQ_STATUS + (offset << 4));
> >
> > if (BIT(0) & pending) {
> > - virq = irq_linear_revmap(ks_pcie->legacy_irq_domain, offset);
> > + virq = irq_linear_revmap(keystone->legacy_irq_domain, offset);
> > dev_dbg(pp->dev, ": irq: irq_offset %d, virq %d\n", offset,
> > virq);
> > generic_handle_irq(virq);
> > }
> >
> > /* EOI the INTx interrupt */
> > - writel(offset, ks_pcie->va_app_base + IRQ_EOI);
> > + writel(offset, keystone->va_app_base + IRQ_EOI);
> > }
> >
> > void ks_dw_pcie_enable_error_irq(void __iomem *reg_base)
> > @@ -352,39 +352,39 @@ static void ks_dw_pcie_clear_dbi_mode(void __iomem *reg_virt)
> > } while (val & DBI_CS2_EN_VAL);
> > }
> >
> > -void ks_dw_pcie_setup_rc_app_regs(struct keystone_pcie *ks_pcie)
> > +void ks_dw_pcie_setup_rc_app_regs(struct keystone_pcie *keystone)
> > {
> > - struct pcie_port *pp = &ks_pcie->pp;
> > + struct pcie_port *pp = &keystone->pp;
> > u32 start = pp->mem->start, end = pp->mem->end;
> > int i, tr_size;
> >
> > /* Disable BARs for inbound access */
> > - ks_dw_pcie_set_dbi_mode(ks_pcie->va_app_base);
> > + ks_dw_pcie_set_dbi_mode(keystone->va_app_base);
> > writel(0, pp->dbi_base + PCI_BASE_ADDRESS_0);
> > writel(0, pp->dbi_base + PCI_BASE_ADDRESS_1);
> > - ks_dw_pcie_clear_dbi_mode(ks_pcie->va_app_base);
> > + ks_dw_pcie_clear_dbi_mode(keystone->va_app_base);
> >
> > /* Set outbound translation size per window division */
> > - writel(CFG_PCIM_WIN_SZ_IDX & 0x7, ks_pcie->va_app_base + OB_SIZE);
> > + writel(CFG_PCIM_WIN_SZ_IDX & 0x7, keystone->va_app_base + OB_SIZE);
> >
> > tr_size = (1 << (CFG_PCIM_WIN_SZ_IDX & 0x7)) * SZ_1M;
> >
> > /* Using Direct 1:1 mapping of RC <-> PCI memory space */
> > for (i = 0; (i < CFG_PCIM_WIN_CNT) && (start < end); i++) {
> > - writel(start | 1, ks_pcie->va_app_base + OB_OFFSET_INDEX(i));
> > - writel(0, ks_pcie->va_app_base + OB_OFFSET_HI(i));
> > + writel(start | 1, keystone->va_app_base + OB_OFFSET_INDEX(i));
> > + writel(0, keystone->va_app_base + OB_OFFSET_HI(i));
> > start += tr_size;
> > }
> >
> > /* Enable OB translation */
> > - writel(OB_XLAT_EN_VAL | readl(ks_pcie->va_app_base + CMD_STATUS),
> > - ks_pcie->va_app_base + CMD_STATUS);
> > + writel(OB_XLAT_EN_VAL | readl(keystone->va_app_base + CMD_STATUS),
> > + keystone->va_app_base + CMD_STATUS);
> > }
> >
> > /**
> > * ks_pcie_cfg_setup() - Set up configuration space address for a device
> > *
> > - * @ks_pcie: ptr to keystone_pcie structure
> > + * @keystone: ptr to keystone_pcie structure
> > * @bus: Bus number the device is residing on
> > * @devfn: device, function number info
> > *
> > @@ -398,11 +398,11 @@ void ks_dw_pcie_setup_rc_app_regs(struct keystone_pcie *ks_pcie)
> > * we will do TYPE 0 access as it will be on our secondary bus (logical).
> > * CFG_SETUP is needed only for remote configuration access.
> > */
> > -static void __iomem *ks_pcie_cfg_setup(struct keystone_pcie *ks_pcie, u8 bus,
> > +static void __iomem *ks_pcie_cfg_setup(struct keystone_pcie *keystone, u8 bus,
> > unsigned int devfn)
> > {
> > u8 device = PCI_SLOT(devfn), function = PCI_FUNC(devfn);
> > - struct pcie_port *pp = &ks_pcie->pp;
> > + struct pcie_port *pp = &keystone->pp;
> > u32 regval;
> >
> > if (bus == 0)
> > @@ -418,18 +418,18 @@ static void __iomem *ks_pcie_cfg_setup(struct keystone_pcie *ks_pcie, u8 bus,
> > if (bus != 1)
> > regval |= BIT(24);
> >
> > - writel(regval, ks_pcie->va_app_base + CFG_SETUP);
> > + writel(regval, keystone->va_app_base + CFG_SETUP);
> > return pp->va_cfg0_base;
> > }
> >
> > int ks_dw_pcie_rd_other_conf(struct pcie_port *pp, struct pci_bus *bus,
> > unsigned int devfn, int where, int size, u32 *val)
> > {
> > - struct keystone_pcie *ks_pcie = to_keystone_pcie(pp);
> > + struct keystone_pcie *keystone = to_keystone_pcie(pp);
> > u8 bus_num = bus->number;
> > void __iomem *addr;
> >
> > - addr = ks_pcie_cfg_setup(ks_pcie, bus_num, devfn);
> > + addr = ks_pcie_cfg_setup(keystone, bus_num, devfn);
> >
> > return dw_pcie_cfg_read(addr + where, size, val);
> > }
> > @@ -437,11 +437,11 @@ int ks_dw_pcie_rd_other_conf(struct pcie_port *pp, struct pci_bus *bus,
> > int ks_dw_pcie_wr_other_conf(struct pcie_port *pp, struct pci_bus *bus,
> > unsigned int devfn, int where, int size, u32 val)
> > {
> > - struct keystone_pcie *ks_pcie = to_keystone_pcie(pp);
> > + struct keystone_pcie *keystone = to_keystone_pcie(pp);
> > u8 bus_num = bus->number;
> > void __iomem *addr;
> >
> > - addr = ks_pcie_cfg_setup(ks_pcie, bus_num, devfn);
> > + addr = ks_pcie_cfg_setup(keystone, bus_num, devfn);
> >
> > return dw_pcie_cfg_write(addr + where, size, val);
> > }
> > @@ -453,22 +453,22 @@ int ks_dw_pcie_wr_other_conf(struct pcie_port *pp, struct pci_bus *bus,
> > */
> > void ks_dw_pcie_v3_65_scan_bus(struct pcie_port *pp)
> > {
> > - struct keystone_pcie *ks_pcie = to_keystone_pcie(pp);
> > + struct keystone_pcie *keystone = to_keystone_pcie(pp);
> >
> > /* Configure and set up BAR0 */
> > - ks_dw_pcie_set_dbi_mode(ks_pcie->va_app_base);
> > + ks_dw_pcie_set_dbi_mode(keystone->va_app_base);
> >
> > /* Enable BAR0 */
> > writel(1, pp->dbi_base + PCI_BASE_ADDRESS_0);
> > writel(SZ_4K - 1, pp->dbi_base + PCI_BASE_ADDRESS_0);
> >
> > - ks_dw_pcie_clear_dbi_mode(ks_pcie->va_app_base);
> > + ks_dw_pcie_clear_dbi_mode(keystone->va_app_base);
> >
> > /*
> > * For BAR0, just setting bus address for inbound writes (MSI) should
> > * be sufficient. Use physical address to avoid any conflicts.
> > */
> > - writel(ks_pcie->app.start, pp->dbi_base + PCI_BASE_ADDRESS_0);
> > + writel(keystone->app.start, pp->dbi_base + PCI_BASE_ADDRESS_0);
> > }
> >
> > /**
> > @@ -481,18 +481,18 @@ int ks_dw_pcie_link_up(struct pcie_port *pp)
> > return (val & LTSSM_STATE_MASK) == LTSSM_STATE_L0;
> > }
> >
> > -void ks_dw_pcie_initiate_link_train(struct keystone_pcie *ks_pcie)
> > +void ks_dw_pcie_initiate_link_train(struct keystone_pcie *keystone)
> > {
> > u32 val;
> >
> > /* Disable Link training */
> > - val = readl(ks_pcie->va_app_base + CMD_STATUS);
> > + val = readl(keystone->va_app_base + CMD_STATUS);
> > val &= ~LTSSM_EN_VAL;
> > - writel(LTSSM_EN_VAL | val, ks_pcie->va_app_base + CMD_STATUS);
> > + writel(LTSSM_EN_VAL | val, keystone->va_app_base + CMD_STATUS);
> >
> > /* Initiate Link Training */
> > - val = readl(ks_pcie->va_app_base + CMD_STATUS);
> > - writel(LTSSM_EN_VAL | val, ks_pcie->va_app_base + CMD_STATUS);
> > + val = readl(keystone->va_app_base + CMD_STATUS);
> > + writel(LTSSM_EN_VAL | val, keystone->va_app_base + CMD_STATUS);
> > }
> >
> > /**
> > @@ -502,10 +502,10 @@ void ks_dw_pcie_initiate_link_train(struct keystone_pcie *ks_pcie)
> > * and call dw_pcie_v3_65_host_init() API to initialize the Keystone
> > * PCI host controller.
> > */
> > -int __init ks_dw_pcie_host_init(struct keystone_pcie *ks_pcie,
> > +int __init ks_dw_pcie_host_init(struct keystone_pcie *keystone,
> > struct device_node *msi_intc_np)
> > {
> > - struct pcie_port *pp = &ks_pcie->pp;
> > + struct pcie_port *pp = &keystone->pp;
> > struct platform_device *pdev = to_platform_device(pp->dev);
> > struct resource *res;
> >
> > @@ -524,19 +524,19 @@ int __init ks_dw_pcie_host_init(struct keystone_pcie *ks_pcie,
> >
> > /* Index 1 is the application reg. space address */
> > res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
> > - ks_pcie->va_app_base = devm_ioremap_resource(pp->dev, res);
> > - if (IS_ERR(ks_pcie->va_app_base))
> > - return PTR_ERR(ks_pcie->va_app_base);
> > + keystone->va_app_base = devm_ioremap_resource(pp->dev, res);
> > + if (IS_ERR(keystone->va_app_base))
> > + return PTR_ERR(keystone->va_app_base);
> >
> > - ks_pcie->app = *res;
> > + keystone->app = *res;
> >
> > /* Create legacy IRQ domain */
> > - ks_pcie->legacy_irq_domain =
> > - irq_domain_add_linear(ks_pcie->legacy_intc_np,
> > + keystone->legacy_irq_domain =
> > + irq_domain_add_linear(keystone->legacy_intc_np,
> > MAX_LEGACY_IRQS,
> > &ks_dw_pcie_legacy_irq_domain_ops,
> > NULL);
> > - if (!ks_pcie->legacy_irq_domain) {
> > + if (!keystone->legacy_irq_domain) {
> > dev_err(pp->dev, "Failed to add irq domain for legacy irqs\n");
> > return -EINVAL;
> > }
> > diff --git a/drivers/pci/host/pci-keystone.c b/drivers/pci/host/pci-keystone.c
> > index 82b461b..55b2be7 100644
> > --- a/drivers/pci/host/pci-keystone.c
> > +++ b/drivers/pci/host/pci-keystone.c
> > @@ -86,9 +86,9 @@ static void quirk_limit_mrrs(struct pci_dev *dev)
> > }
> > DECLARE_PCI_FIXUP_ENABLE(PCI_ANY_ID, PCI_ANY_ID, quirk_limit_mrrs);
> >
> > -static int ks_pcie_establish_link(struct keystone_pcie *ks_pcie)
> > +static int ks_pcie_establish_link(struct keystone_pcie *keystone)
> > {
> > - struct pcie_port *pp = &ks_pcie->pp;
> > + struct pcie_port *pp = &keystone->pp;
> > unsigned int retries;
> >
> > dw_pcie_setup_rc(pp);
> > @@ -100,7 +100,7 @@ static int ks_pcie_establish_link(struct keystone_pcie *ks_pcie)
> >
> > /* check if the link is up or not */
> > for (retries = 0; retries < 5; retries++) {
> > - ks_dw_pcie_initiate_link_train(ks_pcie);
> > + ks_dw_pcie_initiate_link_train(keystone);
> > if (!dw_pcie_wait_for_link(pp))
> > return 0;
> > }
> > @@ -112,9 +112,9 @@ static int ks_pcie_establish_link(struct keystone_pcie *ks_pcie)
> > static void ks_pcie_msi_irq_handler(struct irq_desc *desc)
> > {
> > unsigned int irq = irq_desc_get_irq(desc);
> > - struct keystone_pcie *ks_pcie = irq_desc_get_handler_data(desc);
> > - u32 offset = irq - ks_pcie->msi_host_irqs[0];
> > - struct pcie_port *pp = &ks_pcie->pp;
> > + struct keystone_pcie *keystone = irq_desc_get_handler_data(desc);
> > + u32 offset = irq - keystone->msi_host_irqs[0];
> > + struct pcie_port *pp = &keystone->pp;
> > struct irq_chip *chip = irq_desc_get_chip(desc);
> >
> > dev_dbg(pp->dev, "%s, irq %d\n", __func__, irq);
> > @@ -125,7 +125,7 @@ static void ks_pcie_msi_irq_handler(struct irq_desc *desc)
> > * ack operation.
> > */
> > chained_irq_enter(chip, desc);
> > - ks_dw_pcie_handle_msi_irq(ks_pcie, offset);
> > + ks_dw_pcie_handle_msi_irq(keystone, offset);
> > chained_irq_exit(chip, desc);
> > }
> >
> > @@ -140,9 +140,9 @@ static void ks_pcie_msi_irq_handler(struct irq_desc *desc)
> > static void ks_pcie_legacy_irq_handler(struct irq_desc *desc)
> > {
> > unsigned int irq = irq_desc_get_irq(desc);
> > - struct keystone_pcie *ks_pcie = irq_desc_get_handler_data(desc);
> > - struct pcie_port *pp = &ks_pcie->pp;
> > - u32 irq_offset = irq - ks_pcie->legacy_host_irqs[0];
> > + struct keystone_pcie *keystone = irq_desc_get_handler_data(desc);
> > + struct pcie_port *pp = &keystone->pp;
> > + u32 irq_offset = irq - keystone->legacy_host_irqs[0];
> > struct irq_chip *chip = irq_desc_get_chip(desc);
> >
> > dev_dbg(pp->dev, ": Handling legacy irq %d\n", irq);
> > @@ -153,28 +153,28 @@ static void ks_pcie_legacy_irq_handler(struct irq_desc *desc)
> > * ack operation.
> > */
> > chained_irq_enter(chip, desc);
> > - ks_dw_pcie_handle_legacy_irq(ks_pcie, irq_offset);
> > + ks_dw_pcie_handle_legacy_irq(keystone, irq_offset);
> > chained_irq_exit(chip, desc);
> > }
> >
> > -static int ks_pcie_get_irq_controller_info(struct keystone_pcie *ks_pcie,
> > +static int ks_pcie_get_irq_controller_info(struct keystone_pcie *keystone,
> > char *controller, int *num_irqs)
> > {
> > int temp, max_host_irqs, legacy = 1, *host_irqs;
> > - struct device *dev = ks_pcie->pp.dev;
> > + struct device *dev = keystone->pp.dev;
> > struct device_node *np_pcie = dev->of_node, **np_temp;
> >
> > if (!strcmp(controller, "msi-interrupt-controller"))
> > legacy = 0;
> >
> > if (legacy) {
> > - np_temp = &ks_pcie->legacy_intc_np;
> > + np_temp = &keystone->legacy_intc_np;
> > max_host_irqs = MAX_LEGACY_HOST_IRQS;
> > - host_irqs = &ks_pcie->legacy_host_irqs[0];
> > + host_irqs = &keystone->legacy_host_irqs[0];
> > } else {
> > - np_temp = &ks_pcie->msi_intc_np;
> > + np_temp = &keystone->msi_intc_np;
> > max_host_irqs = MAX_MSI_HOST_IRQS;
> > - host_irqs = &ks_pcie->msi_host_irqs[0];
> > + host_irqs = &keystone->msi_host_irqs[0];
> > }
> >
> > /* interrupt controller is in a child node */
> > @@ -212,29 +212,29 @@ static int ks_pcie_get_irq_controller_info(struct keystone_pcie *ks_pcie,
> > return -EINVAL;
> > }
> >
> > -static void ks_pcie_setup_interrupts(struct keystone_pcie *ks_pcie)
> > +static void ks_pcie_setup_interrupts(struct keystone_pcie *keystone)
> > {
> > int i;
> >
> > /* Legacy IRQ */
> > - for (i = 0; i < ks_pcie->num_legacy_host_irqs; i++) {
> > - irq_set_chained_handler_and_data(ks_pcie->legacy_host_irqs[i],
> > + for (i = 0; i < keystone->num_legacy_host_irqs; i++) {
> > + irq_set_chained_handler_and_data(keystone->legacy_host_irqs[i],
> > ks_pcie_legacy_irq_handler,
> > - ks_pcie);
> > + keystone);
> > }
> > - ks_dw_pcie_enable_legacy_irqs(ks_pcie);
> > + ks_dw_pcie_enable_legacy_irqs(keystone);
> >
> > /* MSI IRQ */
> > if (IS_ENABLED(CONFIG_PCI_MSI)) {
> > - for (i = 0; i < ks_pcie->num_msi_host_irqs; i++) {
> > - irq_set_chained_handler_and_data(ks_pcie->msi_host_irqs[i],
> > + for (i = 0; i < keystone->num_msi_host_irqs; i++) {
> > + irq_set_chained_handler_and_data(keystone->msi_host_irqs[i],
> > ks_pcie_msi_irq_handler,
> > - ks_pcie);
> > + keystone);
> > }
> > }
> >
> > - if (ks_pcie->error_irq > 0)
> > - ks_dw_pcie_enable_error_irq(ks_pcie->va_app_base);
> > + if (keystone->error_irq > 0)
> > + ks_dw_pcie_enable_error_irq(keystone->va_app_base);
> > }
> >
> > /*
> > @@ -259,17 +259,17 @@ static int keystone_pcie_fault(unsigned long addr, unsigned int fsr,
> >
> > static void __init ks_pcie_host_init(struct pcie_port *pp)
> > {
> > - struct keystone_pcie *ks_pcie = to_keystone_pcie(pp);
> > + struct keystone_pcie *keystone = to_keystone_pcie(pp);
> > u32 val;
> >
> > - ks_pcie_establish_link(ks_pcie);
> > - ks_dw_pcie_setup_rc_app_regs(ks_pcie);
> > - ks_pcie_setup_interrupts(ks_pcie);
> > + ks_pcie_establish_link(keystone);
> > + ks_dw_pcie_setup_rc_app_regs(keystone);
> > + ks_pcie_setup_interrupts(keystone);
> > writew(PCI_IO_RANGE_TYPE_32 | (PCI_IO_RANGE_TYPE_32 << 8),
> > pp->dbi_base + PCI_IO_BASE);
> >
> > /* update the Vendor ID */
> > - writew(ks_pcie->device_id, pp->dbi_base + PCI_DEVICE_ID);
> > + writew(keystone->device_id, pp->dbi_base + PCI_DEVICE_ID);
> >
> > /* update the DEV_STAT_CTRL to publish right mrrs */
> > val = readl(pp->dbi_base + PCIE_CAP_BASE + PCI_EXP_DEVCTL);
> > @@ -300,28 +300,28 @@ static struct pcie_host_ops keystone_pcie_host_ops = {
> >
> > static irqreturn_t pcie_err_irq_handler(int irq, void *priv)
> > {
> > - struct keystone_pcie *ks_pcie = priv;
> > + struct keystone_pcie *keystone = priv;
> >
> > - return ks_dw_pcie_handle_error_irq(ks_pcie->pp.dev,
> > - ks_pcie->va_app_base);
> > + return ks_dw_pcie_handle_error_irq(keystone->pp.dev,
> > + keystone->va_app_base);
> > }
> >
> > -static int __init ks_add_pcie_port(struct keystone_pcie *ks_pcie,
> > +static int __init ks_add_pcie_port(struct keystone_pcie *keystone,
> > struct platform_device *pdev)
> > {
> > - struct pcie_port *pp = &ks_pcie->pp;
> > + struct pcie_port *pp = &keystone->pp;
> > int ret;
> >
> > - ret = ks_pcie_get_irq_controller_info(ks_pcie,
> > + ret = ks_pcie_get_irq_controller_info(keystone,
> > "legacy-interrupt-controller",
> > - &ks_pcie->num_legacy_host_irqs);
> > + &keystone->num_legacy_host_irqs);
> > if (ret)
> > return ret;
> >
> > if (IS_ENABLED(CONFIG_PCI_MSI)) {
> > - ret = ks_pcie_get_irq_controller_info(ks_pcie,
> > + ret = ks_pcie_get_irq_controller_info(keystone,
> > "msi-interrupt-controller",
> > - &ks_pcie->num_msi_host_irqs);
> > + &keystone->num_msi_host_irqs);
> > if (ret)
> > return ret;
> > }
> > @@ -330,22 +330,22 @@ static int __init ks_add_pcie_port(struct keystone_pcie *ks_pcie,
> > * Index 0 is the platform interrupt for error interrupt
> > * from RC. This is optional.
> > */
> > - ks_pcie->error_irq = irq_of_parse_and_map(ks_pcie->np, 0);
> > - if (ks_pcie->error_irq <= 0)
> > + keystone->error_irq = irq_of_parse_and_map(keystone->np, 0);
> > + if (keystone->error_irq <= 0)
> > dev_info(&pdev->dev, "no error IRQ defined\n");
> > else {
> > - ret = request_irq(ks_pcie->error_irq, pcie_err_irq_handler,
> > - IRQF_SHARED, "pcie-error-irq", ks_pcie);
> > + ret = request_irq(keystone->error_irq, pcie_err_irq_handler,
> > + IRQF_SHARED, "pcie-error-irq", keystone);
> > if (ret < 0) {
> > dev_err(&pdev->dev, "failed to request error IRQ %d\n",
> > - ks_pcie->error_irq);
> > + keystone->error_irq);
> > return ret;
> > }
> > }
> >
> > pp->root_bus_nr = -1;
> > pp->ops = &keystone_pcie_host_ops;
> > - ret = ks_dw_pcie_host_init(ks_pcie, ks_pcie->msi_intc_np);
> > + ret = ks_dw_pcie_host_init(keystone, keystone->msi_intc_np);
> > if (ret) {
> > dev_err(&pdev->dev, "failed to initialize host\n");
> > return ret;
> > @@ -364,9 +364,9 @@ static const struct of_device_id ks_pcie_of_match[] = {
> >
> > static int __exit ks_pcie_remove(struct platform_device *pdev)
> > {
> > - struct keystone_pcie *ks_pcie = platform_get_drvdata(pdev);
> > + struct keystone_pcie *keystone = platform_get_drvdata(pdev);
> >
> > - clk_disable_unprepare(ks_pcie->clk);
> > + clk_disable_unprepare(keystone->clk);
> >
> > return 0;
> > }
> > @@ -374,19 +374,18 @@ static int __exit ks_pcie_remove(struct platform_device *pdev)
> > static int __init ks_pcie_probe(struct platform_device *pdev)
> > {
> > struct device *dev = &pdev->dev;
> > - struct keystone_pcie *ks_pcie;
> > + struct keystone_pcie *keystone;
> > struct pcie_port *pp;
> > struct resource *res;
> > void __iomem *reg_p;
> > struct phy *phy;
> > int ret;
> >
> > - ks_pcie = devm_kzalloc(&pdev->dev, sizeof(*ks_pcie),
> > - GFP_KERNEL);
> > - if (!ks_pcie)
> > + keystone = devm_kzalloc(&pdev->dev, sizeof(*keystone), GFP_KERNEL);
> > + if (!keystone)
> > return -ENOMEM;
> >
> > - pp = &ks_pcie->pp;
> > + pp = &keystone->pp;
> >
> > /* initialize SerDes Phy if present */
> > phy = devm_phy_get(dev, "pcie-phy");
> > @@ -404,29 +403,29 @@ static int __init ks_pcie_probe(struct platform_device *pdev)
> > reg_p = devm_ioremap_resource(dev, res);
> > if (IS_ERR(reg_p))
> > return PTR_ERR(reg_p);
> > - ks_pcie->device_id = readl(reg_p) >> 16;
> > + keystone->device_id = readl(reg_p) >> 16;
> > devm_iounmap(dev, reg_p);
> > devm_release_mem_region(dev, res->start, resource_size(res));
> >
> > pp->dev = dev;
> > - ks_pcie->np = dev->of_node;
> > - platform_set_drvdata(pdev, ks_pcie);
> > - ks_pcie->clk = devm_clk_get(dev, "pcie");
> > - if (IS_ERR(ks_pcie->clk)) {
> > + keystone->np = dev->of_node;
> > + platform_set_drvdata(pdev, keystone);
> > + keystone->clk = devm_clk_get(dev, "pcie");
> > + if (IS_ERR(keystone->clk)) {
> > dev_err(dev, "Failed to get pcie rc clock\n");
> > - return PTR_ERR(ks_pcie->clk);
> > + return PTR_ERR(keystone->clk);
> > }
> > - ret = clk_prepare_enable(ks_pcie->clk);
> > + ret = clk_prepare_enable(keystone->clk);
> > if (ret)
> > return ret;
> >
> > - ret = ks_add_pcie_port(ks_pcie, pdev);
> > + ret = ks_add_pcie_port(keystone, pdev);
> > if (ret < 0)
> > goto fail_clk;
> >
> > return 0;
> > fail_clk:
> > - clk_disable_unprepare(ks_pcie->clk);
> > + clk_disable_unprepare(keystone->clk);
> >
> > return ret;
> > }
> > diff --git a/drivers/pci/host/pci-keystone.h b/drivers/pci/host/pci-keystone.h
> > index a5b0cb2..379213c 100644
> > --- a/drivers/pci/host/pci-keystone.h
> > +++ b/drivers/pci/host/pci-keystone.h
> > @@ -39,24 +39,24 @@ struct keystone_pcie {
> > };
> >
> > /* Keystone DW specific MSI controller APIs/definitions */
> > -void ks_dw_pcie_handle_msi_irq(struct keystone_pcie *ks_pcie, int offset);
> > +void ks_dw_pcie_handle_msi_irq(struct keystone_pcie *keystone, int offset);
> > phys_addr_t ks_dw_pcie_get_msi_addr(struct pcie_port *pp);
> >
> > /* Keystone specific PCI controller APIs */
> > -void ks_dw_pcie_enable_legacy_irqs(struct keystone_pcie *ks_pcie);
> > -void ks_dw_pcie_handle_legacy_irq(struct keystone_pcie *ks_pcie, int offset);
> > +void ks_dw_pcie_enable_legacy_irqs(struct keystone_pcie *keystone);
> > +void ks_dw_pcie_handle_legacy_irq(struct keystone_pcie *keystone, int offset);
> > void ks_dw_pcie_enable_error_irq(void __iomem *reg_base);
> > irqreturn_t ks_dw_pcie_handle_error_irq(struct device *dev,
> > void __iomem *reg_base);
> > -int ks_dw_pcie_host_init(struct keystone_pcie *ks_pcie,
> > +int ks_dw_pcie_host_init(struct keystone_pcie *keystone,
> > struct device_node *msi_intc_np);
> > int ks_dw_pcie_wr_other_conf(struct pcie_port *pp, struct pci_bus *bus,
> > unsigned int devfn, int where, int size, u32 val);
> > int ks_dw_pcie_rd_other_conf(struct pcie_port *pp, struct pci_bus *bus,
> > unsigned int devfn, int where, int size, u32 *val);
> > -void ks_dw_pcie_setup_rc_app_regs(struct keystone_pcie *ks_pcie);
> > +void ks_dw_pcie_setup_rc_app_regs(struct keystone_pcie *keystone);
> > int ks_dw_pcie_link_up(struct pcie_port *pp);
> > -void ks_dw_pcie_initiate_link_train(struct keystone_pcie *ks_pcie);
> > +void ks_dw_pcie_initiate_link_train(struct keystone_pcie *keystone);
> > void ks_dw_pcie_msi_set_irq(struct pcie_port *pp, int irq);
> > void ks_dw_pcie_msi_clear_irq(struct pcie_port *pp, int irq);
> > void ks_dw_pcie_v3_65_scan_bus(struct pcie_port *pp);
> >
>
>
> --
> Murali Karicheri
> Linux Kernel, Keystone
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^ permalink raw reply [flat|nested] 9+ messages in thread
end of thread, other threads:[~2016-10-07 18:10 UTC | newest]
Thread overview: 9+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2016-10-07 16:40 [PATCH 1/6] PCI: keystone: Name private struct pointer "keystone" consistently Bjorn Helgaas
2016-10-07 16:40 ` [PATCH 2/6] PCI: keystone: Pass keystone_pcie, not address, to IRQ functions Bjorn Helgaas
2016-10-07 16:40 ` [PATCH 3/6] PCI: keystone: Pass keystone_pcie, not address, to DBI functions Bjorn Helgaas
2016-10-07 16:40 ` [PATCH 4/6] PCI: keystone: Add app register accessors Bjorn Helgaas
2016-10-07 16:41 ` [PATCH 5/6] PCI: keystone: Reorder struct keystone_pcie Bjorn Helgaas
2016-10-07 16:41 ` [PATCH 6/6] PCI: keystone: Use dw_pcie_readl_rc() and dw_pcie_pcie_writel_rc() Bjorn Helgaas
2016-10-07 16:53 ` [PATCH 1/6] PCI: keystone: Name private struct pointer "keystone" consistently Murali Karicheri
2016-10-07 16:56 ` Murali Karicheri
2016-10-07 18:09 ` Bjorn Helgaas
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