From: Rob Herring <robh@kernel.org>
To: Jon Derrick <jonathan.derrick@intel.com>
Cc: Thomas Petazzoni <thomas.petazzoni@bootlin.com>,
Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
Russell King <rmk+kernel@armlinux.org.uk>,
Bjorn Helgaas <helgaas@kernel.org>,
Christoph Hellwig <hch@lst.de>,
linux-pci@vger.kernel.org
Subject: Re: [PATCH v2 4/4] PCI: pci-bridge-emul: Eliminate the 'reserved' member
Date: Wed, 20 May 2020 16:41:03 -0600 [thread overview]
Message-ID: <20200520224103.GA736673@bogus> (raw)
In-Reply-To: <20200511162117.6674-5-jonathan.derrick@intel.com>
On Mon, 11 May 2020 12:21:17 -0400, Jon Derrick wrote:
> Per PCIe 5.0 r1.0, Terms and Acronyms, Page 80:
>
> Reserved register fields must be read only and must return 0 (all 0's
> for multi-bit fields) when read. Reserved encodings for register and
> packet fields must not be used. Any implementation dependence on a
> Reserved field value or encoding will result in an implementation that
> is not PCI Express-compliant.
>
> This patch ensures reads will return 0 for any bit not in the Read-Only,
> Read-Write, or Write-1-to-Clear bitmasks.
>
> Signed-off-by: Jon Derrick <jonathan.derrick@intel.com>
> ---
> drivers/pci/pci-bridge-emul.c | 30 +++++++++++++-----------------
> 1 file changed, 13 insertions(+), 17 deletions(-)
>
Acked-by: Rob Herring <robh@kernel.org>
next prev parent reply other threads:[~2020-05-20 22:41 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-05-11 16:21 [PATCH v2 0/4] Align PCI Emul Bridge to PCIe 5.0 Jon Derrick
2020-05-11 16:21 ` [PATCH v2 1/4] PCI: pci-bridge-emul: Fix PCIe bit conflicts Jon Derrick
2020-05-11 16:21 ` [PATCH v2 2/4] PCI: pci-bridge-emul: Fix Root Cap/Status comment Jon Derrick
2020-05-11 16:21 ` [PATCH v2 3/4] PCI: pci-bridge-emul: Update for PCIe 5.0 r1.0 Jon Derrick
2020-05-20 22:39 ` Rob Herring
2020-05-11 16:21 ` [PATCH v2 4/4] PCI: pci-bridge-emul: Eliminate the 'reserved' member Jon Derrick
2020-05-20 22:41 ` Rob Herring [this message]
2020-05-22 11:42 ` [PATCH v2 0/4] Align PCI Emul Bridge to PCIe 5.0 Lorenzo Pieralisi
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