From: Bharat Kumar Gogada <bharat.kumar.gogada@xilinx.com>
To: <linux-pci@vger.kernel.org>, <linux-kernel@vger.kernel.org>
Cc: <lorenzo.pieralisi@arm.com>, <bhelgaas@google.com>,
<michals@xilinx.com>,
Bharat Kumar Gogada <bharat.kumar.gogada@xilinx.com>
Subject: [PATCH 0/2] Add support for Xilinx Versal CPM5 Root Port
Date: Mon, 7 Feb 2022 09:42:47 +0530 [thread overview]
Message-ID: <20220207041250.1658-1-bharat.kumar.gogada@xilinx.com> (raw)
Xilinx Versal Premium series has CPM5 block which supports Root port
functioning at Gen5 speed.
Xilinx Versal CPM5 has few changes with existing CPM block.
- CPM5 has dedicated register space for control and status registers.
- CPM5 legacy interrupt handling needs additonal register bit
to enable and handle legacy interrupts.
Bharat Kumar Gogada (2):
PCI: xilinx-cpm: Update YAML schemas for Versal CPM5 Root Port
PCI: xilinx-cpm: Add support for Versal CPM5 Root Port driver
.../bindings/pci/xilinx-versal-cpm.yaml | 47 ++++++++++++++++---
drivers/pci/controller/pcie-xilinx-cpm.c | 33 ++++++++++++-
2 files changed, 72 insertions(+), 8 deletions(-)
--
2.17.1
next reply other threads:[~2022-02-07 6:16 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-02-07 4:12 Bharat Kumar Gogada [this message]
2022-02-07 4:12 ` [PATCH 1/2] PCI: xilinx-cpm: Update YAML schemas for Versal CPM5 Root Port Bharat Kumar Gogada
2022-02-07 18:28 ` Bjorn Helgaas
2022-02-08 10:38 ` Bharat Kumar Gogada
2022-02-07 4:12 ` Bharat Kumar Gogada
2022-02-07 4:12 ` [PATCH 2/2] PCI: xilinx-cpm: Add support for Versal CPM5 Root Port driver Bharat Kumar Gogada
2022-02-07 18:30 ` Bjorn Helgaas
2022-02-08 10:38 ` Bharat Kumar Gogada
2022-02-07 4:31 ` [PATCH 0/2] Add support for Xilinx Versal CPM5 Root Port Bharat Kumar Gogada
-- strict thread matches above, loose matches on Subject: below --
2022-02-04 13:02 Bharat Kumar Gogada
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