From: Lukas Wunner <lukas@wunner.de>
To: Lukasz Majczak <lma@semihalf.com>
Cc: bhelgaas@google.com, Rajat Jain <rajatja@google.com>,
Vidya Sagar <vidyas@nvidia.com>,
upstream@semihalf.com, linux-pci@vger.kernel.org,
LKML <linux-kernel@vger.kernel.org>
Subject: Re: [BUG] Intel Apollolake: PCIe bridge "loses" capabilities after entering D3Cold state
Date: Fri, 21 Oct 2022 13:19:35 +0200 [thread overview]
Message-ID: <20221021111935.GB28729@wunner.de> (raw)
In-Reply-To: <CAFJ_xbq0cxcH-cgpXLU4Mjk30+muWyWm1aUZGK7iG53yaLBaQg@mail.gmail.com>
On Fri, Oct 21, 2022 at 12:17:35PM +0200, Lukasz Majczak wrote:
> While working with Vidya???s patch I have noticed that after
> suspend/resume cycle on my Chromebook (Apollolake) PCIe bridge loses
> its capabilities - the missing part is:
>
> Capabilities: [200 v1] L1 PM Substates
> L1SubCap: PCI-PM_L1.2+ PCI-PM_L1.1+ ASPM_L1.2+ ASPM_L1.1+ L1_PM_Substates+
> PortCommonModeRestoreTime=40us PortTPowerOnTime=10us
> L1SubCtl1: PCI-PM_L1.2+ PCI-PM_L1.1+ ASPM_L1.2+ ASPM_L1.1+
> T_CommonMode=40us LTR1.2_Threshold=98304ns
> L1SubCtl2: T_PwrOn=60us
>
> Digging more I???ve found out that entering D3Cold state causes this
You mean the capability is gone from lspci after D3cold?
My understanding is that BIOS is responsible for populating config space.
So this sounds like a BIOS bug. What's the BIOS vendor and version?
(dmesg | grep DMI)
Thanks,
Lukas
next prev parent reply other threads:[~2022-10-21 11:19 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-10-21 10:17 [BUG] Intel Apollolake: PCIe bridge "loses" capabilities after entering D3Cold state Lukasz Majczak
2022-10-21 11:19 ` Lukas Wunner [this message]
2022-10-21 12:33 ` Lukasz Majczak
[not found] ` <CAOs-w0KRYh-=gTb0Ed5iYAMs92AYtV_oEei5OgezgKGfwfiBYg@mail.gmail.com>
2022-10-21 15:40 ` Radosław Biernacki
2022-10-21 21:08 ` Bjorn Helgaas
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