Linux PCI subsystem development
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From: Mario Limonciello <mario.limonciello@amd.com>
To: "Rafael J . Wysocki" <rafael@kernel.org>,
	Bjorn Helgaas <helgaas@kernel.org>
Cc: <linux-pci@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
	Len Brown <lenb@kernel.org>, <linux-acpi@vger.kernel.org>,
	Mario Limonciello <mario.limonciello@amd.com>
Subject: [PATCH v7 0/2] Fix wakeup problems on some AMD platforms
Date: Mon, 10 Jul 2023 19:53:23 -0500	[thread overview]
Message-ID: <20230711005325.1499-1-mario.limonciello@amd.com> (raw)

Problems have been reported on AMD laptops with suspend/resume
where particular root ports are put into D3 and then the system is unable
to resume properly.

The issue boils down to the currently selected kernel policy for root port
behavior at suspend time:
0) If the machine is from 2015 or later
1) If a PCIe root port is power manageable by the platform then platform
   will be used to determine the power state of the root port at suspend.
2) If the PCIe root is not power manageable by the platform then the kernel
   will check if it was configured to wakeup. 
3) If it was, then it will be put into the deepest state that supports
   wakeup from PME.
4) If it wasn't, then it will be put into D3hot.

This series adjusts it so only root ports that are power manageable by
the platform will be considered for being put into D3.

Mario Limonciello (2):
  PCI: Refactor pci_bridge_d3_possible()
  PCI: Don't put PCIe root ports into D3 unless they are power
    manageable

 drivers/pci/pci.c | 76 ++++++++++++++++++++++++++---------------------
 1 file changed, 42 insertions(+), 34 deletions(-)


base-commit: 06c2afb862f9da8dc5efa4b6076a0e48c3fbaaa5
-- 
2.34.1


             reply	other threads:[~2023-07-11  1:38 UTC|newest]

Thread overview: 20+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-07-11  0:53 Mario Limonciello [this message]
2023-07-11  0:53 ` [PATCH v7 1/2] PCI: Refactor pci_bridge_d3_possible() Mario Limonciello
2023-07-11  0:53 ` [PATCH v7 2/2] PCI: Don't put non-power manageable PCIe root ports into D3 Mario Limonciello
2023-07-11 22:14   ` Bjorn Helgaas
2023-07-11 22:54     ` Mario Limonciello
2023-07-12 12:13       ` Rafael J. Wysocki
2023-07-12 16:09         ` Limonciello, Mario
2023-07-14 19:17           ` Rafael J. Wysocki
2023-07-15  0:46             ` Limonciello, Mario
2023-08-01  3:25               ` Mario Limonciello
2023-08-01 10:15                 ` Rafael J. Wysocki
2023-08-02  3:17                   ` Mario Limonciello
2023-08-02  5:26                     ` Mika Westerberg
2023-08-02 14:10                       ` Mario Limonciello
2023-08-02 14:31                         ` Mika Westerberg
2023-08-02 14:35                           ` Mario Limonciello
2023-08-02 15:00                             ` Mika Westerberg
     [not found]             ` <67fa2dda-f383-1864-57b8-08b86263bd02@amd.com>
2023-08-01  9:54               ` Rafael J. Wysocki
2023-07-12 11:48     ` Rafael J. Wysocki
2023-07-12 15:23       ` Andy Shevchenko

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