From: Manivannan Sadhasivam <mani@kernel.org>
To: Niklas Cassel <nks@flawful.org>
Cc: "Jingoo Han" <jingoohan1@gmail.com>,
"Gustavo Pimentel" <gustavo.pimentel@synopsys.com>,
"Manivannan Sadhasivam" <mani@kernel.org>,
"Lorenzo Pieralisi" <lpieralisi@kernel.org>,
"Krzysztof Wilczyński" <kw@linux.com>,
"Rob Herring" <robh@kernel.org>,
"Bjorn Helgaas" <bhelgaas@google.com>,
"Kishon Vijay Abraham I" <kishon@kernel.org>,
"Niklas Cassel" <niklas.cassel@wdc.com>,
linux-pci@vger.kernel.org
Subject: Re: [PATCH v2] PCI: dwc: endpoint: Fix dw_pcie_ep_raise_msix_irq() alignment support
Date: Tue, 2 Jan 2024 21:24:06 +0530 [thread overview]
Message-ID: <20240102155406.GA4917@thinkpad> (raw)
In-Reply-To: <20231128132231.2221614-1-nks@flawful.org>
On Tue, Nov 28, 2023 at 02:22:30PM +0100, Niklas Cassel wrote:
> From: Niklas Cassel <niklas.cassel@wdc.com>
>
> Commit 6f5e193bfb55 ("PCI: dwc: Fix dw_pcie_ep_raise_msix_irq() to get
> correct MSI-X table address") modified dw_pcie_ep_raise_msix_irq() to
> support iATUs which require a specific alignment.
>
> However, this support cannot have been properly tested.
>
> The whole point is for the iATU to map an address that is aligned,
> using dw_pcie_ep_map_addr(), and then let the writel() write to
> ep->msi_mem + aligned_offset.
>
> Thus, modify the address that is mapped such that it is aligned.
> With this change, dw_pcie_ep_raise_msix_irq() matches the logic in
> dw_pcie_ep_raise_msi_irq().
>
> Cc: Kishon Vijay Abraham I <kishon@kernel.org>
> Fixes: 6f5e193bfb55 ("PCI: dwc: Fix dw_pcie_ep_raise_msix_irq() to get correct MSI-X table address")
> Signed-off-by: Niklas Cassel <niklas.cassel@wdc.com>
I apparently missed this patch... LGTM!
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Btw, since you are sending this patch from a different address, relevant s-o-b
should also be present.
- Mani
> ---
> Changes since v1:
> -Clarified commit message.
> -Add a working email for Kishon to CC.
>
> drivers/pci/controller/dwc/pcie-designware-ep.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c
> index f6207989fc6a..bc94d7f39535 100644
> --- a/drivers/pci/controller/dwc/pcie-designware-ep.c
> +++ b/drivers/pci/controller/dwc/pcie-designware-ep.c
> @@ -615,6 +615,7 @@ int dw_pcie_ep_raise_msix_irq(struct dw_pcie_ep *ep, u8 func_no,
> }
>
> aligned_offset = msg_addr & (epc->mem->window.page_size - 1);
> + msg_addr &= ~aligned_offset;
> ret = dw_pcie_ep_map_addr(epc, func_no, 0, ep->msi_mem_phys, msg_addr,
> epc->mem->window.page_size);
> if (ret)
> --
> 2.43.0
>
--
மணிவண்ணன் சதாசிவம்
prev parent reply other threads:[~2024-01-02 15:54 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-11-28 13:22 [PATCH v2] PCI: dwc: endpoint: Fix dw_pcie_ep_raise_msix_irq() alignment support Niklas Cassel
2023-11-28 16:21 ` Manivannan Sadhasivam
2023-12-14 9:59 ` Niklas Cassel
2023-12-18 1:17 ` Krzysztof Wilczyński
2023-12-18 1:12 ` Krzysztof Wilczyński
2023-12-26 22:17 ` Bjorn Helgaas
2023-12-27 11:57 ` Niklas Cassel
2023-12-27 13:03 ` Bjorn Helgaas
2024-01-02 16:48 ` Manivannan Sadhasivam
2024-01-02 10:25 ` Kishon Vijay Abraham I
2024-01-03 6:03 ` Kishon Vijay Abraham I
2024-01-09 12:52 ` Niklas Cassel
2024-01-02 15:54 ` Manivannan Sadhasivam [this message]
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