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From: Shyam Saini <shyamsaini@linux.microsoft.com>
To: manivannan.sadhasivam@linaro.org
Cc: Sergey.Semin@baikalelectronics.ru, apais@linux.microsoft.com,
	bboscaccy@linux.microsoft.com, code@tyhicks.com,
	fancer.lancer@gmail.com, jingoohan1@gmail.com,
	linux-pci@vger.kernel.org, okaya@kernel.org, robh@kernel.org,
	shyamsaini@linux.microsoft.com, srivatsa@csail.mit.edu,
	tballasi@linux.microsoft.com, vijayb@linux.microsoft.com
Subject: [PATCH V2] drivers: pci: dwc: configure multiple atu regions
Date: Thu, 13 Jun 2024 15:47:47 -0700	[thread overview]
Message-ID: <20240613224747.545908-1-shyamsaini@linux.microsoft.com> (raw)
In-Reply-To: <20240612060743.GE2645@thinkpad>

Hi Manivannan,

>> Before this change, the dwc PCIe driver configures only 1 ATU region,
>> which is sufficient for the devices with PCIe memory <= 4GB. However,
>> the driver probe fails when device uses more than 4GB of pcie memory.
>> 
> Something is not clear... This commit message implies that the driver used to
> work on your hardware (you haven't mentioned which one it is) and broken by the
> commit from Sergey.

sorry for any confusion, the driver use to work in v5.10 kernel, with v6.0 kernel it
fails to probe with following messages:
layerscape-pcie xx00000.pcie: Failed to set MEM range ...
layerscape-pcie: probe of xx00000.pcie failed with error -22

By tracing code, I found that the probe was failing on [1] this check,
which was added in [2] upstream commit from Serge and finally, the ATU upper bound limit was
set to 4G in [3] commit

pci driver probe succeeds either when
         1) I remove [1] check
         2) or by setting the ATU limit to the size of Mem64 range (my original patch [4])

> As per Sergey's commit, we auto detect the dw_pcie::region_limit. If the IP is <
> 4.60, then the limit is 4G, otherwise depends on CX_ATU_MAX_REGION_SIZE set in
> hw.

I couldn't find any reference of CX_ATU_MAX_REGION_SIZE in my PCIe TRM, perhaps because it
is older than v4.60

> So if your IP is < 4.60, you cannot map > 4GB of outbound memory anyway. But if
> it is > 4.60, you shouldn't see the failure that you reported for > 4G space
> (well you can see the failure if the limit is less than the region size). In the
> previous thread you mentioned that dw_pcie::region_limit is set to 4G. So how
> come your driver was working previously?

The PCIe IP is from Synopsys and is older than 4.60, the board is from Freescale LX2
family. The board uses drivers/pci/controller/dwc/pci-layerscape.c driver
Given PCIe IP is older than 4.60, I am not sure why it was working earlier for a memory range larger than 4G
Highly appreciate your guidance and help on this.

Best regards,
Shyam

[1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/pci/controller/dwc/pcie-designware.c?h=v6.10-rc3#n480
[2] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/drivers/pci/controller/dwc?h=v6.10-rc3&id=edf408b946d37cc70fbf0db6ab85bbf67dae1894
[3] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/drivers/pci/controller/dwc?h=v6.10-rc3&id=89473aa9ab261948ed13b16effe841a675efed77
[4] https://lore.kernel.org/linux-pci/20240523001046.1413579-1-shyamsaini@linux.microsoft.com/





  reply	other threads:[~2024-06-13 22:47 UTC|newest]

Thread overview: 7+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-06-10 23:50 [PATCH V2] drivers: pci: dwc: configure multiple atu regions Shyam Saini
2024-06-12  6:07 ` Manivannan Sadhasivam
2024-06-13 22:47   ` Shyam Saini [this message]
2024-06-14 10:40     ` Serge Semin
2024-06-26  8:26       ` Shyam Saini
2024-06-28 17:27         ` Serge Semin
2024-06-14 12:26 ` Serge Semin

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