* [PATCH] PCI: qcom: Disable ASPM L0s on x1e801800
@ 2024-07-26 6:54 Abel Vesa
2024-07-26 12:00 ` Manivannan Sadhasivam
0 siblings, 1 reply; 2+ messages in thread
From: Abel Vesa @ 2024-07-26 6:54 UTC (permalink / raw)
To: Manivannan Sadhasivam, Lorenzo Pieralisi,
Krzysztof Wilczyński, Rob Herring, Bjorn Helgaas
Cc: Johan Hovold, Krzysztof Wilczyński, linux-arm-msm, linux-pci,
linux-kernel, Abel Vesa
Confirmed by Qualcomm that the L0s should be disabled on this platform
as well. So use the sc8280xp config instead.
Fixes: 6d0c39324c5f ("PCI: qcom: Add X1E80100 PCIe support")
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
---
drivers/pci/controller/dwc/pcie-qcom.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
index 0180edf3310e..04fe624b49c1 100644
--- a/drivers/pci/controller/dwc/pcie-qcom.c
+++ b/drivers/pci/controller/dwc/pcie-qcom.c
@@ -1739,7 +1739,7 @@ static const struct of_device_id qcom_pcie_match[] = {
{ .compatible = "qcom,pcie-sm8450-pcie0", .data = &cfg_1_9_0 },
{ .compatible = "qcom,pcie-sm8450-pcie1", .data = &cfg_1_9_0 },
{ .compatible = "qcom,pcie-sm8550", .data = &cfg_1_9_0 },
- { .compatible = "qcom,pcie-x1e80100", .data = &cfg_1_9_0 },
+ { .compatible = "qcom,pcie-x1e80100", .data = &cfg_sc8280xp },
{ }
};
---
base-commit: 864b1099d16fc7e332c3ad7823058c65f890486c
change-id: 20240725-x1e80100-pcie-disable-l0s-548a2f316eec
Best regards,
--
Abel Vesa <abel.vesa@linaro.org>
^ permalink raw reply related [flat|nested] 2+ messages in thread
* Re: [PATCH] PCI: qcom: Disable ASPM L0s on x1e801800
2024-07-26 6:54 [PATCH] PCI: qcom: Disable ASPM L0s on x1e801800 Abel Vesa
@ 2024-07-26 12:00 ` Manivannan Sadhasivam
0 siblings, 0 replies; 2+ messages in thread
From: Manivannan Sadhasivam @ 2024-07-26 12:00 UTC (permalink / raw)
To: Abel Vesa
Cc: Lorenzo Pieralisi, Krzysztof Wilczyński, Rob Herring,
Bjorn Helgaas, Johan Hovold, Krzysztof Wilczyński,
linux-arm-msm, linux-pci, linux-kernel
On Fri, Jul 26, 2024 at 09:54:13AM +0300, Abel Vesa wrote:
> Confirmed by Qualcomm that the L0s should be disabled on this platform
> as well. So use the sc8280xp config instead.
>
What are the implications of not disabling L0s? Is it not supported on this
platform or the PHY sequence doesn't support L0s?
Please add these info in commit message.
- Mani
> Fixes: 6d0c39324c5f ("PCI: qcom: Add X1E80100 PCIe support")
> Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
> ---
> drivers/pci/controller/dwc/pcie-qcom.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
> index 0180edf3310e..04fe624b49c1 100644
> --- a/drivers/pci/controller/dwc/pcie-qcom.c
> +++ b/drivers/pci/controller/dwc/pcie-qcom.c
> @@ -1739,7 +1739,7 @@ static const struct of_device_id qcom_pcie_match[] = {
> { .compatible = "qcom,pcie-sm8450-pcie0", .data = &cfg_1_9_0 },
> { .compatible = "qcom,pcie-sm8450-pcie1", .data = &cfg_1_9_0 },
> { .compatible = "qcom,pcie-sm8550", .data = &cfg_1_9_0 },
> - { .compatible = "qcom,pcie-x1e80100", .data = &cfg_1_9_0 },
> + { .compatible = "qcom,pcie-x1e80100", .data = &cfg_sc8280xp },
> { }
> };
>
>
> ---
> base-commit: 864b1099d16fc7e332c3ad7823058c65f890486c
> change-id: 20240725-x1e80100-pcie-disable-l0s-548a2f316eec
>
> Best regards,
> --
> Abel Vesa <abel.vesa@linaro.org>
>
--
மணிவண்ணன் சதாசிவம்
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