[PATCH v3 1/2] PCI: Add Rockchip vendor ID

[PATCH v3 1/2] PCI: Add Rockchip vendor ID

[Shawn Lin]

This patch moves PCI_VENDOR_ID_ROCKCHIP from pci_endpoint_test.c to
pci_ids.h. And reuse it in pcie-rockchip-host.c.

Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Cc: Krzysztof Wilczynski <kw@linux.com>
Cc: Lorenzo Pieralisi <lpieralisi@kernel.org>
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>

---

Changes in v3:
- add commit log and reuse this ID for more places

Changes in v2: None

 drivers/misc/pci_endpoint_test.c            | 1 -
 drivers/pci/controller/pcie-rockchip-host.c | 2 +-
 drivers/pci/controller/pcie-rockchip.h      | 1 -
 include/linux/pci_ids.h                     | 2 ++
 4 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/misc/pci_endpoint_test.c b/drivers/misc/pci_endpoint_test.c
index 3aaaf47..b5c8422 100644
--- a/drivers/misc/pci_endpoint_test.c
+++ b/drivers/misc/pci_endpoint_test.c
@@ -85,7 +85,6 @@
 #define PCI_DEVICE_ID_RENESAS_R8A774E1		0x0025
 #define PCI_DEVICE_ID_RENESAS_R8A779F0		0x0031
 
-#define PCI_VENDOR_ID_ROCKCHIP			0x1d87
 #define PCI_DEVICE_ID_ROCKCHIP_RK3588		0x3588
 
 static DEFINE_IDA(pci_endpoint_test_ida);
diff --git a/drivers/pci/controller/pcie-rockchip-host.c b/drivers/pci/controller/pcie-rockchip-host.c
index 5adac6a..6a46be1 100644
--- a/drivers/pci/controller/pcie-rockchip-host.c
+++ b/drivers/pci/controller/pcie-rockchip-host.c
@@ -367,7 +367,7 @@ static int rockchip_pcie_host_init_port(struct rockchip_pcie *rockchip)
 		}
 	}
 
-	rockchip_pcie_write(rockchip, ROCKCHIP_VENDOR_ID,
+	rockchip_pcie_write(rockchip, PCI_VENDOR_ID_ROCKCHIP,
 			    PCIE_CORE_CONFIG_VENDOR);
 	rockchip_pcie_write(rockchip,
 			    PCI_CLASS_BRIDGE_PCI_NORMAL << 8,
diff --git a/drivers/pci/controller/pcie-rockchip.h b/drivers/pci/controller/pcie-rockchip.h
index a51b087..f9eaac9 100644
--- a/drivers/pci/controller/pcie-rockchip.h
+++ b/drivers/pci/controller/pcie-rockchip.h
@@ -198,7 +198,6 @@
 #define AXI_WRAPPER_NOR_MSG			0xc
 
 #define PCIE_RC_SEND_PME_OFF			0x11960
-#define ROCKCHIP_VENDOR_ID			0x1d87
 #define PCIE_LINK_IS_L2(x) \
 	(((x) & PCIE_CLIENT_DEBUG_LTSSM_MASK) == PCIE_CLIENT_DEBUG_LTSSM_L2)
 #define PCIE_LINK_TRAINING_DONE(x) \
diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h
index d2402bf..6f68267 100644
--- a/include/linux/pci_ids.h
+++ b/include/linux/pci_ids.h
@@ -2604,6 +2604,8 @@
 
 #define PCI_VENDOR_ID_ZHAOXIN		0x1d17
 
+#define PCI_VENDOR_ID_ROCKCHIP		0x1d87
+
 #define PCI_VENDOR_ID_HYGON		0x1d94
 
 #define PCI_VENDOR_ID_META		0x1d9b
-- 
2.7.4

[PATCH v3 2/2] perf/dwc_pcie: Add support for Rockchip SoCs

[Shawn Lin]

Add support for Rockchip SoCs by adding vendor ID to the vendor list.
And fix the lane-event based enable/disable/read process which is slightly
different on Rockchip SoCs, by checking vendor ID.

Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>

---

Changes in v3: None
Changes in v2:
- rebase on Bejorn's new patch about Qualifing VSEC Capability by Vendor, Revision

 drivers/perf/dwc_pcie_pmu.c | 22 ++++++++++++++++++++++
 1 file changed, 22 insertions(+)

diff --git a/drivers/perf/dwc_pcie_pmu.c b/drivers/perf/dwc_pcie_pmu.c
index d022f49..ba6d5116 100644
--- a/drivers/perf/dwc_pcie_pmu.c
+++ b/drivers/perf/dwc_pcie_pmu.c
@@ -116,6 +116,8 @@ static const struct dwc_pcie_pmu_vsec_id dwc_pcie_pmu_vsec_ids[] = {
 	  .vsec_id = 0x02, .vsec_rev = 0x4 },
 	{ .vendor_id = PCI_VENDOR_ID_QCOM,
 	  .vsec_id = 0x02, .vsec_rev = 0x4 },
+	{ .vendor_id = PCI_VENDOR_ID_ROCKCHIP,
+	  .vsec_id = 0x02, .vsec_rev = 0x4 },
 	{} /* terminator */
 };
 
@@ -264,12 +266,27 @@ static const struct attribute_group *dwc_pcie_attr_groups[] = {
 	NULL
 };
 
+static void dwc_pcie_pmu_lane_event_enable_for_rk(struct pci_dev *pdev,
+						  u16 ras_des_offset,
+						  bool enable)
+{
+	if (enable)
+		pci_write_config_dword(pdev, ras_des_offset + DWC_PCIE_EVENT_CNT_CTL,
+				DWC_PCIE_CNT_ENABLE | DWC_PCIE_PER_EVENT_ON);
+	else
+		pci_clear_and_set_config_dword(pdev, ras_des_offset + DWC_PCIE_EVENT_CNT_CTL,
+				DWC_PCIE_CNT_ENABLE, DWC_PCIE_PER_EVENT_ON);
+}
+
 static void dwc_pcie_pmu_lane_event_enable(struct dwc_pcie_pmu *pcie_pmu,
 					   bool enable)
 {
 	struct pci_dev *pdev = pcie_pmu->pdev;
 	u16 ras_des_offset = pcie_pmu->ras_des_offset;
 
+	if (pdev->vendor == PCI_VENDOR_ID_ROCKCHIP)
+		return dwc_pcie_pmu_lane_event_enable_for_rk(pdev, ras_des_offset, enable);
+
 	if (enable)
 		pci_clear_and_set_config_dword(pdev,
 					ras_des_offset + DWC_PCIE_EVENT_CNT_CTL,
@@ -295,9 +312,14 @@ static u64 dwc_pcie_pmu_read_lane_event_counter(struct perf_event *event)
 {
 	struct dwc_pcie_pmu *pcie_pmu = to_dwc_pcie_pmu(event->pmu);
 	struct pci_dev *pdev = pcie_pmu->pdev;
+	int event_id = DWC_PCIE_EVENT_ID(event);
 	u16 ras_des_offset = pcie_pmu->ras_des_offset;
 	u32 val;
 
+	if (pdev->vendor == PCI_VENDOR_ID_ROCKCHIP)
+		pci_write_config_dword(pdev, ras_des_offset + DWC_PCIE_EVENT_CNT_CTL,
+				       event_id << 16);
+
 	pci_read_config_dword(pdev, ras_des_offset + DWC_PCIE_EVENT_CNT_DATA, &val);
 
 	return val;
-- 
2.7.4

Re: [PATCH v3 1/2] PCI: Add Rockchip vendor ID

[Bjorn Helgaas]

On Fri, Dec 13, 2024 at 12:24:02PM +0800, Shawn Lin wrote:
> This patch moves PCI_VENDOR_ID_ROCKCHIP from pci_endpoint_test.c to
> pci_ids.h. And reuse it in pcie-rockchip-host.c.
> 
> Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
> Cc: Krzysztof Wilczynski <kw@linux.com>
> Cc: Lorenzo Pieralisi <lpieralisi@kernel.org>
> Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>

Acked-by: Bjorn Helgaas <bhelgaas@google.com>

> ---
> 
> Changes in v3:
> - add commit log and reuse this ID for more places
> 
> Changes in v2: None
> 
>  drivers/misc/pci_endpoint_test.c            | 1 -
>  drivers/pci/controller/pcie-rockchip-host.c | 2 +-
>  drivers/pci/controller/pcie-rockchip.h      | 1 -
>  include/linux/pci_ids.h                     | 2 ++
>  4 files changed, 3 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/misc/pci_endpoint_test.c b/drivers/misc/pci_endpoint_test.c
> index 3aaaf47..b5c8422 100644
> --- a/drivers/misc/pci_endpoint_test.c
> +++ b/drivers/misc/pci_endpoint_test.c
> @@ -85,7 +85,6 @@
>  #define PCI_DEVICE_ID_RENESAS_R8A774E1		0x0025
>  #define PCI_DEVICE_ID_RENESAS_R8A779F0		0x0031
>  
> -#define PCI_VENDOR_ID_ROCKCHIP			0x1d87
>  #define PCI_DEVICE_ID_ROCKCHIP_RK3588		0x3588
>  
>  static DEFINE_IDA(pci_endpoint_test_ida);
> diff --git a/drivers/pci/controller/pcie-rockchip-host.c b/drivers/pci/controller/pcie-rockchip-host.c
> index 5adac6a..6a46be1 100644
> --- a/drivers/pci/controller/pcie-rockchip-host.c
> +++ b/drivers/pci/controller/pcie-rockchip-host.c
> @@ -367,7 +367,7 @@ static int rockchip_pcie_host_init_port(struct rockchip_pcie *rockchip)
>  		}
>  	}
>  
> -	rockchip_pcie_write(rockchip, ROCKCHIP_VENDOR_ID,
> +	rockchip_pcie_write(rockchip, PCI_VENDOR_ID_ROCKCHIP,
>  			    PCIE_CORE_CONFIG_VENDOR);
>  	rockchip_pcie_write(rockchip,
>  			    PCI_CLASS_BRIDGE_PCI_NORMAL << 8,
> diff --git a/drivers/pci/controller/pcie-rockchip.h b/drivers/pci/controller/pcie-rockchip.h
> index a51b087..f9eaac9 100644
> --- a/drivers/pci/controller/pcie-rockchip.h
> +++ b/drivers/pci/controller/pcie-rockchip.h
> @@ -198,7 +198,6 @@
>  #define AXI_WRAPPER_NOR_MSG			0xc
>  
>  #define PCIE_RC_SEND_PME_OFF			0x11960
> -#define ROCKCHIP_VENDOR_ID			0x1d87
>  #define PCIE_LINK_IS_L2(x) \
>  	(((x) & PCIE_CLIENT_DEBUG_LTSSM_MASK) == PCIE_CLIENT_DEBUG_LTSSM_L2)
>  #define PCIE_LINK_TRAINING_DONE(x) \
> diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h
> index d2402bf..6f68267 100644
> --- a/include/linux/pci_ids.h
> +++ b/include/linux/pci_ids.h
> @@ -2604,6 +2604,8 @@
>  
>  #define PCI_VENDOR_ID_ZHAOXIN		0x1d17
>  
> +#define PCI_VENDOR_ID_ROCKCHIP		0x1d87
> +
>  #define PCI_VENDOR_ID_HYGON		0x1d94
>  
>  #define PCI_VENDOR_ID_META		0x1d9b
> -- 
> 2.7.4
> 

Re: [PATCH v3 2/2] perf/dwc_pcie: Add support for Rockchip SoCs

[Shuai Xue]

在 2024/12/13 12:24, Shawn Lin 写道:
> Add support for Rockchip SoCs by adding vendor ID to the vendor list.
> And fix the lane-event based enable/disable/read process which is slightly
> different on Rockchip SoCs, by checking vendor ID.
> 
> Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
> 
> ---
> 
> Changes in v3: None
> Changes in v2:
> - rebase on Bejorn's new patch about Qualifing VSEC Capability by Vendor, Revision
> 
>   drivers/perf/dwc_pcie_pmu.c | 22 ++++++++++++++++++++++
>   1 file changed, 22 insertions(+)
> 
> diff --git a/drivers/perf/dwc_pcie_pmu.c b/drivers/perf/dwc_pcie_pmu.c
> index d022f49..ba6d5116 100644
> --- a/drivers/perf/dwc_pcie_pmu.c
> +++ b/drivers/perf/dwc_pcie_pmu.c
> @@ -116,6 +116,8 @@ static const struct dwc_pcie_pmu_vsec_id dwc_pcie_pmu_vsec_ids[] = {
>   	  .vsec_id = 0x02, .vsec_rev = 0x4 },
>   	{ .vendor_id = PCI_VENDOR_ID_QCOM,
>   	  .vsec_id = 0x02, .vsec_rev = 0x4 },
> +	{ .vendor_id = PCI_VENDOR_ID_ROCKCHIP,
> +	  .vsec_id = 0x02, .vsec_rev = 0x4 },
>   	{} /* terminator */
>   };
>   
> @@ -264,12 +266,27 @@ static const struct attribute_group *dwc_pcie_attr_groups[] = {
>   	NULL
>   };
>   
> +static void dwc_pcie_pmu_lane_event_enable_for_rk(struct pci_dev *pdev,
> +						  u16 ras_des_offset,
> +						  bool enable)
> +{
> +	if (enable)
> +		pci_write_config_dword(pdev, ras_des_offset + DWC_PCIE_EVENT_CNT_CTL,
> +				DWC_PCIE_CNT_ENABLE | DWC_PCIE_PER_EVENT_ON);

DWC_PCIE_CNT_ENABLE is a bit mask,

     #define DWC_PCIE_CNT_ENABLE			GENMASK(4, 2)
     #define DWC_PCIE_PER_EVENT_ON			0x3

so, DWC_PCIE_CNT_ENABLE | DWC_PCIE_PER_EVENT_ON == DWC_PCIE_CNT_ENABLE.

what value do you really intend to set here?


> +	else
> +		pci_clear_and_set_config_dword(pdev, ras_des_offset + DWC_PCIE_EVENT_CNT_CTL,
> +				DWC_PCIE_CNT_ENABLE, DWC_PCIE_PER_EVENT_ON);

It is really weird that DWC_PCIE_PER_EVENT_ON mean disable.
Does 0x3 in the register data book for ROCKCHIP means "per event off"?

The register data book from my hand:

     - 0x1 (PER_EVENT_OFF): per event off
     - 0x3 (PER_EVENT_ON): per event on

> +}
> +
>   static void dwc_pcie_pmu_lane_event_enable(struct dwc_pcie_pmu *pcie_pmu,
>   					   bool enable)
>   {
>   	struct pci_dev *pdev = pcie_pmu->pdev;
>   	u16 ras_des_offset = pcie_pmu->ras_des_offset;
>   
> +	if (pdev->vendor == PCI_VENDOR_ID_ROCKCHIP)
> +		return dwc_pcie_pmu_lane_event_enable_for_rk(pdev, ras_des_offset, enable);
> +
>   	if (enable)
>   		pci_clear_and_set_config_dword(pdev,
>   					ras_des_offset + DWC_PCIE_EVENT_CNT_CTL,
> @@ -295,9 +312,14 @@ static u64 dwc_pcie_pmu_read_lane_event_counter(struct perf_event *event)
>   {
>   	struct dwc_pcie_pmu *pcie_pmu = to_dwc_pcie_pmu(event->pmu);
>   	struct pci_dev *pdev = pcie_pmu->pdev;
> +	int event_id = DWC_PCIE_EVENT_ID(event);
>   	u16 ras_des_offset = pcie_pmu->ras_des_offset;
>   	u32 val;
>   
> +	if (pdev->vendor == PCI_VENDOR_ID_ROCKCHIP)
> +		pci_write_config_dword(pdev, ras_des_offset + DWC_PCIE_EVENT_CNT_CTL,
> +				       event_id << 16);

I think dwc_pcie_pmu_event_add() has done the same work to set the event id.

Best Regards,
Shuai