[PATCH v2 0/2] Add support for PCIe RP PERST#

[PATCH v2 0/2] Add support for PCIe RP PERST#

[Sai Krishna Musham]

Add support for PCIe Root Port PERST# signal.

Add `reset-gpios` property to the Versal CPM PCIe controller binding.

Sai Krishna Musham (2):
  dt-bindings: PCI: xilinx-cpm: Add reset-gpios for PCIe RP PERST#
  PCI: xilinx-cpm: Add support for PCIe RP PERST# signal

 .../bindings/pci/xilinx-versal-cpm.yaml       |  7 ++++++
 drivers/pci/controller/pcie-xilinx-cpm.c      | 23 +++++++++++++++++++
 2 files changed, 30 insertions(+)

-- 
2.44.1

[PATCH v2 1/2] dt-bindings: PCI: xilinx-cpm: Add reset-gpios for PCIe RP PERST#

[Sai Krishna Musham]

Introduce `reset-gpios` property to enable GPIO-based control of
the PCIe RP PERST# signal, generating assert and deassert signals.

Traditionally, the reset was managed in hardware and enabled during
initialization. With this patch set, the reset will be handled by the
driver. Consequently, the `reset-gpios` property must be explicitly
provided to ensure proper functionality.

Signed-off-by: Sai Krishna Musham <sai.krishna.musham@amd.com>
---
This patch depends on the following patch series.
https://lore.kernel.org/all/20250217072713.635643-2-thippeswamy.havalige@amd.com/

Changes for v2:
- Add define from include/dt-bindings/gpio/gpio.h for PERST# polarity
- Update commit message
---
 .../devicetree/bindings/pci/xilinx-versal-cpm.yaml         | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml b/Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml
index b63a759ec2d7..6aaeb76f498b 100644
--- a/Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml
+++ b/Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml
@@ -33,6 +33,9 @@ properties:
       - const: cpm_csr
     minItems: 2
 
+  reset-gpios:
+    description: GPIO used as PERST# signal. Please refer to pci.txt.
+
   interrupts:
     maxItems: 1
 
@@ -63,6 +66,7 @@ properties:
 required:
   - reg
   - reg-names
+  - reset-gpios
   - "#interrupt-cells"
   - interrupts
   - interrupt-map
@@ -75,6 +79,7 @@ unevaluatedProperties: false
 
 examples:
   - |
+    #include <dt-bindings/gpio/gpio.h>
 
     versal {
                #address-cells = <2>;
@@ -99,6 +104,7 @@ examples:
                        reg = <0x0 0xfca10000 0x0 0x1000>,
                              <0x6 0x00000000 0x0 0x10000000>;
                        reg-names = "cpm_slcr", "cfg";
+                       reset-gpios = <&gpio1 38 GPIO_ACTIVE_LOW>;
                        pcie_intc_0: interrupt-controller {
                                #address-cells = <0>;
                                #interrupt-cells = <1>;
@@ -127,6 +133,7 @@ examples:
                              <0x06 0x00000000 0x00 0x1000000>,
                              <0x00 0xfce20000 0x00 0x1000000>;
                        reg-names = "cpm_slcr", "cfg", "cpm_csr";
+                       reset-gpios = <&gpio1 38 GPIO_ACTIVE_LOW>;
 
                        pcie_intc_1: interrupt-controller {
                                #address-cells = <0>;
-- 
2.44.1

[PATCH v2 2/2] PCI: xilinx-cpm: Add support for PCIe RP PERST# signal

[Sai Krishna Musham]

Add GPIO-based control for the PCIe Root Port PERST# signal.

According to section 2.2 of the PCIe Electromechanical Specification
(Revision 6.0), PERST# signal has to be deasserted after a delay of
100 ms (TPVPERL) to ensure proper reset sequencing during PCIe
initialization.

Adapt to use the GPIO framework and make reset optional to keep DTB
backward compatibility.

Signed-off-by: Sai Krishna Musham <sai.krishna.musham@amd.com>
---
This patch depends on the following patch series.
https://lore.kernel.org/all/20250217072713.635643-3-thippeswamy.havalige@amd.com/

Changes for v2:
- Make the request GPIO optional.
- Correct the reset sequence as per PERST#
- Update commit message
---
 drivers/pci/controller/pcie-xilinx-cpm.c | 23 +++++++++++++++++++++++
 1 file changed, 23 insertions(+)

diff --git a/drivers/pci/controller/pcie-xilinx-cpm.c b/drivers/pci/controller/pcie-xilinx-cpm.c
index 81e8bfae53d0..aa0c61d30049 100644
--- a/drivers/pci/controller/pcie-xilinx-cpm.c
+++ b/drivers/pci/controller/pcie-xilinx-cpm.c
@@ -6,6 +6,8 @@
  */
 
 #include <linux/bitfield.h>
+#include <linux/delay.h>
+#include <linux/gpio/consumer.h>
 #include <linux/interrupt.h>
 #include <linux/irq.h>
 #include <linux/irqchip.h>
@@ -568,8 +570,29 @@ static int xilinx_cpm_pcie_probe(struct platform_device *pdev)
 	struct device *dev = &pdev->dev;
 	struct pci_host_bridge *bridge;
 	struct resource_entry *bus;
+	struct gpio_desc *reset_gpio;
 	int err;
 
+	/* Request the GPIO for PCIe reset signal */
+	reset_gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_HIGH);
+	if (IS_ERR(reset_gpio)) {
+		dev_err(dev, "Failed to request reset GPIO\n");
+		return PTR_ERR(reset_gpio);
+	}
+
+	/* Assert the reset signal */
+	gpiod_set_value(reset_gpio, 1);
+
+	/*
+	 * As per section 2.2 of the PCI Express Card Electromechanical
+	 * Specification (Revision 6.0), the deassertion of the PERST# signal
+	 * should be delayed by 100 ms (TPVPERL).
+	 */
+	msleep(100);
+
+	/* Deassert the reset signal */
+	gpiod_set_value(reset_gpio, 0);
+
 	bridge = devm_pci_alloc_host_bridge(dev, sizeof(*port));
 	if (!bridge)
 		return -ENODEV;
-- 
2.44.1

Re: [PATCH v2 2/2] PCI: xilinx-cpm: Add support for PCIe RP PERST# signal

[Bjorn Helgaas]

On Wed, Feb 26, 2025 at 06:13:58PM +0530, Sai Krishna Musham wrote:
> Add GPIO-based control for the PCIe Root Port PERST# signal.
> 
> According to section 2.2 of the PCIe Electromechanical Specification
> (Revision 6.0), PERST# signal has to be deasserted after a delay of
> 100 ms (TPVPERL) to ensure proper reset sequencing during PCIe
> initialization.
> 
> Adapt to use the GPIO framework and make reset optional to keep DTB
> backward compatibility.
> 
> Signed-off-by: Sai Krishna Musham <sai.krishna.musham@amd.com>
> ---
> This patch depends on the following patch series.
> https://lore.kernel.org/all/20250217072713.635643-3-thippeswamy.havalige@amd.com/
> 
> Changes for v2:
> - Make the request GPIO optional.
> - Correct the reset sequence as per PERST#
> - Update commit message
> ---
>  drivers/pci/controller/pcie-xilinx-cpm.c | 23 +++++++++++++++++++++++
>  1 file changed, 23 insertions(+)
> 
> diff --git a/drivers/pci/controller/pcie-xilinx-cpm.c b/drivers/pci/controller/pcie-xilinx-cpm.c
> index 81e8bfae53d0..aa0c61d30049 100644
> --- a/drivers/pci/controller/pcie-xilinx-cpm.c
> +++ b/drivers/pci/controller/pcie-xilinx-cpm.c
> @@ -6,6 +6,8 @@
>   */
>  
>  #include <linux/bitfield.h>
> +#include <linux/delay.h>
> +#include <linux/gpio/consumer.h>
>  #include <linux/interrupt.h>
>  #include <linux/irq.h>
>  #include <linux/irqchip.h>
> @@ -568,8 +570,29 @@ static int xilinx_cpm_pcie_probe(struct platform_device *pdev)
>  	struct device *dev = &pdev->dev;
>  	struct pci_host_bridge *bridge;
>  	struct resource_entry *bus;
> +	struct gpio_desc *reset_gpio;
>  	int err;
>  
> +	/* Request the GPIO for PCIe reset signal */
> +	reset_gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_HIGH);
> +	if (IS_ERR(reset_gpio)) {
> +		dev_err(dev, "Failed to request reset GPIO\n");
> +		return PTR_ERR(reset_gpio);
> +	}
> +
> +	/* Assert the reset signal */
> +	gpiod_set_value(reset_gpio, 1);
> +
> +	/*
> +	 * As per section 2.2 of the PCI Express Card Electromechanical
> +	 * Specification (Revision 6.0), the deassertion of the PERST# signal
> +	 * should be delayed by 100 ms (TPVPERL).
> +	 */
> +	msleep(100);

Use PCIE_T_PVPERL_MS.  The comment at that #define is probably enough.

> +	/* Deassert the reset signal */
> +	gpiod_set_value(reset_gpio, 0);
> +
>  	bridge = devm_pci_alloc_host_bridge(dev, sizeof(*port));
>  	if (!bridge)
>  		return -ENODEV;
> -- 
> 2.44.1
>