Linux PCI subsystem development
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From: Bjorn Helgaas <helgaas@kernel.org>
To: Huacai Chen <chenhuacai@loongson.cn>
Cc: "Bjorn Helgaas" <bhelgaas@google.com>,
	"Lorenzo Pieralisi" <lorenzo.pieralisi@arm.com>,
	"Krzysztof Wilczyński" <kw@linux.com>,
	"Rob Herring" <robh@kernel.org>,
	linux-pci@vger.kernel.org, "Jianmin Lv" <lvjianmin@loongson.cn>,
	"Xuefeng Li" <lixuefeng@loongson.cn>,
	"Huacai Chen" <chenhuacai@gmail.com>,
	"Jiaxun Yang" <jiaxun.yang@flygoat.com>,
	stable@vger.kernel.org, "Xianglai Li" <lixianglai@loongson.cn>
Subject: Re: [PATCH V2] PCI: Add ACS quirk for Loongson PCIe
Date: Thu, 17 Apr 2025 15:28:06 -0500	[thread overview]
Message-ID: <20250417202806.GA127187@bhelgaas> (raw)
In-Reply-To: <20250403040756.720409-1-chenhuacai@loongson.cn>

On Thu, Apr 03, 2025 at 12:07:56PM +0800, Huacai Chen wrote:
> Loongson PCIe Root Ports don't advertise an ACS capability, but they do
> not allow peer-to-peer transactions between Root Ports. Add an ACS quirk
> so each Root Port can be in a separate IOMMU group.
> 
> Cc: stable@vger.kernel.org
> Signed-off-by: Xianglai Li <lixianglai@loongson.cn>
> Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>

Applied to pci/virtualization for v6.16, thanks!

> ---
> V2: Add more device ids.
> 
>  drivers/pci/quirks.c | 23 +++++++++++++++++++++++
>  1 file changed, 23 insertions(+)
> 
> diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
> index 8d610c17e0f2..eee96ad03614 100644
> --- a/drivers/pci/quirks.c
> +++ b/drivers/pci/quirks.c
> @@ -4995,6 +4995,18 @@ static int pci_quirk_brcm_acs(struct pci_dev *dev, u16 acs_flags)
>  		PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF);
>  }
>  
> +static int pci_quirk_loongson_acs(struct pci_dev *dev, u16 acs_flags)
> +{
> +	/*
> +	 * Loongson PCIe Root Ports don't advertise an ACS capability, but
> +	 * they do not allow peer-to-peer transactions between Root Ports.
> +	 * Allow each Root Port to be in a separate IOMMU group by masking
> +	 * SV/RR/CR/UF bits.
> +	 */
> +	return pci_acs_ctrl_enabled(acs_flags,
> +		PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF);
> +}
> +
>  /*
>   * Wangxun 40G/25G/10G/1G NICs have no ACS capability, but on
>   * multi-function devices, the hardware isolates the functions by
> @@ -5128,6 +5140,17 @@ static const struct pci_dev_acs_enabled {
>  	{ PCI_VENDOR_ID_BROADCOM, 0x1762, pci_quirk_mf_endpoint_acs },
>  	{ PCI_VENDOR_ID_BROADCOM, 0x1763, pci_quirk_mf_endpoint_acs },
>  	{ PCI_VENDOR_ID_BROADCOM, 0xD714, pci_quirk_brcm_acs },
> +	/* Loongson PCIe Root Ports */
> +	{ PCI_VENDOR_ID_LOONGSON, 0x3C09, pci_quirk_loongson_acs },
> +	{ PCI_VENDOR_ID_LOONGSON, 0x3C19, pci_quirk_loongson_acs },
> +	{ PCI_VENDOR_ID_LOONGSON, 0x3C29, pci_quirk_loongson_acs },
> +	{ PCI_VENDOR_ID_LOONGSON, 0x7A09, pci_quirk_loongson_acs },
> +	{ PCI_VENDOR_ID_LOONGSON, 0x7A19, pci_quirk_loongson_acs },
> +	{ PCI_VENDOR_ID_LOONGSON, 0x7A29, pci_quirk_loongson_acs },
> +	{ PCI_VENDOR_ID_LOONGSON, 0x7A39, pci_quirk_loongson_acs },
> +	{ PCI_VENDOR_ID_LOONGSON, 0x7A49, pci_quirk_loongson_acs },
> +	{ PCI_VENDOR_ID_LOONGSON, 0x7A59, pci_quirk_loongson_acs },
> +	{ PCI_VENDOR_ID_LOONGSON, 0x7A69, pci_quirk_loongson_acs },
>  	/* Amazon Annapurna Labs */
>  	{ PCI_VENDOR_ID_AMAZON_ANNAPURNA_LABS, 0x0031, pci_quirk_al_acs },
>  	/* Zhaoxin multi-function devices */
> -- 
> 2.47.1
> 

      parent reply	other threads:[~2025-04-17 20:28 UTC|newest]

Thread overview: 3+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-04-03  4:07 [PATCH V2] PCI: Add ACS quirk for Loongson PCIe Huacai Chen
2025-04-14 13:50 ` Huacai Chen
2025-04-17 20:28 ` Bjorn Helgaas [this message]

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