* [PATCH v11 1/6] PCI: Introduce generic bus config read helper function
2025-05-05 16:34 [PATCH v11 0/6] Refactor capability search into common macros Hans Zhang
@ 2025-05-05 16:34 ` Hans Zhang
2025-05-05 16:34 ` [PATCH v11 2/6] PCI: Clean up __pci_find_next_cap_ttl() readability Hans Zhang
` (4 subsequent siblings)
5 siblings, 0 replies; 10+ messages in thread
From: Hans Zhang @ 2025-05-05 16:34 UTC (permalink / raw)
To: lpieralisi, bhelgaas, manivannan.sadhasivam, ilpo.jarvinen, kw
Cc: cassel, robh, jingoohan1, linux-pci, linux-kernel, Hans Zhang
The primary PCI config space accessors are tied to the size of the read
(byte/word/dword). Upcoming refactoring of PCI capability discovery logic
requires passing a config accessor function that must be able to perform
read with different sizes.
Add any size config space read accessor pci_bus_read_config() to allow
giving it as the config space accessor to the upcoming PCI capability
discovery macro.
Reconstructs the PCI function discovery logic to prepare for unified
configuration of access modes. No function changes are intended.
Signed-off-by: Hans Zhang <18255117159@163.com>
---
Changes since v9 ~ v10:
- None
Changes since v8:
- The new split is patch 1/6.
- The patch commit message were modified.
---
drivers/pci/access.c | 17 +++++++++++++++++
drivers/pci/pci.h | 2 ++
2 files changed, 19 insertions(+)
diff --git a/drivers/pci/access.c b/drivers/pci/access.c
index b123da16b63b..603332658ab3 100644
--- a/drivers/pci/access.c
+++ b/drivers/pci/access.c
@@ -85,6 +85,23 @@ EXPORT_SYMBOL(pci_bus_write_config_byte);
EXPORT_SYMBOL(pci_bus_write_config_word);
EXPORT_SYMBOL(pci_bus_write_config_dword);
+int pci_bus_read_config(void *priv, unsigned int devfn, int where, u32 size,
+ u32 *val)
+{
+ struct pci_bus *bus = priv;
+ int ret;
+
+ if (size == 1)
+ ret = pci_bus_read_config_byte(bus, devfn, where, (u8 *)val);
+ else if (size == 2)
+ ret = pci_bus_read_config_word(bus, devfn, where, (u16 *)val);
+ else
+ ret = pci_bus_read_config_dword(bus, devfn, where, val);
+
+ return ret;
+}
+EXPORT_SYMBOL_GPL(pci_bus_read_config);
+
int pci_generic_config_read(struct pci_bus *bus, unsigned int devfn,
int where, int size, u32 *val)
{
diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h
index b81e99cd4b62..5e1477d6e254 100644
--- a/drivers/pci/pci.h
+++ b/drivers/pci/pci.h
@@ -88,6 +88,8 @@ extern bool pci_early_dump;
bool pcie_cap_has_lnkctl(const struct pci_dev *dev);
bool pcie_cap_has_lnkctl2(const struct pci_dev *dev);
bool pcie_cap_has_rtctl(const struct pci_dev *dev);
+int pci_bus_read_config(void *priv, unsigned int devfn, int where, u32 size,
+ u32 *val);
/* Functions internal to the PCI core code */
--
2.25.1
^ permalink raw reply related [flat|nested] 10+ messages in thread* [PATCH v11 2/6] PCI: Clean up __pci_find_next_cap_ttl() readability
2025-05-05 16:34 [PATCH v11 0/6] Refactor capability search into common macros Hans Zhang
2025-05-05 16:34 ` [PATCH v11 1/6] PCI: Introduce generic bus config read helper function Hans Zhang
@ 2025-05-05 16:34 ` Hans Zhang
2025-05-05 16:34 ` [PATCH v11 3/6] PCI: Refactor capability search into common macros Hans Zhang
` (3 subsequent siblings)
5 siblings, 0 replies; 10+ messages in thread
From: Hans Zhang @ 2025-05-05 16:34 UTC (permalink / raw)
To: lpieralisi, bhelgaas, manivannan.sadhasivam, ilpo.jarvinen, kw
Cc: cassel, robh, jingoohan1, linux-pci, linux-kernel, Hans Zhang
Refactor the __pci_find_next_cap_ttl() to improve code clarity:
- Replace magic number 0x40 with PCI_STD_HEADER_SIZEOF.
- Use ALIGN_DOWN() for position alignment instead of manual bitmask.
- Extract PCI capability fields via FIELD_GET() with standardized masks.
- Add necessary headers (linux/align.h).
The changes are purely non-functional cleanups, ensuring behavior remains
identical to the original implementation.
Signed-off-by: Hans Zhang <18255117159@163.com>
---
Changes since v10:
- Remove #include <uapi/linux/pci_regs.h> and add macro definition comments.
Changes since v9:
- None
Changes since v8:
- Split into patch 1/6, patch 2/6.
- The
---
drivers/pci/pci.c | 9 +++++----
include/uapi/linux/pci_regs.h | 2 ++
2 files changed, 7 insertions(+), 4 deletions(-)
diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
index e77d5b53c0ce..27d2adb18a30 100644
--- a/drivers/pci/pci.c
+++ b/drivers/pci/pci.c
@@ -9,6 +9,7 @@
*/
#include <linux/acpi.h>
+#include <linux/align.h>
#include <linux/kernel.h>
#include <linux/delay.h>
#include <linux/dmi.h>
@@ -432,17 +433,17 @@ static u8 __pci_find_next_cap_ttl(struct pci_bus *bus, unsigned int devfn,
pci_bus_read_config_byte(bus, devfn, pos, &pos);
while ((*ttl)--) {
- if (pos < 0x40)
+ if (pos < PCI_STD_HEADER_SIZEOF)
break;
- pos &= ~3;
+ pos = ALIGN_DOWN(pos, 4);
pci_bus_read_config_word(bus, devfn, pos, &ent);
- id = ent & 0xff;
+ id = FIELD_GET(PCI_CAP_ID_MASK, ent);
if (id == 0xff)
break;
if (id == cap)
return pos;
- pos = (ent >> 8);
+ pos = FIELD_GET(PCI_CAP_LIST_NEXT_MASK, ent);
}
return 0;
}
diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h
index ba326710f9c8..35051f9ac16a 100644
--- a/include/uapi/linux/pci_regs.h
+++ b/include/uapi/linux/pci_regs.h
@@ -206,6 +206,8 @@
/* 0x48-0x7f reserved */
/* Capability lists */
+#define PCI_CAP_ID_MASK 0x00ff /* Capability ID mask */
+#define PCI_CAP_LIST_NEXT_MASK 0xff00 /* Next Capability Pointer mask */
#define PCI_CAP_LIST_ID 0 /* Capability ID */
#define PCI_CAP_ID_PM 0x01 /* Power Management */
--
2.25.1
^ permalink raw reply related [flat|nested] 10+ messages in thread* [PATCH v11 3/6] PCI: Refactor capability search into common macros
2025-05-05 16:34 [PATCH v11 0/6] Refactor capability search into common macros Hans Zhang
2025-05-05 16:34 ` [PATCH v11 1/6] PCI: Introduce generic bus config read helper function Hans Zhang
2025-05-05 16:34 ` [PATCH v11 2/6] PCI: Clean up __pci_find_next_cap_ttl() readability Hans Zhang
@ 2025-05-05 16:34 ` Hans Zhang
2025-05-05 16:34 ` [PATCH v11 4/6] PCI: dwc: Use common PCI host bridge APIs for finding the capabilities Hans Zhang
` (2 subsequent siblings)
5 siblings, 0 replies; 10+ messages in thread
From: Hans Zhang @ 2025-05-05 16:34 UTC (permalink / raw)
To: lpieralisi, bhelgaas, manivannan.sadhasivam, ilpo.jarvinen, kw
Cc: cassel, robh, jingoohan1, linux-pci, linux-kernel, Hans Zhang
The PCI Capability search functionality is duplicated across the PCI core
and several controller drivers. The core's current implementation requires
fully initialized PCI device and bus structures, which prevents controller
drivers from using it during early initialization phases before these
structures are available.
Move the Capability search logic into a header-based macro that accepts a
config space accessor function as an argument. This enables controller
drivers to perform Capability discovery using their early access
mechanisms prior to full device initialization while sharing the
Capability search code.
Convert the existing PCI core Capability search implementation to use this
new macro. Controller drivers can later use the same macros with their
early access mechanisms while maintaining the existing protection against
infinite loops through preserved TTL checks.
The ttl parameter was originally an additional safeguard to prevent
infinite loops in corrupted config space. However, the
PCI_FIND_NEXT_CAP_TTL macro already enforces a TTL limit internally.
Removing redundant ttl handling simplifies the interface while maintaining
the safety guarantee. This aligns with the macro's design intent of
encapsulating TTL management.
Signed-off-by: Hans Zhang <18255117159@163.com>
---
Changes since v10:
- Remove #include <uapi/linux/pci_regs.h>.
- The patch commit message were modified.
Changes since v9:
- None
Changes since v8:
- The patch commit message were modified.
---
drivers/pci/pci.c | 69 +++++---------------------------------
drivers/pci/pci.h | 85 +++++++++++++++++++++++++++++++++++++++++++++++
2 files changed, 94 insertions(+), 60 deletions(-)
diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
index 27d2adb18a30..271d922abdcc 100644
--- a/drivers/pci/pci.c
+++ b/drivers/pci/pci.c
@@ -9,7 +9,6 @@
*/
#include <linux/acpi.h>
-#include <linux/align.h>
#include <linux/kernel.h>
#include <linux/delay.h>
#include <linux/dmi.h>
@@ -425,35 +424,16 @@ static int pci_dev_str_match(struct pci_dev *dev, const char *p,
}
static u8 __pci_find_next_cap_ttl(struct pci_bus *bus, unsigned int devfn,
- u8 pos, int cap, int *ttl)
+ u8 pos, int cap)
{
- u8 id;
- u16 ent;
-
- pci_bus_read_config_byte(bus, devfn, pos, &pos);
-
- while ((*ttl)--) {
- if (pos < PCI_STD_HEADER_SIZEOF)
- break;
- pos = ALIGN_DOWN(pos, 4);
- pci_bus_read_config_word(bus, devfn, pos, &ent);
-
- id = FIELD_GET(PCI_CAP_ID_MASK, ent);
- if (id == 0xff)
- break;
- if (id == cap)
- return pos;
- pos = FIELD_GET(PCI_CAP_LIST_NEXT_MASK, ent);
- }
- return 0;
+ return PCI_FIND_NEXT_CAP_TTL(pci_bus_read_config, pos, cap, bus,
+ devfn);
}
static u8 __pci_find_next_cap(struct pci_bus *bus, unsigned int devfn,
u8 pos, int cap)
{
- int ttl = PCI_FIND_CAP_TTL;
-
- return __pci_find_next_cap_ttl(bus, devfn, pos, cap, &ttl);
+ return __pci_find_next_cap_ttl(bus, devfn, pos, cap);
}
u8 pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap)
@@ -554,42 +534,11 @@ EXPORT_SYMBOL(pci_bus_find_capability);
*/
u16 pci_find_next_ext_capability(struct pci_dev *dev, u16 start, int cap)
{
- u32 header;
- int ttl;
- u16 pos = PCI_CFG_SPACE_SIZE;
-
- /* minimum 8 bytes per capability */
- ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8;
-
if (dev->cfg_size <= PCI_CFG_SPACE_SIZE)
return 0;
- if (start)
- pos = start;
-
- if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
- return 0;
-
- /*
- * If we have no capabilities, this is indicated by cap ID,
- * cap version and next pointer all being 0.
- */
- if (header == 0)
- return 0;
-
- while (ttl-- > 0) {
- if (PCI_EXT_CAP_ID(header) == cap && pos != start)
- return pos;
-
- pos = PCI_EXT_CAP_NEXT(header);
- if (pos < PCI_CFG_SPACE_SIZE)
- break;
-
- if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
- break;
- }
-
- return 0;
+ return PCI_FIND_NEXT_EXT_CAPABILITY(pci_bus_read_config, start, cap,
+ dev->bus, dev->devfn);
}
EXPORT_SYMBOL_GPL(pci_find_next_ext_capability);
@@ -649,7 +598,7 @@ EXPORT_SYMBOL_GPL(pci_get_dsn);
static u8 __pci_find_next_ht_cap(struct pci_dev *dev, u8 pos, int ht_cap)
{
- int rc, ttl = PCI_FIND_CAP_TTL;
+ int rc;
u8 cap, mask;
if (ht_cap == HT_CAPTYPE_SLAVE || ht_cap == HT_CAPTYPE_HOST)
@@ -658,7 +607,7 @@ static u8 __pci_find_next_ht_cap(struct pci_dev *dev, u8 pos, int ht_cap)
mask = HT_5BIT_CAP_MASK;
pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn, pos,
- PCI_CAP_ID_HT, &ttl);
+ PCI_CAP_ID_HT);
while (pos) {
rc = pci_read_config_byte(dev, pos + 3, &cap);
if (rc != PCIBIOS_SUCCESSFUL)
@@ -669,7 +618,7 @@ static u8 __pci_find_next_ht_cap(struct pci_dev *dev, u8 pos, int ht_cap)
pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn,
pos + PCI_CAP_LIST_NEXT,
- PCI_CAP_ID_HT, &ttl);
+ PCI_CAP_ID_HT);
}
return 0;
diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h
index 5e1477d6e254..9d512d37301b 100644
--- a/drivers/pci/pci.h
+++ b/drivers/pci/pci.h
@@ -2,6 +2,7 @@
#ifndef DRIVERS_PCI_H
#define DRIVERS_PCI_H
+#include <linux/align.h>
#include <linux/pci.h>
struct pcie_tlp_log;
@@ -91,6 +92,90 @@ bool pcie_cap_has_rtctl(const struct pci_dev *dev);
int pci_bus_read_config(void *priv, unsigned int devfn, int where, u32 size,
u32 *val);
+/* Standard Capability finder */
+/**
+ * PCI_FIND_NEXT_CAP_TTL - Find a PCI standard capability
+ * @read_cfg: Function pointer for reading PCI config space
+ * @start: Starting position to begin search
+ * @cap: Capability ID to find
+ * @args: Arguments to pass to read_cfg function
+ *
+ * Iterates through the capability list in PCI config space to find
+ * the specified capability. Implements TTL (time-to-live) protection
+ * against infinite loops.
+ *
+ * Returns: Position of the capability if found, 0 otherwise.
+ */
+#define PCI_FIND_NEXT_CAP_TTL(read_cfg, start, cap, args...) \
+({ \
+ int __ttl = PCI_FIND_CAP_TTL; \
+ u8 __id, __found_pos = 0; \
+ u8 __pos = (start); \
+ u16 __ent; \
+ \
+ read_cfg(args, __pos, 1, (u32 *)&__pos); \
+ \
+ while (__ttl--) { \
+ if (__pos < PCI_STD_HEADER_SIZEOF) \
+ break; \
+ \
+ __pos = ALIGN_DOWN(__pos, 4); \
+ read_cfg(args, __pos, 2, (u32 *)&__ent); \
+ \
+ __id = FIELD_GET(PCI_CAP_ID_MASK, __ent); \
+ if (__id == 0xff) \
+ break; \
+ \
+ if (__id == (cap)) { \
+ __found_pos = __pos; \
+ break; \
+ } \
+ \
+ __pos = FIELD_GET(PCI_CAP_LIST_NEXT_MASK, __ent); \
+ } \
+ __found_pos; \
+})
+
+/* Extended Capability finder */
+/**
+ * PCI_FIND_NEXT_EXT_CAPABILITY - Find a PCI extended capability
+ * @read_cfg: Function pointer for reading PCI config space
+ * @start: Starting position to begin search (0 for initial search)
+ * @cap: Extended capability ID to find
+ * @args: Arguments to pass to read_cfg function
+ *
+ * Searches the extended capability space in PCI config registers
+ * for the specified capability. Implements TTL protection against
+ * infinite loops using a calculated maximum search count.
+ *
+ * Returns: Position of the capability if found, 0 otherwise.
+ */
+#define PCI_FIND_NEXT_EXT_CAPABILITY(read_cfg, start, cap, args...) \
+({ \
+ u16 __pos = (start) ?: PCI_CFG_SPACE_SIZE; \
+ u16 __found_pos = 0; \
+ int __ttl, __ret; \
+ u32 __header; \
+ \
+ __ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8; \
+ while (__ttl-- > 0 && __pos >= PCI_CFG_SPACE_SIZE) { \
+ __ret = read_cfg(args, __pos, 4, &__header); \
+ if (__ret != PCIBIOS_SUCCESSFUL) \
+ break; \
+ \
+ if (__header == 0) \
+ break; \
+ \
+ if (PCI_EXT_CAP_ID(__header) == (cap) && __pos != start) { \
+ __found_pos = __pos; \
+ break; \
+ } \
+ \
+ __pos = PCI_EXT_CAP_NEXT(__header); \
+ } \
+ __found_pos; \
+})
+
/* Functions internal to the PCI core code */
#ifdef CONFIG_DMI
--
2.25.1
^ permalink raw reply related [flat|nested] 10+ messages in thread* [PATCH v11 4/6] PCI: dwc: Use common PCI host bridge APIs for finding the capabilities
2025-05-05 16:34 [PATCH v11 0/6] Refactor capability search into common macros Hans Zhang
` (2 preceding siblings ...)
2025-05-05 16:34 ` [PATCH v11 3/6] PCI: Refactor capability search into common macros Hans Zhang
@ 2025-05-05 16:34 ` Hans Zhang
2025-05-09 12:49 ` kernel test robot
2025-05-05 16:34 ` [PATCH v11 5/6] PCI: cadence: " Hans Zhang
2025-05-05 16:34 ` [PATCH v11 6/6] PCI: cadence: Use cdns_pcie_find_*capability to avoid hardcode Hans Zhang
5 siblings, 1 reply; 10+ messages in thread
From: Hans Zhang @ 2025-05-05 16:34 UTC (permalink / raw)
To: lpieralisi, bhelgaas, manivannan.sadhasivam, ilpo.jarvinen, kw
Cc: cassel, robh, jingoohan1, linux-pci, linux-kernel, Hans Zhang
Use the PCI core is now exposing generic macros for the host bridges to
search for the PCIe capabilities, make use of them in the DWC driver.
Signed-off-by: Hans Zhang <18255117159@163.com>
---
Changes since v10:
- None
Changes since v9:
- Resolved [v9 4/6] compilation error.
The latest 6.15 rc1 merge __dw_pcie_find_vsec_capability, which uses
dw_pcie_find_next_ext_capability.
Changes since v8:
- None
Changes since v7:
- Resolve compilation errors.
Changes since v6:
https://lore.kernel.org/linux-pci/20250323164852.430546-3-18255117159@163.com/
- The patch commit message were modified.
Changes since v5:
https://lore.kernel.org/linux-pci/20250321163803.391056-3-18255117159@163.com/
- Kconfig add "select PCI_HOST_HELPERS"
---
drivers/pci/controller/dwc/pcie-designware.c | 76 +++-----------------
1 file changed, 9 insertions(+), 67 deletions(-)
diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c
index 97d76d3dc066..837188f579a2 100644
--- a/drivers/pci/controller/dwc/pcie-designware.c
+++ b/drivers/pci/controller/dwc/pcie-designware.c
@@ -205,83 +205,25 @@ void dw_pcie_version_detect(struct dw_pcie *pci)
pci->type = ver;
}
-/*
- * These interfaces resemble the pci_find_*capability() interfaces, but these
- * are for configuring host controllers, which are bridges *to* PCI devices but
- * are not PCI devices themselves.
- */
-static u8 __dw_pcie_find_next_cap(struct dw_pcie *pci, u8 cap_ptr,
- u8 cap)
+static int dw_pcie_read_cfg(void *priv, int where, int size, u32 *val)
{
- u8 cap_id, next_cap_ptr;
- u16 reg;
-
- if (!cap_ptr)
- return 0;
-
- reg = dw_pcie_readw_dbi(pci, cap_ptr);
- cap_id = (reg & 0x00ff);
-
- if (cap_id > PCI_CAP_ID_MAX)
- return 0;
+ struct dw_pcie *pci = priv;
- if (cap_id == cap)
- return cap_ptr;
+ *val = dw_pcie_read_dbi(pci, where, size);
- next_cap_ptr = (reg & 0xff00) >> 8;
- return __dw_pcie_find_next_cap(pci, next_cap_ptr, cap);
+ return PCIBIOS_SUCCESSFUL;
}
u8 dw_pcie_find_capability(struct dw_pcie *pci, u8 cap)
{
- u8 next_cap_ptr;
- u16 reg;
-
- reg = dw_pcie_readw_dbi(pci, PCI_CAPABILITY_LIST);
- next_cap_ptr = (reg & 0x00ff);
-
- return __dw_pcie_find_next_cap(pci, next_cap_ptr, cap);
+ return PCI_FIND_NEXT_CAP_TTL(dw_pcie_read_cfg, PCI_CAPABILITY_LIST, cap,
+ pci);
}
EXPORT_SYMBOL_GPL(dw_pcie_find_capability);
-static u16 dw_pcie_find_next_ext_capability(struct dw_pcie *pci, u16 start,
- u8 cap)
-{
- u32 header;
- int ttl;
- int pos = PCI_CFG_SPACE_SIZE;
-
- /* minimum 8 bytes per capability */
- ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8;
-
- if (start)
- pos = start;
-
- header = dw_pcie_readl_dbi(pci, pos);
- /*
- * If we have no capabilities, this is indicated by cap ID,
- * cap version and next pointer all being 0.
- */
- if (header == 0)
- return 0;
-
- while (ttl-- > 0) {
- if (PCI_EXT_CAP_ID(header) == cap && pos != start)
- return pos;
-
- pos = PCI_EXT_CAP_NEXT(header);
- if (pos < PCI_CFG_SPACE_SIZE)
- break;
-
- header = dw_pcie_readl_dbi(pci, pos);
- }
-
- return 0;
-}
-
u16 dw_pcie_find_ext_capability(struct dw_pcie *pci, u8 cap)
{
- return dw_pcie_find_next_ext_capability(pci, 0, cap);
+ return PCI_FIND_NEXT_EXT_CAPABILITY(dw_pcie_read_cfg, 0, cap, pci);
}
EXPORT_SYMBOL_GPL(dw_pcie_find_ext_capability);
@@ -294,8 +236,8 @@ static u16 __dw_pcie_find_vsec_capability(struct dw_pcie *pci, u16 vendor_id,
if (vendor_id != dw_pcie_readw_dbi(pci, PCI_VENDOR_ID))
return 0;
- while ((vsec = dw_pcie_find_next_ext_capability(pci, vsec,
- PCI_EXT_CAP_ID_VNDR))) {
+ while ((vsec = PCI_FIND_NEXT_EXT_CAPABILITY(
+ dw_pcie_read_cfg, vsec, PCI_EXT_CAP_ID_VNDR, pci))) {
header = dw_pcie_readl_dbi(pci, vsec + PCI_VNDR_HEADER);
if (PCI_VNDR_HEADER_ID(header) == vsec_id)
return vsec;
--
2.25.1
^ permalink raw reply related [flat|nested] 10+ messages in thread* Re: [PATCH v11 4/6] PCI: dwc: Use common PCI host bridge APIs for finding the capabilities
2025-05-05 16:34 ` [PATCH v11 4/6] PCI: dwc: Use common PCI host bridge APIs for finding the capabilities Hans Zhang
@ 2025-05-09 12:49 ` kernel test robot
2025-05-09 16:57 ` Hans Zhang
0 siblings, 1 reply; 10+ messages in thread
From: kernel test robot @ 2025-05-09 12:49 UTC (permalink / raw)
To: Hans Zhang, lpieralisi, bhelgaas, manivannan.sadhasivam,
ilpo.jarvinen, kw
Cc: oe-kbuild-all, cassel, robh, jingoohan1, linux-pci, linux-kernel,
Hans Zhang
Hi Hans,
kernel test robot noticed the following build warnings:
[auto build test WARNING on ca91b9500108d4cf083a635c2e11c884d5dd20ea]
url: https://github.com/intel-lab-lkp/linux/commits/Hans-Zhang/PCI-Introduce-generic-bus-config-read-helper-function/20250506-004221
base: ca91b9500108d4cf083a635c2e11c884d5dd20ea
patch link: https://lore.kernel.org/r/20250505163420.198012-5-18255117159%40163.com
patch subject: [PATCH v11 4/6] PCI: dwc: Use common PCI host bridge APIs for finding the capabilities
config: parisc-randconfig-r063-20250509 (https://download.01.org/0day-ci/archive/20250509/202505092036.Sw8SstSY-lkp@intel.com/config)
compiler: hppa-linux-gcc (GCC) 14.2.0
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20250509/202505092036.Sw8SstSY-lkp@intel.com/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202505092036.Sw8SstSY-lkp@intel.com/
All warnings (new ones prefixed by >>):
In function 'dw_pcie_read_cfg',
inlined from 'dw_pcie_find_capability' at drivers/pci/controller/dwc/pcie-designware.c:219:9:
>> drivers/pci/controller/dwc/pcie-designware.c:212:14: warning: write of 32-bit data outside the bound of destination object, data truncated into 8-bit [-Wextra]
212 | *val = dw_pcie_read_dbi(pci, where, size);
| ~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
vim +212 drivers/pci/controller/dwc/pcie-designware.c
207
208 static int dw_pcie_read_cfg(void *priv, int where, int size, u32 *val)
209 {
210 struct dw_pcie *pci = priv;
211
> 212 *val = dw_pcie_read_dbi(pci, where, size);
213
214 return PCIBIOS_SUCCESSFUL;
215 }
216
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
^ permalink raw reply [flat|nested] 10+ messages in thread* Re: [PATCH v11 4/6] PCI: dwc: Use common PCI host bridge APIs for finding the capabilities
2025-05-09 12:49 ` kernel test robot
@ 2025-05-09 16:57 ` Hans Zhang
0 siblings, 0 replies; 10+ messages in thread
From: Hans Zhang @ 2025-05-09 16:57 UTC (permalink / raw)
To: kernel test robot, lpieralisi, bhelgaas, manivannan.sadhasivam,
ilpo.jarvinen, kw
Cc: oe-kbuild-all, cassel, robh, jingoohan1, linux-pci, linux-kernel
On 2025/5/9 20:49, kernel test robot wrote:
> Hi Hans,
>
> kernel test robot noticed the following build warnings:
>
> [auto build test WARNING on ca91b9500108d4cf083a635c2e11c884d5dd20ea]
>
> url: https://github.com/intel-lab-lkp/linux/commits/Hans-Zhang/PCI-Introduce-generic-bus-config-read-helper-function/20250506-004221
> base: ca91b9500108d4cf083a635c2e11c884d5dd20ea
> patch link: https://lore.kernel.org/r/20250505163420.198012-5-18255117159%40163.com
> patch subject: [PATCH v11 4/6] PCI: dwc: Use common PCI host bridge APIs for finding the capabilities
> config: parisc-randconfig-r063-20250509 (https://download.01.org/0day-ci/archive/20250509/202505092036.Sw8SstSY-lkp@intel.com/config)
> compiler: hppa-linux-gcc (GCC) 14.2.0
> reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20250509/202505092036.Sw8SstSY-lkp@intel.com/reproduce)
>
> If you fix the issue in a separate patch/commit (i.e. not just a new version of
> the same patch/commit), kindly add following tags
> | Reported-by: kernel test robot <lkp@intel.com>
> | Closes: https://lore.kernel.org/oe-kbuild-all/202505092036.Sw8SstSY-lkp@intel.com/
>
> All warnings (new ones prefixed by >>):
>
> In function 'dw_pcie_read_cfg',
> inlined from 'dw_pcie_find_capability' at drivers/pci/controller/dwc/pcie-designware.c:219:9:
>>> drivers/pci/controller/dwc/pcie-designware.c:212:14: warning: write of 32-bit data outside the bound of destination object, data truncated into 8-bit [-Wextra]
> 212 | *val = dw_pcie_read_dbi(pci, where, size);
> | ~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
>
>
> vim +212 drivers/pci/controller/dwc/pcie-designware.c
>
> 207
> 208 static int dw_pcie_read_cfg(void *priv, int where, int size, u32 *val)
> 209 {
> 210 struct dw_pcie *pci = priv;
> 211
> > 212 *val = dw_pcie_read_dbi(pci, where, size);
> 213
> 214 return PCIBIOS_SUCCESSFUL;
> 215 }
> 216
>
Dear Maintainers,
I don't know why the warning here is. I think the return value of
dw_pcie_read_dbi, whether u8/u16, will be automatically and forcibly
converted to u32.
The following files have similar uses:
drivers/pci/controller/dwc/pci-exynos.c
static int exynos_pcie_rd_own_conf(struct pci_bus *bus, unsigned int devfn,
int where, int size, u32 *val)
{
struct dw_pcie *pci = to_dw_pcie_from_pp(bus->sysdata);
if (PCI_SLOT(devfn))
return PCIBIOS_DEVICE_NOT_FOUND;
*val = dw_pcie_read_dbi(pci, where, size);
return PCIBIOS_SUCCESSFUL;
}
drivers/pci/controller/dwc/pcie-histb.c
static int histb_pcie_rd_own_conf(struct pci_bus *bus, unsigned int devfn,
int where, int size, u32 *val)
{
struct dw_pcie *pci = to_dw_pcie_from_pp(bus->sysdata);
if (PCI_SLOT(devfn))
return PCIBIOS_DEVICE_NOT_FOUND;
*val = dw_pcie_read_dbi(pci, where, size);
return PCIBIOS_SUCCESSFUL;
}
drivers/pci/controller/dwc/pcie-kirin.c
static int kirin_pcie_rd_own_conf(struct pci_bus *bus, unsigned int devfn,
int where, int size, u32 *val)
{
struct dw_pcie *pci = to_dw_pcie_from_pp(bus->sysdata);
if (PCI_SLOT(devfn))
return PCIBIOS_DEVICE_NOT_FOUND;
*val = dw_pcie_read_dbi(pci, where, size);
return PCIBIOS_SUCCESSFUL;
}
drivers/pci/access.c
int pci_generic_config_read(struct pci_bus *bus, unsigned int devfn,
int where, int size, u32 *val)
{
void __iomem *addr;
addr = bus->ops->map_bus(bus, devfn, where);
if (!addr)
return PCIBIOS_DEVICE_NOT_FOUND;
if (size == 1)
*val = readb(addr);
else if (size == 2)
*val = readw(addr);
else
*val = readl(addr);
return PCIBIOS_SUCCESSFUL;
}
EXPORT_SYMBOL_GPL(pci_generic_config_read);
May I ignore this warning? Could it be that I misunderstood something?
Best regards,
Hans
^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH v11 5/6] PCI: cadence: Use common PCI host bridge APIs for finding the capabilities
2025-05-05 16:34 [PATCH v11 0/6] Refactor capability search into common macros Hans Zhang
` (3 preceding siblings ...)
2025-05-05 16:34 ` [PATCH v11 4/6] PCI: dwc: Use common PCI host bridge APIs for finding the capabilities Hans Zhang
@ 2025-05-05 16:34 ` Hans Zhang
2025-05-13 8:06 ` kernel test robot
2025-05-05 16:34 ` [PATCH v11 6/6] PCI: cadence: Use cdns_pcie_find_*capability to avoid hardcode Hans Zhang
5 siblings, 1 reply; 10+ messages in thread
From: Hans Zhang @ 2025-05-05 16:34 UTC (permalink / raw)
To: lpieralisi, bhelgaas, manivannan.sadhasivam, ilpo.jarvinen, kw
Cc: cassel, robh, jingoohan1, linux-pci, linux-kernel, Hans Zhang
Use the PCI core is now exposing generic macros for the host bridges to
search for the PCIe capabilities, make use of them in the CDNS driver.
Signed-off-by: Hans Zhang <18255117159@163.com>
---
Changes since v8 ~ v10:
- None
Changes since v7:
- Resolve compilation errors.
Changes since v6:
https://lore.kernel.org/linux-pci/20250323164852.430546-4-18255117159@163.com/
- The patch commit message were modified.
Changes since v5:
https://lore.kernel.org/linux-pci/20250321163803.391056-4-18255117159@163.com
- Kconfig add "select PCI_HOST_HELPERS"
---
drivers/pci/controller/cadence/pcie-cadence.c | 28 +++++++++++++++++++
drivers/pci/controller/cadence/pcie-cadence.h | 13 +++++++++
2 files changed, 41 insertions(+)
diff --git a/drivers/pci/controller/cadence/pcie-cadence.c b/drivers/pci/controller/cadence/pcie-cadence.c
index 204e045aed8c..ca4a1a809fcb 100644
--- a/drivers/pci/controller/cadence/pcie-cadence.c
+++ b/drivers/pci/controller/cadence/pcie-cadence.c
@@ -7,6 +7,34 @@
#include <linux/of.h>
#include "pcie-cadence.h"
+#include "../../pci.h"
+
+static int cdns_pcie_read_cfg(void *priv, int where, int size, u32 *val)
+{
+ struct cdns_pcie *pcie = priv;
+
+ if (size == 4)
+ *val = cdns_pcie_readl(pcie, where);
+ else if (size == 2)
+ *val = cdns_pcie_readw(pcie, where);
+ else if (size == 1)
+ *val = cdns_pcie_readb(pcie, where);
+
+ return PCIBIOS_SUCCESSFUL;
+}
+
+u8 cdns_pcie_find_capability(struct cdns_pcie *pcie, u8 cap)
+{
+ return PCI_FIND_NEXT_CAP_TTL(cdns_pcie_read_cfg, PCI_CAPABILITY_LIST,
+ cap, pcie);
+}
+EXPORT_SYMBOL_GPL(cdns_pcie_find_capability);
+
+u16 cdns_pcie_find_ext_capability(struct cdns_pcie *pcie, u8 cap)
+{
+ return PCI_FIND_NEXT_EXT_CAPABILITY(cdns_pcie_read_cfg, 0, cap, pcie);
+}
+EXPORT_SYMBOL_GPL(cdns_pcie_find_ext_capability);
void cdns_pcie_detect_quiet_min_delay_set(struct cdns_pcie *pcie)
{
diff --git a/drivers/pci/controller/cadence/pcie-cadence.h b/drivers/pci/controller/cadence/pcie-cadence.h
index 39ee9945c903..56d6a0e73eb7 100644
--- a/drivers/pci/controller/cadence/pcie-cadence.h
+++ b/drivers/pci/controller/cadence/pcie-cadence.h
@@ -398,6 +398,16 @@ static inline u32 cdns_pcie_readl(struct cdns_pcie *pcie, u32 reg)
return readl(pcie->reg_base + reg);
}
+static inline u32 cdns_pcie_readw(struct cdns_pcie *pcie, u32 reg)
+{
+ return readw(pcie->reg_base + reg);
+}
+
+static inline u32 cdns_pcie_readb(struct cdns_pcie *pcie, u32 reg)
+{
+ return readb(pcie->reg_base + reg);
+}
+
static inline u32 cdns_pcie_read_sz(void __iomem *addr, int size)
{
void __iomem *aligned_addr = PTR_ALIGN_DOWN(addr, 0x4);
@@ -557,6 +567,9 @@ static inline int cdns_pcie_ep_setup(struct cdns_pcie_ep *ep)
}
#endif
+u8 cdns_pcie_find_capability(struct cdns_pcie *pcie, u8 cap);
+u16 cdns_pcie_find_ext_capability(struct cdns_pcie *pcie, u8 cap);
+
void cdns_pcie_detect_quiet_min_delay_set(struct cdns_pcie *pcie);
void cdns_pcie_set_outbound_region(struct cdns_pcie *pcie, u8 busnr, u8 fn,
--
2.25.1
^ permalink raw reply related [flat|nested] 10+ messages in thread* Re: [PATCH v11 5/6] PCI: cadence: Use common PCI host bridge APIs for finding the capabilities
2025-05-05 16:34 ` [PATCH v11 5/6] PCI: cadence: " Hans Zhang
@ 2025-05-13 8:06 ` kernel test robot
0 siblings, 0 replies; 10+ messages in thread
From: kernel test robot @ 2025-05-13 8:06 UTC (permalink / raw)
To: Hans Zhang, lpieralisi, bhelgaas, manivannan.sadhasivam,
ilpo.jarvinen, kw
Cc: oe-kbuild-all, cassel, robh, jingoohan1, linux-pci, linux-kernel,
Hans Zhang
Hi Hans,
kernel test robot noticed the following build errors:
[auto build test ERROR on ca91b9500108d4cf083a635c2e11c884d5dd20ea]
url: https://github.com/intel-lab-lkp/linux/commits/Hans-Zhang/PCI-Introduce-generic-bus-config-read-helper-function/20250506-004221
base: ca91b9500108d4cf083a635c2e11c884d5dd20ea
patch link: https://lore.kernel.org/r/20250505163420.198012-6-18255117159%40163.com
patch subject: [PATCH v11 5/6] PCI: cadence: Use common PCI host bridge APIs for finding the capabilities
config: csky-randconfig-001-20250513 (https://download.01.org/0day-ci/archive/20250513/202505131520.uEv4I92o-lkp@intel.com/config)
compiler: csky-linux-gcc (GCC) 14.2.0
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20250513/202505131520.uEv4I92o-lkp@intel.com/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202505131520.uEv4I92o-lkp@intel.com/
All errors (new ones prefixed by >>):
In file included from drivers/pci/controller/cadence/pcie-cadence.c:10:
drivers/pci/controller/cadence/pcie-cadence.c: In function 'cdns_pcie_find_capability':
>> drivers/pci/controller/cadence/../../pci.h:125:24: error: implicit declaration of function 'FIELD_GET' [-Wimplicit-function-declaration]
125 | __id = FIELD_GET(PCI_CAP_ID_MASK, __ent); \
| ^~~~~~~~~
drivers/pci/controller/cadence/pcie-cadence.c:28:16: note: in expansion of macro 'PCI_FIND_NEXT_CAP_TTL'
28 | return PCI_FIND_NEXT_CAP_TTL(cdns_pcie_read_cfg, PCI_CAPABILITY_LIST,
| ^~~~~~~~~~~~~~~~~~~~~
vim +/FIELD_GET +125 drivers/pci/controller/cadence/../../pci.h
343e51ae6e3f64 Jacob Keller 2013-07-31 88
7a1562d4f2d017 Yinghai Lu 2014-11-11 89 bool pcie_cap_has_lnkctl(const struct pci_dev *dev);
503fa23614dc95 Maciej W. Rozycki 2022-09-17 90 bool pcie_cap_has_lnkctl2(const struct pci_dev *dev);
af65d1ad416bc6 Patel, Mayurkumar 2019-10-18 91 bool pcie_cap_has_rtctl(const struct pci_dev *dev);
5f06abead7cb8c Hans Zhang 2025-05-06 92 int pci_bus_read_config(void *priv, unsigned int devfn, int where, u32 size,
5f06abead7cb8c Hans Zhang 2025-05-06 93 u32 *val);
7a1562d4f2d017 Yinghai Lu 2014-11-11 94
db69afa296b68c Hans Zhang 2025-05-06 95 /* Standard Capability finder */
db69afa296b68c Hans Zhang 2025-05-06 96 /**
db69afa296b68c Hans Zhang 2025-05-06 97 * PCI_FIND_NEXT_CAP_TTL - Find a PCI standard capability
db69afa296b68c Hans Zhang 2025-05-06 98 * @read_cfg: Function pointer for reading PCI config space
db69afa296b68c Hans Zhang 2025-05-06 99 * @start: Starting position to begin search
db69afa296b68c Hans Zhang 2025-05-06 100 * @cap: Capability ID to find
db69afa296b68c Hans Zhang 2025-05-06 101 * @args: Arguments to pass to read_cfg function
db69afa296b68c Hans Zhang 2025-05-06 102 *
db69afa296b68c Hans Zhang 2025-05-06 103 * Iterates through the capability list in PCI config space to find
db69afa296b68c Hans Zhang 2025-05-06 104 * the specified capability. Implements TTL (time-to-live) protection
db69afa296b68c Hans Zhang 2025-05-06 105 * against infinite loops.
db69afa296b68c Hans Zhang 2025-05-06 106 *
db69afa296b68c Hans Zhang 2025-05-06 107 * Returns: Position of the capability if found, 0 otherwise.
db69afa296b68c Hans Zhang 2025-05-06 108 */
db69afa296b68c Hans Zhang 2025-05-06 109 #define PCI_FIND_NEXT_CAP_TTL(read_cfg, start, cap, args...) \
db69afa296b68c Hans Zhang 2025-05-06 110 ({ \
db69afa296b68c Hans Zhang 2025-05-06 111 int __ttl = PCI_FIND_CAP_TTL; \
db69afa296b68c Hans Zhang 2025-05-06 112 u8 __id, __found_pos = 0; \
db69afa296b68c Hans Zhang 2025-05-06 113 u8 __pos = (start); \
db69afa296b68c Hans Zhang 2025-05-06 114 u16 __ent; \
db69afa296b68c Hans Zhang 2025-05-06 115 \
db69afa296b68c Hans Zhang 2025-05-06 116 read_cfg(args, __pos, 1, (u32 *)&__pos); \
db69afa296b68c Hans Zhang 2025-05-06 117 \
db69afa296b68c Hans Zhang 2025-05-06 118 while (__ttl--) { \
db69afa296b68c Hans Zhang 2025-05-06 119 if (__pos < PCI_STD_HEADER_SIZEOF) \
db69afa296b68c Hans Zhang 2025-05-06 120 break; \
db69afa296b68c Hans Zhang 2025-05-06 121 \
db69afa296b68c Hans Zhang 2025-05-06 122 __pos = ALIGN_DOWN(__pos, 4); \
db69afa296b68c Hans Zhang 2025-05-06 123 read_cfg(args, __pos, 2, (u32 *)&__ent); \
db69afa296b68c Hans Zhang 2025-05-06 124 \
db69afa296b68c Hans Zhang 2025-05-06 @125 __id = FIELD_GET(PCI_CAP_ID_MASK, __ent); \
db69afa296b68c Hans Zhang 2025-05-06 126 if (__id == 0xff) \
db69afa296b68c Hans Zhang 2025-05-06 127 break; \
db69afa296b68c Hans Zhang 2025-05-06 128 \
db69afa296b68c Hans Zhang 2025-05-06 129 if (__id == (cap)) { \
db69afa296b68c Hans Zhang 2025-05-06 130 __found_pos = __pos; \
db69afa296b68c Hans Zhang 2025-05-06 131 break; \
db69afa296b68c Hans Zhang 2025-05-06 132 } \
db69afa296b68c Hans Zhang 2025-05-06 133 \
db69afa296b68c Hans Zhang 2025-05-06 134 __pos = FIELD_GET(PCI_CAP_LIST_NEXT_MASK, __ent); \
db69afa296b68c Hans Zhang 2025-05-06 135 } \
db69afa296b68c Hans Zhang 2025-05-06 136 __found_pos; \
db69afa296b68c Hans Zhang 2025-05-06 137 })
db69afa296b68c Hans Zhang 2025-05-06 138
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH v11 6/6] PCI: cadence: Use cdns_pcie_find_*capability to avoid hardcode.
2025-05-05 16:34 [PATCH v11 0/6] Refactor capability search into common macros Hans Zhang
` (4 preceding siblings ...)
2025-05-05 16:34 ` [PATCH v11 5/6] PCI: cadence: " Hans Zhang
@ 2025-05-05 16:34 ` Hans Zhang
5 siblings, 0 replies; 10+ messages in thread
From: Hans Zhang @ 2025-05-05 16:34 UTC (permalink / raw)
To: lpieralisi, bhelgaas, manivannan.sadhasivam, ilpo.jarvinen, kw
Cc: cassel, robh, jingoohan1, linux-pci, linux-kernel, Hans Zhang
The PCIe capability/extended capability offsets are not guaranteed to be
the same across all SoCs integrating the Cadence PCIe IP. Hence, use the
cdns_pcie_find_{ext}_capability() APIs for finding them.
This avoids hardcoding the offsets in the driver.
Signed-off-by: Hans Zhang <18255117159@163.com>
---
Changes since v8 ~ v10:
- None
Changes since v7:
- Resolve compilation errors.
Changes since v6:
https://lore.kernel.org/linux-pci/20250323164852.430546-4-18255117159@163.com/
- The patch commit message were modified.
Changes since v5:
https://lore.kernel.org/linux-pci/20250321163803.391056-4-18255117159@163.com
- Kconfig add "select PCI_HOST_HELPERS"
---
.../pci/controller/cadence/pcie-cadence-ep.c | 40 +++++++++++--------
drivers/pci/controller/cadence/pcie-cadence.h | 5 ---
2 files changed, 23 insertions(+), 22 deletions(-)
diff --git a/drivers/pci/controller/cadence/pcie-cadence-ep.c b/drivers/pci/controller/cadence/pcie-cadence-ep.c
index 599ec4b1223e..5c4b2151d181 100644
--- a/drivers/pci/controller/cadence/pcie-cadence-ep.c
+++ b/drivers/pci/controller/cadence/pcie-cadence-ep.c
@@ -19,12 +19,13 @@
static u8 cdns_pcie_get_fn_from_vfn(struct cdns_pcie *pcie, u8 fn, u8 vfn)
{
- u32 cap = CDNS_PCIE_EP_FUNC_SRIOV_CAP_OFFSET;
u32 first_vf_offset, stride;
+ u16 cap;
if (vfn == 0)
return fn;
+ cap = cdns_pcie_find_ext_capability(pcie, PCI_EXT_CAP_ID_SRIOV);
first_vf_offset = cdns_pcie_ep_fn_readw(pcie, fn, cap + PCI_SRIOV_VF_OFFSET);
stride = cdns_pcie_ep_fn_readw(pcie, fn, cap + PCI_SRIOV_VF_STRIDE);
fn = fn + first_vf_offset + ((vfn - 1) * stride);
@@ -36,10 +37,11 @@ static int cdns_pcie_ep_write_header(struct pci_epc *epc, u8 fn, u8 vfn,
struct pci_epf_header *hdr)
{
struct cdns_pcie_ep *ep = epc_get_drvdata(epc);
- u32 cap = CDNS_PCIE_EP_FUNC_SRIOV_CAP_OFFSET;
struct cdns_pcie *pcie = &ep->pcie;
u32 reg;
+ u16 cap;
+ cap = cdns_pcie_find_ext_capability(pcie, PCI_EXT_CAP_ID_SRIOV);
if (vfn > 1) {
dev_err(&epc->dev, "Only Virtual Function #1 has deviceID\n");
return -EINVAL;
@@ -224,9 +226,10 @@ static int cdns_pcie_ep_set_msi(struct pci_epc *epc, u8 fn, u8 vfn, u8 mmc)
{
struct cdns_pcie_ep *ep = epc_get_drvdata(epc);
struct cdns_pcie *pcie = &ep->pcie;
- u32 cap = CDNS_PCIE_EP_FUNC_MSI_CAP_OFFSET;
u16 flags;
+ u8 cap;
+ cap = cdns_pcie_find_capability(pcie, PCI_CAP_ID_MSI);
fn = cdns_pcie_get_fn_from_vfn(pcie, fn, vfn);
/*
@@ -246,9 +249,10 @@ static int cdns_pcie_ep_get_msi(struct pci_epc *epc, u8 fn, u8 vfn)
{
struct cdns_pcie_ep *ep = epc_get_drvdata(epc);
struct cdns_pcie *pcie = &ep->pcie;
- u32 cap = CDNS_PCIE_EP_FUNC_MSI_CAP_OFFSET;
u16 flags, mme;
+ u8 cap;
+ cap = cdns_pcie_find_capability(pcie, PCI_CAP_ID_MSI);
fn = cdns_pcie_get_fn_from_vfn(pcie, fn, vfn);
/* Validate that the MSI feature is actually enabled. */
@@ -269,9 +273,10 @@ static int cdns_pcie_ep_get_msix(struct pci_epc *epc, u8 func_no, u8 vfunc_no)
{
struct cdns_pcie_ep *ep = epc_get_drvdata(epc);
struct cdns_pcie *pcie = &ep->pcie;
- u32 cap = CDNS_PCIE_EP_FUNC_MSIX_CAP_OFFSET;
u32 val, reg;
+ u8 cap;
+ cap = cdns_pcie_find_capability(pcie, PCI_CAP_ID_MSIX);
func_no = cdns_pcie_get_fn_from_vfn(pcie, func_no, vfunc_no);
reg = cap + PCI_MSIX_FLAGS;
@@ -290,9 +295,10 @@ static int cdns_pcie_ep_set_msix(struct pci_epc *epc, u8 fn, u8 vfn,
{
struct cdns_pcie_ep *ep = epc_get_drvdata(epc);
struct cdns_pcie *pcie = &ep->pcie;
- u32 cap = CDNS_PCIE_EP_FUNC_MSIX_CAP_OFFSET;
u32 val, reg;
+ u8 cap;
+ cap = cdns_pcie_find_capability(pcie, PCI_CAP_ID_MSIX);
fn = cdns_pcie_get_fn_from_vfn(pcie, fn, vfn);
reg = cap + PCI_MSIX_FLAGS;
@@ -378,11 +384,11 @@ static int cdns_pcie_ep_send_msi_irq(struct cdns_pcie_ep *ep, u8 fn, u8 vfn,
u8 interrupt_num)
{
struct cdns_pcie *pcie = &ep->pcie;
- u32 cap = CDNS_PCIE_EP_FUNC_MSI_CAP_OFFSET;
u16 flags, mme, data, data_mask;
- u8 msi_count;
u64 pci_addr, pci_addr_mask = 0xff;
+ u8 msi_count, cap;
+ cap = cdns_pcie_find_capability(pcie, PCI_CAP_ID_MSI);
fn = cdns_pcie_get_fn_from_vfn(pcie, fn, vfn);
/* Check whether the MSI feature has been enabled by the PCI host. */
@@ -430,14 +436,14 @@ static int cdns_pcie_ep_map_msi_irq(struct pci_epc *epc, u8 fn, u8 vfn,
u32 *msi_addr_offset)
{
struct cdns_pcie_ep *ep = epc_get_drvdata(epc);
- u32 cap = CDNS_PCIE_EP_FUNC_MSI_CAP_OFFSET;
struct cdns_pcie *pcie = &ep->pcie;
u64 pci_addr, pci_addr_mask = 0xff;
u16 flags, mme, data, data_mask;
- u8 msi_count;
+ u8 msi_count, cap;
int ret;
int i;
+ cap = cdns_pcie_find_capability(pcie, PCI_CAP_ID_MSI);
fn = cdns_pcie_get_fn_from_vfn(pcie, fn, vfn);
/* Check whether the MSI feature has been enabled by the PCI host. */
@@ -480,16 +486,16 @@ static int cdns_pcie_ep_map_msi_irq(struct pci_epc *epc, u8 fn, u8 vfn,
static int cdns_pcie_ep_send_msix_irq(struct cdns_pcie_ep *ep, u8 fn, u8 vfn,
u16 interrupt_num)
{
- u32 cap = CDNS_PCIE_EP_FUNC_MSIX_CAP_OFFSET;
u32 tbl_offset, msg_data, reg;
struct cdns_pcie *pcie = &ep->pcie;
struct pci_epf_msix_tbl *msix_tbl;
struct cdns_pcie_epf *epf;
u64 pci_addr_mask = 0xff;
u64 msg_addr;
+ u8 bir, cap;
u16 flags;
- u8 bir;
+ cap = cdns_pcie_find_capability(pcie, PCI_CAP_ID_MSIX);
epf = &ep->epf[fn];
if (vfn > 0)
epf = &epf->epf[vfn - 1];
@@ -563,7 +569,9 @@ static int cdns_pcie_ep_start(struct pci_epc *epc)
int max_epfs = sizeof(epc->function_num_map) * 8;
int ret, epf, last_fn;
u32 reg, value;
+ u8 cap;
+ cap = cdns_pcie_find_capability(pcie, PCI_CAP_ID_EXP);
/*
* BIT(0) is hardwired to 1, hence function 0 is always enabled
* and can't be disabled anyway.
@@ -587,12 +595,10 @@ static int cdns_pcie_ep_start(struct pci_epc *epc)
continue;
value = cdns_pcie_ep_fn_readl(pcie, epf,
- CDNS_PCIE_EP_FUNC_DEV_CAP_OFFSET +
- PCI_EXP_DEVCAP);
+ cap + PCI_EXP_DEVCAP);
value &= ~PCI_EXP_DEVCAP_FLR;
- cdns_pcie_ep_fn_writel(pcie, epf,
- CDNS_PCIE_EP_FUNC_DEV_CAP_OFFSET +
- PCI_EXP_DEVCAP, value);
+ cdns_pcie_ep_fn_writel(pcie, epf, cap + PCI_EXP_DEVCAP,
+ value);
}
}
diff --git a/drivers/pci/controller/cadence/pcie-cadence.h b/drivers/pci/controller/cadence/pcie-cadence.h
index 56d6a0e73eb7..08491275349d 100644
--- a/drivers/pci/controller/cadence/pcie-cadence.h
+++ b/drivers/pci/controller/cadence/pcie-cadence.h
@@ -125,11 +125,6 @@
*/
#define CDNS_PCIE_EP_FUNC_BASE(fn) (((fn) << 12) & GENMASK(19, 12))
-#define CDNS_PCIE_EP_FUNC_MSI_CAP_OFFSET 0x90
-#define CDNS_PCIE_EP_FUNC_MSIX_CAP_OFFSET 0xb0
-#define CDNS_PCIE_EP_FUNC_DEV_CAP_OFFSET 0xc0
-#define CDNS_PCIE_EP_FUNC_SRIOV_CAP_OFFSET 0x200
-
/*
* Endpoint PF Registers
*/
--
2.25.1
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