Linux PCI subsystem development
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From: Randolph Lin <randolph@andestech.com>
To: <linux-kernel@vger.kernel.org>
Cc: <linux-pci@vger.kernel.org>, <linux-riscv@lists.infradead.org>,
	<devicetree@vger.kernel.org>, <jingoohan1@gmail.com>,
	<mani@kernel.org>, <lpieralisi@kernel.org>,
	<kwilczynski@kernel.org>, <robh@kernel.org>,
	<bhelgaas@google.com>, <krzk+dt@kernel.org>,
	<conor+dt@kernel.org>, <alex@ghiti.fr>, <aou@eecs.berkeley.edu>,
	<palmer@dabbelt.com>, <paul.walmsley@sifive.com>,
	<ben717@andestech.com>, <inochiama@gmail.com>,
	<thippeswamy.havalige@amd.com>, <namcao@linutronix.de>,
	<shradha.t@samsung.com>, <randolph.sklin@gmail.com>,
	<tim609@andestech.com>, Randolph Lin <randolph@andestech.com>
Subject: [PATCH v2 1/5] PCI: dwc: Add outbound ATU address range validation callback
Date: Tue, 16 Sep 2025 18:04:13 +0800	[thread overview]
Message-ID: <20250916100417.3036847-2-randolph@andestech.com> (raw)
In-Reply-To: <20250916100417.3036847-1-randolph@andestech.com>

Introduce an optional callback for outbound ATU address range
validation to handle cases that deviate from the generic check.

Signed-off-by: Randolph Lin <randolph@andestech.com>
---
 drivers/pci/controller/dwc/pcie-designware.c | 29 ++++++++++++++++----
 drivers/pci/controller/dwc/pcie-designware.h |  3 ++
 2 files changed, 26 insertions(+), 6 deletions(-)

diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c
index 89aad5a08928..087f9077cf21 100644
--- a/drivers/pci/controller/dwc/pcie-designware.c
+++ b/drivers/pci/controller/dwc/pcie-designware.c
@@ -528,6 +528,28 @@ static inline u32 dw_pcie_enable_ecrc(u32 val)
 	return val | PCIE_ATU_TD;
 }
 
+static
+bool dw_pcie_outbound_atu_addr_valid(struct dw_pcie *pci,
+				     const struct dw_pcie_ob_atu_cfg *atu,
+				     u64 *limit_addr)
+{
+	u64 parent_bus_addr = atu->parent_bus_addr;
+
+	if (pci->ops && pci->ops->outbound_atu_addr_valid)
+		return pci->ops->outbound_atu_addr_valid(pci, atu, limit_addr);
+
+	*limit_addr = parent_bus_addr + atu->size - 1;
+
+	if ((*limit_addr & ~pci->region_limit) !=
+	    (parent_bus_addr & ~pci->region_limit) ||
+	    !IS_ALIGNED(parent_bus_addr, pci->region_align) ||
+	    !IS_ALIGNED(atu->pci_addr, pci->region_align) ||
+	    !atu->size)
+		return false;
+
+	return true;
+}
+
 int dw_pcie_prog_outbound_atu(struct dw_pcie *pci,
 			      const struct dw_pcie_ob_atu_cfg *atu)
 {
@@ -535,13 +557,8 @@ int dw_pcie_prog_outbound_atu(struct dw_pcie *pci,
 	u32 retries, val;
 	u64 limit_addr;
 
-	limit_addr = parent_bus_addr + atu->size - 1;
-
-	if ((limit_addr & ~pci->region_limit) != (parent_bus_addr & ~pci->region_limit) ||
-	    !IS_ALIGNED(parent_bus_addr, pci->region_align) ||
-	    !IS_ALIGNED(atu->pci_addr, pci->region_align) || !atu->size) {
+	if (!dw_pcie_outbound_atu_addr_valid(pci, atu, &limit_addr))
 		return -EINVAL;
-	}
 
 	dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_LOWER_BASE,
 			      lower_32_bits(parent_bus_addr));
diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h
index 00f52d472dcd..6d4805048048 100644
--- a/drivers/pci/controller/dwc/pcie-designware.h
+++ b/drivers/pci/controller/dwc/pcie-designware.h
@@ -469,6 +469,9 @@ struct dw_pcie_ep {
 
 struct dw_pcie_ops {
 	u64	(*cpu_addr_fixup)(struct dw_pcie *pcie, u64 cpu_addr);
+	bool	(*outbound_atu_addr_valid)(struct dw_pcie *pcie,
+					   const struct dw_pcie_ob_atu_cfg *atu,
+					   u64 *limit_addr);
 	u32	(*read_dbi)(struct dw_pcie *pcie, void __iomem *base, u32 reg,
 			    size_t size);
 	void	(*write_dbi)(struct dw_pcie *pcie, void __iomem *base, u32 reg,
-- 
2.34.1


  reply	other threads:[~2025-09-16 10:07 UTC|newest]

Thread overview: 13+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-09-16 10:04 [PATCH v2 0/5] Add support for Andes Qilai SoC PCIe controller Randolph Lin
2025-09-16 10:04 ` Randolph Lin [this message]
2025-09-16 10:04 ` [PATCH v2 2/5] dt-bindings: Add Andes QiLai PCIe support Randolph Lin
2025-09-17 16:38   ` Frank Li
2025-09-17 21:59   ` Bjorn Helgaas
2025-09-16 10:04 ` [PATCH v2 3/5] riscv: dts: andes: Add PCIe node into the QiLai SoC Randolph Lin
2025-09-16 10:04 ` [PATCH v2 4/5] PCI: andes: Add Andes QiLai SoC PCIe host driver support Randolph Lin
2025-09-16 14:46   ` Bjorn Helgaas
2025-09-17 12:16     ` Randolph Lin
2025-09-17 21:57       ` Bjorn Helgaas
2025-09-18 12:54         ` Randolph Lin
2025-09-17  9:52   ` kernel test robot
2025-09-16 10:04 ` [PATCH v2 5/5] MAINTAINERS: Add maintainers for Andes QiLai PCIe driver Randolph Lin

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