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From: kernel test robot <lkp@intel.com>
To: Randolph Lin <randolph@andestech.com>, linux-kernel@vger.kernel.org
Cc: llvm@lists.linux.dev, oe-kbuild-all@lists.linux.dev,
	linux-pci@vger.kernel.org, linux-riscv@lists.infradead.org,
	devicetree@vger.kernel.org, jingoohan1@gmail.com,
	mani@kernel.org, lpieralisi@kernel.org, kwilczynski@kernel.org,
	robh@kernel.org, bhelgaas@google.com, krzk+dt@kernel.org,
	conor+dt@kernel.org, alex@ghiti.fr, aou@eecs.berkeley.edu,
	palmer@dabbelt.com, paul.walmsley@sifive.com,
	ben717@andestech.com, inochiama@gmail.com,
	thippeswamy.havalige@amd.com, namcao@linutronix.de,
	shradha.t@samsung.com, randolph.sklin@gmail.com,
	tim609@andestech.com, Randolph Lin <randolph@andestech.com>
Subject: Re: [PATCH v2 4/5] PCI: andes: Add Andes QiLai SoC PCIe host driver support
Date: Wed, 17 Sep 2025 17:52:16 +0800	[thread overview]
Message-ID: <202509171747.yJ9wsIkH-lkp@intel.com> (raw)
In-Reply-To: <20250916100417.3036847-5-randolph@andestech.com>

Hi Randolph,

kernel test robot noticed the following build warnings:

[auto build test WARNING on pci/next]
[also build test WARNING on pci/for-linus robh/for-next linus/master v6.17-rc6 next-20250916]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]

url:    https://github.com/intel-lab-lkp/linux/commits/Randolph-Lin/PCI-dwc-Add-outbound-ATU-address-range-validation-callback/20250916-180841
base:   https://git.kernel.org/pub/scm/linux/kernel/git/pci/pci.git next
patch link:    https://lore.kernel.org/r/20250916100417.3036847-5-randolph%40andestech.com
patch subject: [PATCH v2 4/5] PCI: andes: Add Andes QiLai SoC PCIe host driver support
config: riscv-allmodconfig (https://download.01.org/0day-ci/archive/20250917/202509171747.yJ9wsIkH-lkp@intel.com/config)
compiler: clang version 22.0.0git (https://github.com/llvm/llvm-project 7c861bcedf61607b6c087380ac711eb7ff918ca6)
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20250917/202509171747.yJ9wsIkH-lkp@intel.com/reproduce)

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202509171747.yJ9wsIkH-lkp@intel.com/

All warnings (new ones prefixed by >>):

   In file included from <built-in>:3:
   In file included from include/linux/compiler_types.h:171:
   include/linux/compiler-clang.h:28:9: warning: '__SANITIZE_ADDRESS__' macro redefined [-Wmacro-redefined]
      28 | #define __SANITIZE_ADDRESS__
         |         ^
   <built-in>:371:9: note: previous definition is here
     371 | #define __SANITIZE_ADDRESS__ 1
         |         ^
>> drivers/pci/controller/dwc/pcie-andes-qilai.c:179:22: warning: variable 'ret' is uninitialized when used here [-Wuninitialized]
     179 |                 dev_err_probe(dev, ret, "Failed to Get APB registers.\n");
         |                                    ^~~
   drivers/pci/controller/dwc/pcie-andes-qilai.c:159:9: note: initialize the variable 'ret' to silence this warning
     159 |         int ret;
         |                ^
         |                 = 0
   2 warnings generated.


vim +/ret +179 drivers/pci/controller/dwc/pcie-andes-qilai.c

   153	
   154	static int qilai_pcie_probe(struct platform_device *pdev)
   155	{
   156		struct qilai_pcie *pcie;
   157		struct dw_pcie *pci;
   158		struct device *dev;
   159		int ret;
   160	
   161		pcie = devm_kzalloc(&pdev->dev, sizeof(*pcie), GFP_KERNEL);
   162		if (!pcie)
   163			return -ENOMEM;
   164	
   165		pcie->pdev = pdev;
   166		platform_set_drvdata(pdev, pcie);
   167	
   168		pci = &pcie->pci;
   169		dev = &pcie->pdev->dev;
   170		pcie->pci.dev = dev;
   171		pcie->pci.ops = &qilai_pcie_ops;
   172		pcie->pci.pp.ops = &qilai_pcie_host_ops;
   173		pci->use_parent_dt_ranges = true;
   174	
   175		dw_pcie_cap_set(&pcie->pci, REQ_RES);
   176	
   177		pcie->apb_base = devm_platform_ioremap_resource_byname(pdev, "apb");
   178		if (IS_ERR(pcie->apb_base)) {
 > 179			dev_err_probe(dev, ret, "Failed to Get APB registers.\n");
   180			return PTR_ERR(pcie->apb_base);
   181		}
   182	
   183		ret = dw_pcie_host_init(&pcie->pci.pp);
   184		if (ret) {
   185			dev_err_probe(dev, ret, "Failed to initialize PCIe host\n");
   186			return ret;
   187		}
   188	
   189		qilai_pcie_iocp_cache_setup(&pcie->pci.pp);
   190	
   191		return 0;
   192	}
   193	

-- 
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki

  parent reply	other threads:[~2025-09-17  9:52 UTC|newest]

Thread overview: 13+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-09-16 10:04 [PATCH v2 0/5] Add support for Andes Qilai SoC PCIe controller Randolph Lin
2025-09-16 10:04 ` [PATCH v2 1/5] PCI: dwc: Add outbound ATU address range validation callback Randolph Lin
2025-09-16 10:04 ` [PATCH v2 2/5] dt-bindings: Add Andes QiLai PCIe support Randolph Lin
2025-09-17 16:38   ` Frank Li
2025-09-17 21:59   ` Bjorn Helgaas
2025-09-16 10:04 ` [PATCH v2 3/5] riscv: dts: andes: Add PCIe node into the QiLai SoC Randolph Lin
2025-09-16 10:04 ` [PATCH v2 4/5] PCI: andes: Add Andes QiLai SoC PCIe host driver support Randolph Lin
2025-09-16 14:46   ` Bjorn Helgaas
2025-09-17 12:16     ` Randolph Lin
2025-09-17 21:57       ` Bjorn Helgaas
2025-09-18 12:54         ` Randolph Lin
2025-09-17  9:52   ` kernel test robot [this message]
2025-09-16 10:04 ` [PATCH v2 5/5] MAINTAINERS: Add maintainers for Andes QiLai PCIe driver Randolph Lin

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