Linux PCI subsystem development
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From: "Ilpo Järvinen" <ilpo.jarvinen@linux.intel.com>
To: linux-pci@vger.kernel.org, "Bjorn Helgaas" <bhelgaas@google.com>,
	"Benjamin Herrenschmidt" <benh@kernel.crashing.org>,
	"Wei Yang" <weiyang@linux.vnet.ibm.com>,
	"Malte Schröder" <malte+lkml@tnxip.de>,
	linux-kernel@vger.kernel.org
Cc: "Ilpo Järvinen" <ilpo.jarvinen@linux.intel.com>
Subject: [PATCH 4/4] resource: Increase MAX_IORES_LEVEL to 8
Date: Fri, 28 Nov 2025 13:50:21 +0200	[thread overview]
Message-ID: <20251128115021.4287-5-ilpo.jarvinen@linux.intel.com> (raw)
In-Reply-To: <20251128115021.4287-1-ilpo.jarvinen@linux.intel.com>

While debugging a PCI resource allocation issue, the resources for many
nested bridges and endpoints got flattened in /proc/iomem by
MAX_IORES_LEVEL that is set to 5. This made the iomem output hard to
read as the visual hierarchy cues were lost.

Increase MAX_IORES_LEVEL to 8 to avoid flattening PCI topologies with
nested bridges so aggressively (the case in the Link has the deepest
resource at level 7 so 8 looks a reasonable limit).

Link: https://bugzilla.kernel.org/show_bug.cgi?id=220775
Signed-off-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com>
---
 kernel/resource.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/kernel/resource.c b/kernel/resource.c
index b9fa2a4ce089..c5c907b3236d 100644
--- a/kernel/resource.c
+++ b/kernel/resource.c
@@ -82,7 +82,7 @@ static struct resource *next_resource(struct resource *p, bool skip_children,
 
 #ifdef CONFIG_PROC_FS
 
-enum { MAX_IORES_LEVEL = 5 };
+enum { MAX_IORES_LEVEL = 8 };
 
 static void *r_start(struct seq_file *m, loff_t *pos)
 	__acquires(resource_lock)
-- 
2.39.5


      parent reply	other threads:[~2025-11-28 11:51 UTC|newest]

Thread overview: 5+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-11-28 11:50 [PATCH 0/4] PCI: Bridge window head alignment fix/rework Ilpo Järvinen
2025-11-28 11:50 ` [PATCH 1/4] PCI: Fix bridge window alignment with optional resources Ilpo Järvinen
2025-11-28 11:50 ` [PATCH 2/4] PCI: Rewrite bridge window head alignment function Ilpo Järvinen
2025-11-28 11:50 ` [PATCH 3/4] PCI: Stop over-estimating bridge window size Ilpo Järvinen
2025-11-28 11:50 ` Ilpo Järvinen [this message]

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