From: <smadhavan@nvidia.com>
To: <dave@stgolabs.net>, <jonathan.cameron@huawei.com>,
<dave.jiang@intel.com>, <alison.schofield@intel.com>,
<vishal.l.verma@intel.com>, <ira.weiny@intel.com>,
<dan.j.williams@intel.com>, <bhelgaas@google.com>,
<ming.li@zohomail.com>, <rrichter@amd.com>,
<Smita.KoralahalliChannabasappa@amd.com>,
<huaisheng.ye@intel.com>, <linux-cxl@vger.kernel.org>,
<linux-pci@vger.kernel.org>
Cc: <smadhavan@nvidia.com>, <vaslot@nvidia.com>, <vsethi@nvidia.com>,
<sdonthineni@nvidia.com>, <vidyas@nvidia.com>, <mochs@nvidia.com>,
<jsequeira@nvidia.com>
Subject: [PATCH v3 6/10] PCI: wire CXL reset prepare/cleanup
Date: Fri, 16 Jan 2026 01:41:42 +0000 [thread overview]
Message-ID: <20260116014146.2149236-7-smadhavan@nvidia.com> (raw)
In-Reply-To: <20260116014146.2149236-1-smadhavan@nvidia.com>
From: Srirangan Madhavan <smadhavan@nvidia.com>
Wire CXL reset preparation and cleanup into the PCI CXL reset path.
The flow now validates/offlines regions, performs teardown and cache
flushes, then releases the lock on completion or error. This keeps the
common reset_prepare flow intact while adding cxl_reset-specific quiesce logic.
Signed-off-by: Srirangan Madhavan <smadhavan@nvidia.com>
---
drivers/pci/pci.c | 19 ++++++++++++++++++-
include/linux/pci.h | 2 ++
2 files changed, 20 insertions(+), 1 deletion(-)
diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
index b3eb82b21c35..83fd7e75a12e 100644
--- a/drivers/pci/pci.c
+++ b/drivers/pci/pci.c
@@ -4985,10 +4985,27 @@ static int cxl_reset(struct pci_dev *dev, bool probe)
if (probe)
return 0;
+ /*
+ * CXL-reset-specific preparation: validate memory offline,
+ * tear down regions, flush device caches.
+ */
+ rc = cxl_reset_prepare_device(dev);
+ if (rc)
+ return rc;
+
if (!pci_wait_for_pending_transaction(dev))
pci_err(dev, "timed out waiting for pending transaction; performing function level reset anyway\n");
- return cxl_reset_init(dev, dvsec);
+ rc = cxl_reset_init(dev, dvsec);
+ if (rc)
+ goto out_cleanup;
+
+ cxl_reset_cleanup_device(dev);
+ return 0;
+
+out_cleanup:
+ cxl_reset_cleanup_device(dev);
+ return rc;
}
static int cxl_reset_bus_function(struct pci_dev *dev, bool probe)
diff --git a/include/linux/pci.h b/include/linux/pci.h
index 056eff0b1e86..d29f0bfc84b5 100644
--- a/include/linux/pci.h
+++ b/include/linux/pci.h
@@ -1465,6 +1465,8 @@ int __must_check pci_resize_resource(struct pci_dev *dev, int i, int size,
int pci_select_bars(struct pci_dev *dev, unsigned long flags);
bool pci_device_is_present(struct pci_dev *pdev);
bool cxl_is_type2_device(struct pci_dev *dev);
+int cxl_reset_prepare_device(struct pci_dev *pdev);
+void cxl_reset_cleanup_device(struct pci_dev *pdev);
void pci_ignore_hotplug(struct pci_dev *dev);
struct pci_dev *pci_real_dma_dev(struct pci_dev *dev);
int pci_status_get_and_clear_errors(struct pci_dev *pdev);
--
2.34.1
next prev parent reply other threads:[~2026-01-16 1:42 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-01-16 1:41 [PATCH v3 0/10] CXL reset support for Type 2 devices smadhavan
2026-01-16 1:41 ` [PATCH v3 1/10] cxl: move DVSEC defines to cxl pci header smadhavan
2026-01-16 1:41 ` [PATCH v3 2/10] PCI: switch CXL port DVSEC defines smadhavan
2026-01-16 1:41 ` [PATCH v3 3/10] cxl: add type 2 helper and reset DVSEC bits smadhavan
2026-01-16 1:41 ` [PATCH v3 4/10] PCI: add CXL reset method smadhavan
2026-01-17 13:56 ` kernel test robot
2026-01-17 14:28 ` kernel test robot
2026-01-16 1:41 ` [PATCH v3 5/10] cxl: add reset prepare and region teardown smadhavan
2026-01-16 1:41 ` smadhavan [this message]
2026-01-16 1:41 ` [PATCH v3 7/10] cxl: add host cache flush and multi-function reset smadhavan
2026-01-16 1:41 ` [PATCH v3 8/10] cxl: add DVSEC config save/restore smadhavan
2026-01-16 1:41 ` [PATCH v3 9/10] PCI: save/restore CXL config around reset smadhavan
2026-01-16 1:41 ` [PATCH v3 10/10] cxl: add HDM decoder and IDE save/restore smadhavan
2026-01-18 22:29 ` [PATCH v3 0/10] CXL reset support for Type 2 devices Alison Schofield
2026-01-20 22:33 ` Srirangan Madhavan
[not found] ` <CY5PR12MB6226EE35D88E6F4442572D1CC389A@CY5PR12MB6226.namprd12.prod.outlook.com>
2026-01-21 0:30 ` Alison Schofield
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