Re: [PATCH v3 4/10] PCI: add CXL reset method

[kernel test robot <lkp@intel.com>]

Hi,

kernel test robot noticed the following build warnings:

[auto build test WARNING on pci/next]
[also build test WARNING on pci/for-linus linus/master v6.19-rc5]
[cannot apply to next-20260116]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]

url:    https://github.com/intel-lab-lkp/linux/commits/smadhavan-nvidia-com/cxl-move-DVSEC-defines-to-cxl-pci-header/20260116-094457
base:   https://git.kernel.org/pub/scm/linux/kernel/git/pci/pci.git next
patch link:    https://lore.kernel.org/r/20260116014146.2149236-5-smadhavan%40nvidia.com
patch subject: [PATCH v3 4/10] PCI: add CXL reset method
config: loongarch-allnoconfig (https://download.01.org/0day-ci/archive/20260117/202601172246.rz4Orygn-lkp@intel.com/config)
compiler: clang version 22.0.0git (https://github.com/llvm/llvm-project 9b8addffa70cee5b2acc5454712d9cf78ce45710)
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20260117/202601172246.rz4Orygn-lkp@intel.com/reproduce)

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202601172246.rz4Orygn-lkp@intel.com/

All warnings (new ones prefixed by >>):

>> drivers/pci/pci.c:4979:10: warning: & has lower precedence than ==; == will be evaluated first [-Wparentheses]
    4979 |         if (reg & CXL_DVSEC_CXL_RST_CAPABLE == 0)
         |                 ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
   drivers/pci/pci.c:4979:10: note: place parentheses around the '==' expression to silence this warning
    4979 |         if (reg & CXL_DVSEC_CXL_RST_CAPABLE == 0)
         |                 ^ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
   drivers/pci/pci.c:4979:10: note: place parentheses around the & expression to evaluate it first
    4979 |         if (reg & CXL_DVSEC_CXL_RST_CAPABLE == 0)
         |             ~~~~^~~~~~~~~~~~~~~~~~~~~~~~~~~
   1 warning generated.


vim +4979 drivers/pci/pci.c

  4956	
  4957	/**
  4958	 * cxl_reset - initiate a cxl reset
  4959	 * @dev: device to reset
  4960	 * @probe: if true, return 0 if device can be reset this way
  4961	 *
  4962	 * Initiate a cxl reset on @dev.
  4963	 */
  4964	static int cxl_reset(struct pci_dev *dev, bool probe)
  4965	{
  4966		u16 dvsec, reg;
  4967		int rc;
  4968	
  4969		dvsec = pci_find_dvsec_capability(dev, PCI_VENDOR_ID_CXL,
  4970						  CXL_DVSEC_PCIE_DEVICE);
  4971		if (!dvsec)
  4972			return -ENOTTY;
  4973	
  4974		/* Check if CXL Reset is supported. */
  4975		rc = pci_read_config_word(dev, dvsec + CXL_DVSEC_CAP_OFFSET, &reg);
  4976		if (rc)
  4977			return -ENOTTY;
  4978	
> 4979		if (reg & CXL_DVSEC_CXL_RST_CAPABLE == 0)
  4980			return -ENOTTY;
  4981	
  4982		/*
  4983		 * Expose CXL reset for Type 2 devices.
  4984		 */
  4985		if (!cxl_is_type2_device(dev))
  4986			return -ENOTTY;
  4987	
  4988		if (probe)
  4989			return 0;
  4990	
  4991		if (!pci_wait_for_pending_transaction(dev))
  4992			pci_err(dev, "timed out waiting for pending transaction; performing function level reset anyway\n");
  4993	
  4994		return cxl_reset_init(dev, dvsec);
  4995	}
  4996	

-- 
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https://github.com/intel/lkp-tests/wiki