* [PATCH] PCI: Correct PCI_CAP_EXP_ENDPOINT_SIZEOF_V2 value
@ 2026-02-27 12:36 Bjorn Helgaas
2026-02-27 13:04 ` Krzysztof Wilczyński
2026-02-27 16:47 ` Bjorn Helgaas
0 siblings, 2 replies; 3+ messages in thread
From: Bjorn Helgaas @ 2026-02-27 12:36 UTC (permalink / raw)
To: linux-pci, David Woodhouse, Alex Williamson
Cc: Baruch Siach, kvm, linux-kernel, Bjorn Helgaas
fb82437fdd8c ("PCI: Change capability register offsets to hex") incorrectly
converted the PCI_CAP_EXP_ENDPOINT_SIZEOF_V2 value from decimal 52 to hex
0x32:
-#define PCI_CAP_EXP_ENDPOINT_SIZEOF_V2 52 /* v2 endpoints with link end here */
+#define PCI_CAP_EXP_ENDPOINT_SIZEOF_V2 0x32 /* end of v2 EPs w/ link */
Change PCI_CAP_EXP_ENDPOINT_SIZEOF_V2 to the correct value of 0x34.
fb82437fdd8c was from Baruch Siach <baruch@tkos.co.il>, but this was not
Baruch's fault; it's a mistake I made when applying the patch.
Fixes: fb82437fdd8c ("PCI: Change capability register offsets to hex")
Reported-by: David Woodhouse <dwmw2@infradead.org>
Closes: https://lore.kernel.org/all/3ae392a0158e9d9ab09a1d42150429dd8ca42791.camel@infradead.org
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
---
include/uapi/linux/pci_regs.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h
index ec1c54b5a310..14f634ab9350 100644
--- a/include/uapi/linux/pci_regs.h
+++ b/include/uapi/linux/pci_regs.h
@@ -712,7 +712,7 @@
#define PCI_EXP_LNKCTL2_HASD 0x0020 /* HW Autonomous Speed Disable */
#define PCI_EXP_LNKSTA2 0x32 /* Link Status 2 */
#define PCI_EXP_LNKSTA2_FLIT 0x0400 /* Flit Mode Status */
-#define PCI_CAP_EXP_ENDPOINT_SIZEOF_V2 0x32 /* end of v2 EPs w/ link */
+#define PCI_CAP_EXP_ENDPOINT_SIZEOF_V2 0x34 /* end of v2 EPs w/ link */
#define PCI_EXP_SLTCAP2 0x34 /* Slot Capabilities 2 */
#define PCI_EXP_SLTCAP2_IBPD 0x00000001 /* In-band PD Disable Supported */
#define PCI_EXP_SLTCTL2 0x38 /* Slot Control 2 */
--
2.51.0
^ permalink raw reply related [flat|nested] 3+ messages in thread* Re: [PATCH] PCI: Correct PCI_CAP_EXP_ENDPOINT_SIZEOF_V2 value
2026-02-27 12:36 [PATCH] PCI: Correct PCI_CAP_EXP_ENDPOINT_SIZEOF_V2 value Bjorn Helgaas
@ 2026-02-27 13:04 ` Krzysztof Wilczyński
2026-02-27 16:47 ` Bjorn Helgaas
1 sibling, 0 replies; 3+ messages in thread
From: Krzysztof Wilczyński @ 2026-02-27 13:04 UTC (permalink / raw)
To: Bjorn Helgaas
Cc: linux-pci, David Woodhouse, Alex Williamson, Baruch Siach, kvm,
linux-kernel, Bjorn Helgaas
Hello,
[...]
> diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h
> index ec1c54b5a310..14f634ab9350 100644
> --- a/include/uapi/linux/pci_regs.h
> +++ b/include/uapi/linux/pci_regs.h
> @@ -712,7 +712,7 @@
> #define PCI_EXP_LNKCTL2_HASD 0x0020 /* HW Autonomous Speed Disable */
> #define PCI_EXP_LNKSTA2 0x32 /* Link Status 2 */
> #define PCI_EXP_LNKSTA2_FLIT 0x0400 /* Flit Mode Status */
> -#define PCI_CAP_EXP_ENDPOINT_SIZEOF_V2 0x32 /* end of v2 EPs w/ link */
> +#define PCI_CAP_EXP_ENDPOINT_SIZEOF_V2 0x34 /* end of v2 EPs w/ link */
> #define PCI_EXP_SLTCAP2 0x34 /* Slot Capabilities 2 */
> #define PCI_EXP_SLTCAP2_IBPD 0x00000001 /* In-band PD Disable Supported */
> #define PCI_EXP_SLTCTL2 0x38 /* Slot Control 2 */
Looks good!
Reviewed-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
Thank you!
Krzysztof
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH] PCI: Correct PCI_CAP_EXP_ENDPOINT_SIZEOF_V2 value
2026-02-27 12:36 [PATCH] PCI: Correct PCI_CAP_EXP_ENDPOINT_SIZEOF_V2 value Bjorn Helgaas
2026-02-27 13:04 ` Krzysztof Wilczyński
@ 2026-02-27 16:47 ` Bjorn Helgaas
1 sibling, 0 replies; 3+ messages in thread
From: Bjorn Helgaas @ 2026-02-27 16:47 UTC (permalink / raw)
To: linux-pci, David Woodhouse, Alex Williamson
Cc: Baruch Siach, kvm, linux-kernel, Bjorn Helgaas
On Fri, Feb 27, 2026 at 06:36:53AM -0600, Bjorn Helgaas wrote:
> fb82437fdd8c ("PCI: Change capability register offsets to hex") incorrectly
> converted the PCI_CAP_EXP_ENDPOINT_SIZEOF_V2 value from decimal 52 to hex
> 0x32:
>
> -#define PCI_CAP_EXP_ENDPOINT_SIZEOF_V2 52 /* v2 endpoints with link end here */
> +#define PCI_CAP_EXP_ENDPOINT_SIZEOF_V2 0x32 /* end of v2 EPs w/ link */
>
> Change PCI_CAP_EXP_ENDPOINT_SIZEOF_V2 to the correct value of 0x34.
>
> fb82437fdd8c was from Baruch Siach <baruch@tkos.co.il>, but this was not
> Baruch's fault; it's a mistake I made when applying the patch.
>
> Fixes: fb82437fdd8c ("PCI: Change capability register offsets to hex")
> Reported-by: David Woodhouse <dwmw2@infradead.org>
> Closes: https://lore.kernel.org/all/3ae392a0158e9d9ab09a1d42150429dd8ca42791.camel@infradead.org
> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
I applied this to pci/for-linus for v7.0.
Per David, it fixes a VMM issue with PCI capabilities.
> ---
> include/uapi/linux/pci_regs.h | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h
> index ec1c54b5a310..14f634ab9350 100644
> --- a/include/uapi/linux/pci_regs.h
> +++ b/include/uapi/linux/pci_regs.h
> @@ -712,7 +712,7 @@
> #define PCI_EXP_LNKCTL2_HASD 0x0020 /* HW Autonomous Speed Disable */
> #define PCI_EXP_LNKSTA2 0x32 /* Link Status 2 */
> #define PCI_EXP_LNKSTA2_FLIT 0x0400 /* Flit Mode Status */
> -#define PCI_CAP_EXP_ENDPOINT_SIZEOF_V2 0x32 /* end of v2 EPs w/ link */
> +#define PCI_CAP_EXP_ENDPOINT_SIZEOF_V2 0x34 /* end of v2 EPs w/ link */
> #define PCI_EXP_SLTCAP2 0x34 /* Slot Capabilities 2 */
> #define PCI_EXP_SLTCAP2_IBPD 0x00000001 /* In-band PD Disable Supported */
> #define PCI_EXP_SLTCTL2 0x38 /* Slot Control 2 */
> --
> 2.51.0
>
^ permalink raw reply [flat|nested] 3+ messages in thread
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2026-02-27 12:36 [PATCH] PCI: Correct PCI_CAP_EXP_ENDPOINT_SIZEOF_V2 value Bjorn Helgaas
2026-02-27 13:04 ` Krzysztof Wilczyński
2026-02-27 16:47 ` Bjorn Helgaas
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