Re: [PATCH v2] PCI: tegra194: Use aspm-l1-entry-delay-ns DT property for L1 entrance latency

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] L1 entrance latency calculation prevents programming a hardware value of 0.
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commit 63300af08363595c90cc1e642b1cf857792eae94
Author: Manikanta Maddireddy <mmaddireddy@nvidia.com>

PCI: tegra194: Use aspm-l1-entry-delay-ns DT property for L1 entrance latency

This commit parses the aspm-l1-entry-delay-ns device tree property to
configure the ASPM L1 entrance latency. It converts the delay from
nanoseconds to a 3-bit hardware encoding.

> diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c
> index 9dcfa194050e7..c9716d6144517 100644
> --- a/drivers/pci/controller/dwc/pcie-tegra194.c
> +++ b/drivers/pci/controller/dwc/pcie-tegra194.c
[ ... ]
> @@ -1141,6 +1146,15 @@ static int tegra_pcie_dw_parse_dt(struct tegra_pcie_dw *pcie)
>  		dev_info(pcie->dev,
>  			 "Failed to read ASPM L0s Entrance latency: %d\n", ret);
>  
> +	/* Default to max latency of 7. */
> +	pcie->aspm_l1_enter_lat = 7;
> +	ret = of_property_read_u32(np, "aspm-l1-entry-delay-ns", &val);
> +	if (!ret) {
> +		u32 us = max(val / 1000, 1U);
> +
> +		pcie->aspm_l1_enter_lat = min(ilog2(us) + 1, 7);

The commit message states the value is converted to a hardware encoded 3-bit
value that is equal to log2(ns/1000) + 1. Does this calculation prevent
programming a hardware value of 0?

By using max(val / 1000, 1U), the minimum value for us is 1. Since
ilog2(1) + 1 is 1, pcie->aspm_l1_enter_lat can never evaluate to 0.

If the hardware supports an encoded value of 0 to represent delays less than
1us, this logic prevents configuring it.

> +	}
> +
>  	ret = of_property_read_u32(np, "num-lanes", &pcie->num_lanes);

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Sashiko AI review · https://sashiko.dev/#/patchset/20260512034821.1320714-1-mmaddireddy@nvidia.com?part=1