[PATCH v2] PCI: tegra194: Use aspm-l1-entry-delay-ns DT property for L1 entrance latency

[PATCH v2] PCI: tegra194: Use aspm-l1-entry-delay-ns DT property for L1 entrance latency

[Manikanta Maddireddy]

Program ASPM L1 entrance latency from the optional aspm-l1-entry-delay-ns
device tree property. Convert the value from nanoseconds to a hardware
encoded 3-bit value that is equal to log2(ns/1000) + 1. If the property
is absent or greater than 7 (the maximum latency value supported), then
default to 7.

Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
---
V2: Fixed commit message as per review comments.

 drivers/pci/controller/dwc/pcie-tegra194.c | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c
index 9dcfa194050e..c9716d614451 100644
--- a/drivers/pci/controller/dwc/pcie-tegra194.c
+++ b/drivers/pci/controller/dwc/pcie-tegra194.c
@@ -18,6 +18,7 @@
 #include <linux/interrupt.h>
 #include <linux/iopoll.h>
 #include <linux/kernel.h>
+#include <linux/log2.h>
 #include <linux/module.h>
 #include <linux/of.h>
 #include <linux/of_pci.h>
@@ -272,6 +273,7 @@ struct tegra_pcie_dw {
 	u32 aspm_cmrt;
 	u32 aspm_pwr_on_t;
 	u32 aspm_l0s_enter_lat;
+	u32 aspm_l1_enter_lat;
 
 	struct regulator *pex_ctl_supply;
 	struct regulator *slot_ctl_3v3;
@@ -715,6 +717,8 @@ static void init_host_aspm(struct tegra_pcie_dw *pcie)
 	val = dw_pcie_readl_dbi(pci, PCIE_PORT_AFR);
 	val &= ~PORT_AFR_L0S_ENTRANCE_LAT_MASK;
 	val |= (pcie->aspm_l0s_enter_lat << PORT_AFR_L0S_ENTRANCE_LAT_SHIFT);
+	val &= ~PORT_AFR_L1_ENTRANCE_LAT_MASK;
+	val |= (pcie->aspm_l1_enter_lat << PORT_AFR_L1_ENTRANCE_LAT_SHIFT);
 	val |= PORT_AFR_ENTER_ASPM;
 	dw_pcie_writel_dbi(pci, PCIE_PORT_AFR, val);
 }
@@ -1115,6 +1119,7 @@ static int tegra_pcie_dw_parse_dt(struct tegra_pcie_dw *pcie)
 {
 	struct platform_device *pdev = to_platform_device(pcie->dev);
 	struct device_node *np = pcie->dev->of_node;
+	u32 val;
 	int ret;
 
 	pcie->dbi_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi");
@@ -1141,6 +1146,15 @@ static int tegra_pcie_dw_parse_dt(struct tegra_pcie_dw *pcie)
 		dev_info(pcie->dev,
 			 "Failed to read ASPM L0s Entrance latency: %d\n", ret);
 
+	/* Default to max latency of 7. */
+	pcie->aspm_l1_enter_lat = 7;
+	ret = of_property_read_u32(np, "aspm-l1-entry-delay-ns", &val);
+	if (!ret) {
+		u32 us = max(val / 1000, 1U);
+
+		pcie->aspm_l1_enter_lat = min(ilog2(us) + 1, 7);
+	}
+
 	ret = of_property_read_u32(np, "num-lanes", &pcie->num_lanes);
 	if (ret < 0) {
 		dev_err(pcie->dev, "Failed to read num-lanes: %d\n", ret);
-- 
2.34.1

Re: [PATCH v2] PCI: tegra194: Use aspm-l1-entry-delay-ns DT property for L1 entrance latency

[Jon Hunter]

On 12/05/2026 04:48, Manikanta Maddireddy wrote:
> Program ASPM L1 entrance latency from the optional aspm-l1-entry-delay-ns
> device tree property. Convert the value from nanoseconds to a hardware
> encoded 3-bit value that is equal to log2(ns/1000) + 1. If the property
> is absent or greater than 7 (the maximum latency value supported), then
> default to 7.
> 
> Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
> ---
> V2: Fixed commit message as per review comments.
> 
>   drivers/pci/controller/dwc/pcie-tegra194.c | 14 ++++++++++++++
>   1 file changed, 14 insertions(+)
> 
> diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c
> index 9dcfa194050e..c9716d614451 100644
> --- a/drivers/pci/controller/dwc/pcie-tegra194.c
> +++ b/drivers/pci/controller/dwc/pcie-tegra194.c
> @@ -18,6 +18,7 @@
>   #include <linux/interrupt.h>
>   #include <linux/iopoll.h>
>   #include <linux/kernel.h>
> +#include <linux/log2.h>
>   #include <linux/module.h>
>   #include <linux/of.h>
>   #include <linux/of_pci.h>
> @@ -272,6 +273,7 @@ struct tegra_pcie_dw {
>   	u32 aspm_cmrt;
>   	u32 aspm_pwr_on_t;
>   	u32 aspm_l0s_enter_lat;
> +	u32 aspm_l1_enter_lat;
>   
>   	struct regulator *pex_ctl_supply;
>   	struct regulator *slot_ctl_3v3;
> @@ -715,6 +717,8 @@ static void init_host_aspm(struct tegra_pcie_dw *pcie)
>   	val = dw_pcie_readl_dbi(pci, PCIE_PORT_AFR);
>   	val &= ~PORT_AFR_L0S_ENTRANCE_LAT_MASK;
>   	val |= (pcie->aspm_l0s_enter_lat << PORT_AFR_L0S_ENTRANCE_LAT_SHIFT);
> +	val &= ~PORT_AFR_L1_ENTRANCE_LAT_MASK;
> +	val |= (pcie->aspm_l1_enter_lat << PORT_AFR_L1_ENTRANCE_LAT_SHIFT);
>   	val |= PORT_AFR_ENTER_ASPM;
>   	dw_pcie_writel_dbi(pci, PCIE_PORT_AFR, val);
>   }
> @@ -1115,6 +1119,7 @@ static int tegra_pcie_dw_parse_dt(struct tegra_pcie_dw *pcie)
>   {
>   	struct platform_device *pdev = to_platform_device(pcie->dev);
>   	struct device_node *np = pcie->dev->of_node;
> +	u32 val;
>   	int ret;
>   
>   	pcie->dbi_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi");
> @@ -1141,6 +1146,15 @@ static int tegra_pcie_dw_parse_dt(struct tegra_pcie_dw *pcie)
>   		dev_info(pcie->dev,
>   			 "Failed to read ASPM L0s Entrance latency: %d\n", ret);
>   
> +	/* Default to max latency of 7. */
> +	pcie->aspm_l1_enter_lat = 7;
> +	ret = of_property_read_u32(np, "aspm-l1-entry-delay-ns", &val);
> +	if (!ret) {
> +		u32 us = max(val / 1000, 1U);
> +
> +		pcie->aspm_l1_enter_lat = min(ilog2(us) + 1, 7);
> +	}
> +
>   	ret = of_property_read_u32(np, "num-lanes", &pcie->num_lanes);
>   	if (ret < 0) {
>   		dev_err(pcie->dev, "Failed to read num-lanes: %d\n", ret);


Reviewed-by: Jon Hunter <jonathanh@nvidia.com>

Thanks!
Jon

-- 
nvpublic

Re: [PATCH v2] PCI: tegra194: Use aspm-l1-entry-delay-ns DT property for L1 entrance latency

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] L1 entrance latency calculation prevents programming a hardware value of 0.
--

commit 63300af08363595c90cc1e642b1cf857792eae94
Author: Manikanta Maddireddy <mmaddireddy@nvidia.com>

PCI: tegra194: Use aspm-l1-entry-delay-ns DT property for L1 entrance latency

This commit parses the aspm-l1-entry-delay-ns device tree property to
configure the ASPM L1 entrance latency. It converts the delay from
nanoseconds to a 3-bit hardware encoding.

> diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c
> index 9dcfa194050e7..c9716d6144517 100644
> --- a/drivers/pci/controller/dwc/pcie-tegra194.c
> +++ b/drivers/pci/controller/dwc/pcie-tegra194.c
[ ... ]
> @@ -1141,6 +1146,15 @@ static int tegra_pcie_dw_parse_dt(struct tegra_pcie_dw *pcie)
>  		dev_info(pcie->dev,
>  			 "Failed to read ASPM L0s Entrance latency: %d\n", ret);
>  
> +	/* Default to max latency of 7. */
> +	pcie->aspm_l1_enter_lat = 7;
> +	ret = of_property_read_u32(np, "aspm-l1-entry-delay-ns", &val);
> +	if (!ret) {
> +		u32 us = max(val / 1000, 1U);
> +
> +		pcie->aspm_l1_enter_lat = min(ilog2(us) + 1, 7);

The commit message states the value is converted to a hardware encoded 3-bit
value that is equal to log2(ns/1000) + 1. Does this calculation prevent
programming a hardware value of 0?

By using max(val / 1000, 1U), the minimum value for us is 1. Since
ilog2(1) + 1 is 1, pcie->aspm_l1_enter_lat can never evaluate to 0.

If the hardware supports an encoded value of 0 to represent delays less than
1us, this logic prevents configuring it.

> +	}
> +
>  	ret = of_property_read_u32(np, "num-lanes", &pcie->num_lanes);

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260512034821.1320714-1-mmaddireddy@nvidia.com?part=1