From: sashiko-bot@kernel.org
To: "Hans Zhang" <18255117159@163.com>
Cc: wsa+renesas@sang-engineering.com, linux-pci@vger.kernel.org
Subject: Re: [PATCH v4 7/7] PCI: rzg3s-host: Use common pci_host_common_link_train_delay() helper
Date: Mon, 18 May 2026 02:41:18 +0000 [thread overview]
Message-ID: <20260518024118.A9613C2BCB0@smtp.kernel.org> (raw)
In-Reply-To: <20260518004246.1384532-8-18255117159@163.com>
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] The mandatory PCIe link training delay is skipped when the 'max-link-speed' device tree property is omitted.
--
commit 66a7457779d07490b3340e0c36c8ac63f1f0a84f
Author: Hans Zhang <18255117159@163.com>
PCI: rzg3s-host: Use common pci_host_common_link_train_delay() helper
This commit replaces an unconditional 100ms msleep with the
pci_host_common_link_train_delay() helper. The delay is now only applied
when max_link_speed is greater than 2.
> diff --git a/drivers/pci/controller/pcie-rzg3s-host.c b/drivers/pci/controller/pcie-rzg3s-host.c
> --- a/drivers/pci/controller/pcie-rzg3s-host.c
> +++ b/drivers/pci/controller/pcie-rzg3s-host.c
[ ... ]
> @@ -1663,7 +1664,7 @@ rzg3s_pcie_host_setup(struct rzg3s_pcie_host *host,
> if (ret)
> dev_info(dev, "Failed to set max link speed\n");
>
> - msleep(PCIE_RESET_CONFIG_WAIT_MS);
> + pci_host_common_link_train_delay(host->max_link_speed);
Could this regression skip the mandatory link training delay if the
max-link-speed device tree property is omitted?
If the property is missing, of_pci_get_max_link_speed() returns a negative
error code like -EINVAL, which gets stored in host->max_link_speed.
When rzg3s_pcie_set_max_link_speed() runs, it ignores negative values and
uses the hardware's native capability to configure the link, which could be
Gen3 or Gen4. However, host->max_link_speed is not updated to reflect this
actual link speed.
Because pci_host_common_link_train_delay() takes an int, passing the
negative error code causes the condition to evaluate to false:
drivers/pci/controller/pci-host-common.h:pci_host_common_link_train_delay() {
if (max_link_speed > 2)
msleep(PCIE_RESET_CONFIG_WAIT_MS);
}
This skips the 100ms delay even for Gen3+ links, which could cause
enumeration failures for downstream devices.
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260518004246.1384532-1-18255117159@163.com?part=7
prev parent reply other threads:[~2026-05-18 2:41 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-05-18 0:42 [PATCH v4 0/7] PCI: Add common helper for 100 ms delay after link training Hans Zhang
2026-05-18 0:42 ` [PATCH v4 1/7] PCI: Add pci_host_common_link_train_delay() helper Hans Zhang
2026-05-18 1:01 ` sashiko-bot
2026-05-18 0:42 ` [PATCH v4 2/7] PCI: cadence: Add post-link delay for LGA and j721e glue driver Hans Zhang
2026-05-18 1:20 ` sashiko-bot
2026-05-18 2:12 ` Manikandan Karunakaran Pillai
2026-05-18 2:26 ` Hans Zhang
2026-05-18 2:38 ` Manikandan Karunakaran Pillai
2026-05-18 3:03 ` Hans Zhang
2026-05-18 3:17 ` Manikandan Karunakaran Pillai
2026-05-18 0:42 ` [PATCH v4 3/7] PCI: cadence: HPA: Add post-link delay Hans Zhang
2026-05-18 1:36 ` sashiko-bot
2026-05-18 2:16 ` Manikandan Karunakaran Pillai
2026-05-18 2:27 ` Hans Zhang
2026-05-18 0:42 ` [PATCH v4 4/7] PCI: dwc: Use common pci_host_common_link_train_delay() helper Hans Zhang
2026-05-18 1:49 ` sashiko-bot
2026-05-18 0:42 ` [PATCH v4 5/7] PCI: aardvark: Add 100 ms delay after link training Hans Zhang
2026-05-18 2:09 ` sashiko-bot
2026-05-18 0:42 ` [PATCH v4 6/7] PCI: mediatek-gen3: Add 100 ms delay after link up Hans Zhang
2026-05-18 2:30 ` sashiko-bot
2026-05-18 0:42 ` [PATCH v4 7/7] PCI: rzg3s-host: Use common pci_host_common_link_train_delay() helper Hans Zhang
2026-05-18 2:41 ` sashiko-bot [this message]
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