* [PATCH v6 0/3] PCI: cadence: Add LTSSM debugfs
@ 2026-05-19 12:36 Hans Zhang
2026-05-19 12:36 ` [PATCH v6 1/3] PCI: cadence: Add HPA architecture flag Hans Zhang
` (2 more replies)
0 siblings, 3 replies; 13+ messages in thread
From: Hans Zhang @ 2026-05-19 12:36 UTC (permalink / raw)
To: bhelgaas, lpieralisi, kwilczynski, mani
Cc: robh, mpillai, a-garg7, s-vadapalli, linux-pci, linux-kernel,
Hans Zhang
Hi,
This series adds debugfs support to the Cadence PCIe controller driver,
allowing users to read the current LTSSM state of the link for debugging
purposes.
Patch 1 introduces a new flag 'is_hpa' in the cdns_pcie structure to
distinguish HPA (High Performance Architecture) IP platforms from LGA
(Legacy Architecture) IP platforms, as they have different register
layouts for LTSSM status.
Patch 2 implements the debugfs file "ltssm_status" for HPA IP under a
per-device directory. It reads the LTSSM state from the appropriate
hardware register based on the 'is_hpa' flag and displays both a
descriptive string and the raw value.
Patch 3 adds LTSSM debugfs support for LGA IP, utilizing a new callback
'get_lga_ltssm' in cdns_pcie_ops to read the LTSSM state from the LGA
register. The debugfs interface now supports both IP types seamlessly.
=====================
Test:
root@orangepi6plus:~# ls -l /sys/kernel/debug/cdns_pcie_a0*
/sys/kernel/debug/cdns_pcie_a010000.pcie:
total 0
-r--r--r-- 1 root root 0 Jan 1 1970 ltssm_status
/sys/kernel/debug/cdns_pcie_a0c0000.pcie:
total 0
-r--r--r-- 1 root root 0 Jan 1 1970 ltssm_status
/sys/kernel/debug/cdns_pcie_a0e0000.pcie:
total 0
-r--r--r-- 1 root root 0 Jan 1 1970 ltssm_status
root@orangepi6plus:~#
root@orangepi6plus:~#
root@orangepi6plus:~# cat /sys/kernel/debug/cdns_pcie_a0*/ltss*
L0_STATE (0x29)
L0_STATE (0x29)
L0_STATE (0x29)
root@orangepi6plus:~#
root@orangepi6plus:~# uname -a
Linux orangepi6plus 7.1.0-rc3-00007-ge3963f3f4e31 #62 SMP PREEMPT Tue May 19 20:28:24 CST 2026 aarch64 aarch64 aarch64 GNUx
=====================
---
Changes for v6:
- The LTSSM status of the LGA IP no longer contains the "LTSSM_" character. (Aksh)
Changes for v5:
- Split LGA and HPA LTSSM debugfs support into separate patches as they
have different register definitions and access methods. (Aksh, Manikandan)
- Add cdns_pcie_hpa_host_disable() to properly clean up debugfs on
removal (Mani)
- Remove redundant copyright email address (Mani)
Changes for v4:
- Remove the copyright email address of the author of pcie-cadence-debugfs.c (Mani)
- Add cdns_pcie_hpa_host_disable() (Mani)
- Use DEFINE_SHOW_ATTRIBUTE() (Mani & Sashiko)
Changes for v3:
- Export cdns_pcie_debugfs_deinit (Mani)
- pcie-cadence-ep.c pcie-cadence-host.c pci-sky1.c call cdns_pcie_debugfs_deinit
Changes for v2:
- s/DW_PCIE_LTSSM_NAME/CDNS_PCIE_LTSSM_NAME/
- S/January 2026/March 2026/
- EXPORT_SYMBOL_GPL(cdns_pcie_debugfs_init); // Resolve the following error issues.
>> ERROR: modpost: "cdns_pcie_debugfs_init" [drivers/pci/controller/cadence/pcie-cadence-host-mod.ko] undefined!
>> ERROR: modpost: "cdns_pcie_debugfs_init" [drivers/pci/controller/cadence/pcie-cadence-ep-mod.ko] undefined!
v5:
https://patchwork.kernel.org/project/linux-pci/patch/20260515145747.129635-1-18255117159@163.com/
v4:
https://patchwork.kernel.org/project/linux-pci/patch/20260508034101.1910036-1-18255117159@163.com/
v3:
https://patchwork.kernel.org/project/linux-pci/patch/20260406103237.1203127-1-18255117159@163.com/
v2:
https://patchwork.kernel.org/project/linux-pci/patch/20260321033035.3008585-3-18255117159@163.com/
v1:
https://patchwork.kernel.org/project/linux-pci/cover/20260315155514.127255-1-18255117159@163.com/
Hans Zhang (3):
PCI: cadence: Add HPA architecture flag
PCI: cadence: Add HPA IP debugfs for LTSSM status
PCI: cadence: Add LGA IP debugfs for LTSSM status
Documentation/ABI/testing/debugfs-cdns-pcie | 5 +
drivers/pci/controller/cadence/Kconfig | 9 +
drivers/pci/controller/cadence/Makefile | 1 +
drivers/pci/controller/cadence/pci-sky1.c | 5 +
.../controller/cadence/pcie-cadence-debugfs.c | 263 ++++++++++++++++++
.../pci/controller/cadence/pcie-cadence-ep.c | 3 +
.../cadence/pcie-cadence-host-hpa.c | 19 +-
.../controller/cadence/pcie-cadence-host.c | 9 +-
drivers/pci/controller/cadence/pcie-cadence.h | 198 +++++++++++++
9 files changed, 510 insertions(+), 2 deletions(-)
create mode 100644 Documentation/ABI/testing/debugfs-cdns-pcie
create mode 100644 drivers/pci/controller/cadence/pcie-cadence-debugfs.c
base-commit: 50897c955902c93ae71c38698abb910525ebdc89
--
2.43.0
^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH v6 1/3] PCI: cadence: Add HPA architecture flag
2026-05-19 12:36 [PATCH v6 0/3] PCI: cadence: Add LTSSM debugfs Hans Zhang
@ 2026-05-19 12:36 ` Hans Zhang
2026-05-19 12:36 ` [PATCH v6 2/3] PCI: cadence: Add HPA IP debugfs for LTSSM status Hans Zhang
2026-05-19 12:36 ` [PATCH v6 3/3] PCI: cadence: Add LGA " Hans Zhang
2 siblings, 0 replies; 13+ messages in thread
From: Hans Zhang @ 2026-05-19 12:36 UTC (permalink / raw)
To: bhelgaas, lpieralisi, kwilczynski, mani
Cc: robh, mpillai, a-garg7, s-vadapalli, linux-pci, linux-kernel,
Hans Zhang
Add a boolean flag 'is_hpa' to the cdns_pcie structure to indicate
that the controller is part of a Heterogeneous Processor Architecture
(HPA) system. This flag will be used by subsequent patches to handle
HPA-specific register layouts and behaviors.
Signed-off-by: Hans Zhang <18255117159@163.com>
---
drivers/pci/controller/cadence/pci-sky1.c | 1 +
drivers/pci/controller/cadence/pcie-cadence.h | 2 ++
2 files changed, 3 insertions(+)
diff --git a/drivers/pci/controller/cadence/pci-sky1.c b/drivers/pci/controller/cadence/pci-sky1.c
index cd55c64e58a9..e1f4a98e2ab6 100644
--- a/drivers/pci/controller/cadence/pci-sky1.c
+++ b/drivers/pci/controller/cadence/pci-sky1.c
@@ -174,6 +174,7 @@ static int sky1_pcie_probe(struct platform_device *pdev)
cdns_pcie->reg_base = pcie->reg_base;
cdns_pcie->msg_res = pcie->msg_res;
cdns_pcie->is_rc = true;
+ cdns_pcie->is_hpa = true;
reg_off = devm_kzalloc(dev, sizeof(*reg_off), GFP_KERNEL);
if (!reg_off) {
diff --git a/drivers/pci/controller/cadence/pcie-cadence.h b/drivers/pci/controller/cadence/pcie-cadence.h
index 574e9cf4d003..9a464cbaf073 100644
--- a/drivers/pci/controller/cadence/pcie-cadence.h
+++ b/drivers/pci/controller/cadence/pcie-cadence.h
@@ -80,6 +80,7 @@ struct cdns_plat_pcie_of_data {
* @msg_res: Region for send message to map PCI accesses
* @dev: PCIe controller
* @is_rc: tell whether the PCIe controller mode is Root Complex or Endpoint.
+ * @is_hpa: indicates if the architecture is HPA
* @phy_count: number of supported PHY devices
* @phy: list of pointers to specific PHY control blocks
* @link: list of pointers to corresponding device link representations
@@ -93,6 +94,7 @@ struct cdns_pcie {
struct resource *msg_res;
struct device *dev;
bool is_rc;
+ bool is_hpa;
int phy_count;
struct phy **phy;
struct device_link **link;
--
2.43.0
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH v6 2/3] PCI: cadence: Add HPA IP debugfs for LTSSM status
2026-05-19 12:36 [PATCH v6 0/3] PCI: cadence: Add LTSSM debugfs Hans Zhang
2026-05-19 12:36 ` [PATCH v6 1/3] PCI: cadence: Add HPA architecture flag Hans Zhang
@ 2026-05-19 12:36 ` Hans Zhang
2026-05-19 13:20 ` sashiko-bot
2026-05-20 7:26 ` Aksh Garg
2026-05-19 12:36 ` [PATCH v6 3/3] PCI: cadence: Add LGA " Hans Zhang
2 siblings, 2 replies; 13+ messages in thread
From: Hans Zhang @ 2026-05-19 12:36 UTC (permalink / raw)
To: bhelgaas, lpieralisi, kwilczynski, mani
Cc: robh, mpillai, a-garg7, s-vadapalli, linux-pci, linux-kernel,
Hans Zhang
Add debugfs support for HPA-based Cadence PCIe controllers. A new file
'ltssm_status' is created under debugfs, allowing users to read the
current LTSSM state as a string and raw value.
Signed-off-by: Hans Zhang <18255117159@163.com>
---
Documentation/ABI/testing/debugfs-cdns-pcie | 5 +
drivers/pci/controller/cadence/Kconfig | 9 +
drivers/pci/controller/cadence/Makefile | 1 +
drivers/pci/controller/cadence/pci-sky1.c | 4 +
.../controller/cadence/pcie-cadence-debugfs.c | 208 ++++++++++++++++++
.../cadence/pcie-cadence-host-hpa.c | 19 +-
drivers/pci/controller/cadence/pcie-cadence.h | 153 +++++++++++++
7 files changed, 398 insertions(+), 1 deletion(-)
create mode 100644 Documentation/ABI/testing/debugfs-cdns-pcie
create mode 100644 drivers/pci/controller/cadence/pcie-cadence-debugfs.c
diff --git a/Documentation/ABI/testing/debugfs-cdns-pcie b/Documentation/ABI/testing/debugfs-cdns-pcie
new file mode 100644
index 000000000000..c1104e28e4ee
--- /dev/null
+++ b/Documentation/ABI/testing/debugfs-cdns-pcie
@@ -0,0 +1,5 @@
+What: /sys/kernel/debug/cdns_pcie_<dev>/ltssm_status
+Date: March 2026
+Contact: Hans Zhang <18255117159@163.com>
+Description: (RO) Read will return the current PCIe LTSSM state in both
+ string and raw value.
\ No newline at end of file
diff --git a/drivers/pci/controller/cadence/Kconfig b/drivers/pci/controller/cadence/Kconfig
index 9e651d545973..cb010bc97aad 100644
--- a/drivers/pci/controller/cadence/Kconfig
+++ b/drivers/pci/controller/cadence/Kconfig
@@ -6,6 +6,15 @@ menu "Cadence-based PCIe controllers"
config PCIE_CADENCE
tristate
+config PCIE_CADENCE_DEBUGFS
+ tristate "Cadence PCIe debugfs entries"
+ depends on DEBUG_FS
+ depends on PCIE_CADENCE_HOST || PCIE_CADENCE_EP
+ help
+ Say Y here to enable debugfs entries for the PCIe controller. These
+ entries provide various debug features related to the controller and
+ the LTSSM status of link can be displayed.
+
config PCIE_CADENCE_HOST
tristate
depends on OF
diff --git a/drivers/pci/controller/cadence/Makefile b/drivers/pci/controller/cadence/Makefile
index b8ec1cecfaa8..2cdc4617e0c2 100644
--- a/drivers/pci/controller/cadence/Makefile
+++ b/drivers/pci/controller/cadence/Makefile
@@ -4,6 +4,7 @@ pcie-cadence-host-mod-y := pcie-cadence-host-common.o pcie-cadence-host.o pcie-c
pcie-cadence-ep-mod-y := pcie-cadence-ep.o
obj-$(CONFIG_PCIE_CADENCE) = pcie-cadence-mod.o
+obj-$(CONFIG_PCIE_CADENCE_DEBUGFS) += pcie-cadence-debugfs.o
obj-$(CONFIG_PCIE_CADENCE_HOST) += pcie-cadence-host-mod.o
obj-$(CONFIG_PCIE_CADENCE_EP) += pcie-cadence-ep-mod.o
obj-$(CONFIG_PCIE_CADENCE_PLAT) += pcie-cadence-plat.o
diff --git a/drivers/pci/controller/cadence/pci-sky1.c b/drivers/pci/controller/cadence/pci-sky1.c
index e1f4a98e2ab6..b8632f1d3156 100644
--- a/drivers/pci/controller/cadence/pci-sky1.c
+++ b/drivers/pci/controller/cadence/pci-sky1.c
@@ -221,6 +221,10 @@ MODULE_DEVICE_TABLE(of, of_sky1_pcie_match);
static void sky1_pcie_remove(struct platform_device *pdev)
{
struct sky1_pcie *pcie = platform_get_drvdata(pdev);
+ struct cdns_pcie_rc *rc;
+
+ rc = container_of(pcie->cdns_pcie, struct cdns_pcie_rc, pcie);
+ cdns_pcie_hpa_host_disable(rc);
pci_ecam_free(pcie->cfg);
}
diff --git a/drivers/pci/controller/cadence/pcie-cadence-debugfs.c b/drivers/pci/controller/cadence/pcie-cadence-debugfs.c
new file mode 100644
index 000000000000..97c5deef2b1a
--- /dev/null
+++ b/drivers/pci/controller/cadence/pcie-cadence-debugfs.c
@@ -0,0 +1,208 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Cadence PCIe controller debugfs driver
+ *
+ * Copyright (C) 2026 Hans Zhang <18255117159@163.com>
+ */
+
+#include <linux/bitfield.h>
+#include <linux/debugfs.h>
+#include <linux/seq_file.h>
+
+#include "pcie-cadence.h"
+
+#define CDNS_DEBUGFS_BUF_MAX 128
+
+static const char *cdns_pcie_hpa_ltssm_status_string(enum cdns_pcie_hpa_ltssm ltssm)
+{
+ const char *str;
+
+ switch (ltssm) {
+#define CDNS_PCIE_HPA_LTSSM_NAME(n) case n: str = #n; break
+ CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_DETECT_QUIET);
+ CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_DETECT_QUIET_ENTRY);
+ CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_DETECT_ACTIVE);
+ CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_DETECT_ACTIVE_1);
+ CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_DETECT_ACTIVE_2);
+ CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_DETECT_ACTIVE_3);
+ CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_RCVR_DETECTED_ST);
+ CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_RCVR_DETECTED_1);
+ CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_POLLING_ACTIVE);
+ CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_POLLING_ACTIVE_1);
+ CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_POLLING_ACTIVE_2);
+ CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_POLLING_ACTIVE_3);
+ CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_POLLING_COMPLIANCE);
+ CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_POLLING_COMPLIANCE_1);
+ CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_POLLING_CONFIG);
+ CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_POLLING_CONFIG_1);
+ CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_POLLING_CONFIG_2);
+ CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_CONFIG_LW_START_RC);
+ CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_CONFIG_LW_START_RC_1);
+ CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_CONFIG_LW_START_RC_2);
+ CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_CONFIG_LW_ACC_RC);
+ CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_CONFIG_LANENUM_WAIT_RC);
+ CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_CONFIG_LANENUM_WAIT_RC_1);
+ CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_CONFIG_LANENUM_ACC_RC);
+ CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_CONFIG_LW_START_EP);
+ CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_CONFIG_LW_START_EP_1);
+ CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_CONFIG_LW_START_EP_2);
+ CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_CONFIG_LW_ACC_EP);
+ CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_CONFIG_LANENUM_WAIT_EP);
+ CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_CONFIG_LANENUM_WAIT_EP_1);
+ CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_CONFIG_LANENUM_ACC_EP);
+ CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_CONFIG_LANENUM_ACC_EP_1);
+ CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_DUMMY_STATE_1);
+ CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_CONFIG_COMPLETE);
+ CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_CONFIG_COMPLETE_1);
+ CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_CONFIG_COMPLETE_2);
+ CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_CONFIG_IDLE);
+ CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_CONFIG_IDLE_1);
+ CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_DUMMY_STATE_2);
+ CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_DUMMY_STATE_3);
+ CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_DUMMY_STATE_4);
+ CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_L0_STATE);
+ CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_RECOVERY_RCVR_LOCK);
+ CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_RECOVERY_RCVR_LOCK_1);
+ CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_RECOVERY_RCVR_CFG);
+ CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_RECOVERY_RCVR_CFG_1);
+ CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_RECOVERY_IDLE);
+ CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_RECOVERY_IDLE_1);
+ CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_DISABLE_LINK);
+ CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_DISABLE_LINK_1);
+ CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_DISABLE_LINK_2);
+ CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_DISABLE_LINK_3);
+ CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_DISABLE_LINK_4);
+ CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_DISABLE_LINK_5);
+ CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_DISABLE_LINK_6);
+ CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_DISABLE_LINK_7);
+ CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_HOT_RESET);
+ CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_HOT_RESET_1);
+ CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_HOT_RESET_2);
+ CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_HOT_RESET_3);
+ CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_L0S_ENTRY);
+ CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_L0S_1);
+ CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_L0S_2);
+ CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_L0S_3);
+ CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_L0S_4);
+ CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_L0S_5);
+ CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_WAIT_FOR_LINK_TX);
+ CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_TX_FTS_ENTRY);
+ CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_TX_FTS_1);
+ CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_TX_FTS_2);
+ CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_TX_ELEC_IDLE_ST);
+ CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_TX_ELEC_IDLE_1);
+ CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_TX_ELEC_IDLE_2);
+ CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_TX_ELEC_IDLE_3);
+ CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_RECOVERY_SPEED);
+ CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_RECOVERY_SPEED_1);
+ CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_RECOVERY_SPEED_2);
+ CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_RECOVERY_SPEED_3);
+ CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_POLLING_COMPLIANCE_GEN23);
+ CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_POLLING_COMPLIANCE_GEN23_1);
+ CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_POLLING_COMPLIANCE_GEN23_2);
+ CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_POLLING_COMPLIANCE_GEN23_3);
+ CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_POLLING_COMPLIANCE_GEN23_4);
+ CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_POLLING_COMPLIANCE_GEN23_5);
+ CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_POLLING_COMPLIANCE_GEN23_6);
+ CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_POLLING_COMPLIANCE_GEN23_7);
+ CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_POLLING_COMPLIANCE_GEN23_8);
+ CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_LOOPBACK_SLAVE_ENTRY);
+ CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_LOOPBACK_SLAVE_ENTRY_FROM_RECOVERY);
+ CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_LOOPBACK_SLAVE_EXIT_1);
+ CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_LOOPBACK_SLAVE_EXIT);
+ CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_LOOPBACK_SLAVE_GEN2_1);
+ CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_LOOPBACK_SLAVE_GEN2_2);
+ CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_LOOPBACK_SLAVE_GEN2_3);
+ CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_LOOPBACK_SLAVE_GEN2_4);
+ CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_LOOPBACK_SLAVE_GEN2_5);
+ CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_LOOPBACK_SLAVE_ACTIVE);
+ CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_L1_ENTRY);
+ CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_L1_1);
+ CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_L1_2);
+ CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_L1_3);
+ CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_L1_4);
+ CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_L1_IDLE);
+ CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_L1_EXIT);
+ CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_L2_ENTRY);
+ CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_L2_1);
+ CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_L2_2);
+ CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_L2_3);
+ CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_L2_4);
+ CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_L2_5);
+ CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_L2_IDLE);
+ CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_LOOPBACK_MASTER_ENTRY);
+ CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_LOOPBACK_MASTER_ENTRY_1);
+ CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_LOOPBACK_MASTER_ENTRY_2);
+ CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_LOOPBACK_MASTER_ENTRY_3);
+ CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_LOOPBACK_MASTER_ENTRY_4);
+ CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_LOOPBACK_MASTER_ENTRY_5);
+ CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_LOOPBACK_MASTER_ENTRY_FROM_RECOVERY);
+ CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_LOOPBACK_MASTER_ACTIVE);
+ CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_LOOPBACK_MASTER_EXIT);
+ CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_LOOPBACK_MASTER_EXIT_1);
+ CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_LOOPBACK_MASTER_EXIT_2);
+ CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_RECOVERY_EQUALIZATION_PHASE0);
+ CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_RECOVERY_EQUALIZATION_PHASE1);
+ CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_RECOVERY_EQUALIZATION_PHASE2_1);
+ CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_RECOVERY_EQUALIZATION_PHASE2_2);
+ CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_RECOVERY_EQUALIZATION_PHASE3_1);
+ CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_RECOVERY_EQUALIZATION_PHASE3_2);
+ default:
+ str = "CDNS_PCIE_HPA_LTSSM_UNKNOWN";
+ break;
+ }
+
+ return str + strlen("CDNS_PCIE_HPA_LTSSM_");
+}
+
+static int ltssm_status_show(struct seq_file *s, void *v)
+{
+ struct cdns_pcie *pci = s->private;
+ enum cdns_pcie_hpa_ltssm hpa_ltssm;
+ const char *str_ltssm;
+ u32 val;
+
+ if (pci->is_hpa) {
+ val = cdns_pcie_hpa_readl(pci, REG_BANK_IP_REG,
+ CDNS_PCIE_HPA_PHY_DBG_STS_REG0);
+ hpa_ltssm = FIELD_GET(CDNS_PCIE_HPA_LTSSM_STATUS_MASK, val);
+ str_ltssm = cdns_pcie_hpa_ltssm_status_string(hpa_ltssm);
+ } else {
+ /* TODO: LGA IP*/
+ return 0;
+ }
+
+ seq_printf(s, "%s (0x%02x)\n", str_ltssm, hpa_ltssm);
+
+ return 0;
+}
+
+DEFINE_SHOW_ATTRIBUTE(ltssm_status);
+
+static void cdns_pcie_ltssm_debugfs_init(struct cdns_pcie *pci, struct dentry *dir)
+{
+ debugfs_create_file("ltssm_status", 0444, dir, pci,
+ <ssm_status_fops);
+}
+
+void cdns_pcie_debugfs_deinit(struct cdns_pcie *pci)
+{
+ if (!pci->debug_dir)
+ return;
+
+ debugfs_remove_recursive(pci->debug_dir);
+}
+EXPORT_SYMBOL_GPL(cdns_pcie_debugfs_deinit);
+
+void cdns_pcie_debugfs_init(struct cdns_pcie *pci)
+{
+ char dirname[CDNS_DEBUGFS_BUF_MAX];
+ struct device *dev = pci->dev;
+
+ /* Create main directory for each platform driver. */
+ snprintf(dirname, CDNS_DEBUGFS_BUF_MAX, "cdns_pcie_%s", dev_name(dev));
+ pci->debug_dir = debugfs_create_dir(dirname, NULL);
+
+ cdns_pcie_ltssm_debugfs_init(pci, pci->debug_dir);
+}
+EXPORT_SYMBOL_GPL(cdns_pcie_debugfs_init);
diff --git a/drivers/pci/controller/cadence/pcie-cadence-host-hpa.c b/drivers/pci/controller/cadence/pcie-cadence-host-hpa.c
index 0f540bed58e8..abc1d0e58b98 100644
--- a/drivers/pci/controller/cadence/pcie-cadence-host-hpa.c
+++ b/drivers/pci/controller/cadence/pcie-cadence-host-hpa.c
@@ -309,6 +309,17 @@ int cdns_pcie_hpa_host_link_setup(struct cdns_pcie_rc *rc)
}
EXPORT_SYMBOL_GPL(cdns_pcie_hpa_host_link_setup);
+void cdns_pcie_hpa_host_disable(struct cdns_pcie_rc *rc)
+{
+ struct pci_host_bridge *bridge;
+
+ cdns_pcie_debugfs_deinit(&rc->pcie);
+ bridge = pci_host_bridge_from_priv(rc);
+ pci_stop_root_bus(bridge->bus);
+ pci_remove_root_bus(bridge->bus);
+}
+EXPORT_SYMBOL_GPL(cdns_pcie_hpa_host_disable);
+
int cdns_pcie_hpa_host_setup(struct cdns_pcie_rc *rc)
{
struct device *dev = rc->pcie.dev;
@@ -360,7 +371,13 @@ int cdns_pcie_hpa_host_setup(struct cdns_pcie_rc *rc)
if (!bridge->ops)
bridge->ops = &cdns_pcie_hpa_host_ops;
- return pci_host_probe(bridge);
+ ret = pci_host_probe(bridge);
+ if (ret)
+ return ret;
+
+ cdns_pcie_debugfs_init(pcie);
+
+ return 0;
}
EXPORT_SYMBOL_GPL(cdns_pcie_hpa_host_setup);
diff --git a/drivers/pci/controller/cadence/pcie-cadence.h b/drivers/pci/controller/cadence/pcie-cadence.h
index 9a464cbaf073..2320319af83b 100644
--- a/drivers/pci/controller/cadence/pcie-cadence.h
+++ b/drivers/pci/controller/cadence/pcie-cadence.h
@@ -14,6 +14,8 @@
#include "pcie-cadence-lga-regs.h"
#include "pcie-cadence-hpa-regs.h"
+#define CDNS_PCIE_HPA_LTSSM_STATUS_MASK GENMASK(27, 20)
+
enum cdns_pcie_rp_bar {
RP_BAR_UNDEFINED = -1,
RP_BAR0,
@@ -42,6 +44,138 @@ enum cdns_pcie_reg_bank {
REG_BANKS_MAX,
};
+enum cdns_pcie_hpa_ltssm {
+ CDNS_PCIE_HPA_LTSSM_DETECT_QUIET = 0,
+ CDNS_PCIE_HPA_LTSSM_DETECT_QUIET_ENTRY = 1,
+ CDNS_PCIE_HPA_LTSSM_DETECT_ACTIVE = 2,
+ CDNS_PCIE_HPA_LTSSM_DETECT_ACTIVE_1 = 3,
+ CDNS_PCIE_HPA_LTSSM_DETECT_ACTIVE_2 = 4,
+ CDNS_PCIE_HPA_LTSSM_DETECT_ACTIVE_3 = 5,
+ CDNS_PCIE_HPA_LTSSM_RCVR_DETECTED_ST = 6,
+ CDNS_PCIE_HPA_LTSSM_RCVR_DETECTED_1 = 7,
+ CDNS_PCIE_HPA_LTSSM_POLLING_ACTIVE = 8,
+ CDNS_PCIE_HPA_LTSSM_POLLING_ACTIVE_1 = 9,
+ CDNS_PCIE_HPA_LTSSM_POLLING_ACTIVE_2 = 10,
+ CDNS_PCIE_HPA_LTSSM_POLLING_ACTIVE_3 = 11,
+ CDNS_PCIE_HPA_LTSSM_POLLING_COMPLIANCE = 12,
+ CDNS_PCIE_HPA_LTSSM_POLLING_COMPLIANCE_1 = 13,
+ CDNS_PCIE_HPA_LTSSM_POLLING_CONFIG = 14,
+ CDNS_PCIE_HPA_LTSSM_POLLING_CONFIG_1 = 15,
+ CDNS_PCIE_HPA_LTSSM_POLLING_CONFIG_2 = 16,
+ CDNS_PCIE_HPA_LTSSM_CONFIG_LW_START_RC = 17,
+ CDNS_PCIE_HPA_LTSSM_CONFIG_LW_START_RC_1 = 18,
+ CDNS_PCIE_HPA_LTSSM_CONFIG_LW_START_RC_2 = 19,
+ CDNS_PCIE_HPA_LTSSM_CONFIG_LW_ACC_RC = 20,
+ CDNS_PCIE_HPA_LTSSM_CONFIG_LANENUM_WAIT_RC = 21,
+ CDNS_PCIE_HPA_LTSSM_CONFIG_LANENUM_WAIT_RC_1 = 22,
+ CDNS_PCIE_HPA_LTSSM_CONFIG_LANENUM_ACC_RC = 23,
+ CDNS_PCIE_HPA_LTSSM_CONFIG_LW_START_EP = 24,
+ CDNS_PCIE_HPA_LTSSM_CONFIG_LW_START_EP_1 = 25,
+ CDNS_PCIE_HPA_LTSSM_CONFIG_LW_START_EP_2 = 26,
+ CDNS_PCIE_HPA_LTSSM_CONFIG_LW_ACC_EP = 27,
+ CDNS_PCIE_HPA_LTSSM_CONFIG_LANENUM_WAIT_EP = 28,
+ CDNS_PCIE_HPA_LTSSM_CONFIG_LANENUM_WAIT_EP_1 = 29,
+ CDNS_PCIE_HPA_LTSSM_CONFIG_LANENUM_ACC_EP = 30,
+ CDNS_PCIE_HPA_LTSSM_CONFIG_LANENUM_ACC_EP_1 = 31,
+ CDNS_PCIE_HPA_LTSSM_DUMMY_STATE_1 = 32,
+ CDNS_PCIE_HPA_LTSSM_CONFIG_COMPLETE = 33,
+ CDNS_PCIE_HPA_LTSSM_CONFIG_COMPLETE_1 = 34,
+ CDNS_PCIE_HPA_LTSSM_CONFIG_COMPLETE_2 = 35,
+ CDNS_PCIE_HPA_LTSSM_CONFIG_IDLE = 36,
+ CDNS_PCIE_HPA_LTSSM_CONFIG_IDLE_1 = 37,
+ CDNS_PCIE_HPA_LTSSM_DUMMY_STATE_2 = 38,
+ CDNS_PCIE_HPA_LTSSM_DUMMY_STATE_3 = 39,
+ CDNS_PCIE_HPA_LTSSM_DUMMY_STATE_4 = 40,
+ CDNS_PCIE_HPA_LTSSM_L0_STATE = 41,
+ CDNS_PCIE_HPA_LTSSM_RECOVERY_RCVR_LOCK = 42,
+ CDNS_PCIE_HPA_LTSSM_RECOVERY_RCVR_LOCK_1 = 43,
+ CDNS_PCIE_HPA_LTSSM_RECOVERY_RCVR_CFG = 44,
+ CDNS_PCIE_HPA_LTSSM_RECOVERY_RCVR_CFG_1 = 45,
+ CDNS_PCIE_HPA_LTSSM_RECOVERY_IDLE = 46,
+ CDNS_PCIE_HPA_LTSSM_RECOVERY_IDLE_1 = 47,
+ CDNS_PCIE_HPA_LTSSM_DISABLE_LINK = 48,
+ CDNS_PCIE_HPA_LTSSM_DISABLE_LINK_1 = 49,
+ CDNS_PCIE_HPA_LTSSM_DISABLE_LINK_2 = 50,
+ CDNS_PCIE_HPA_LTSSM_DISABLE_LINK_3 = 51,
+ CDNS_PCIE_HPA_LTSSM_DISABLE_LINK_4 = 52,
+ CDNS_PCIE_HPA_LTSSM_DISABLE_LINK_5 = 53,
+ CDNS_PCIE_HPA_LTSSM_DISABLE_LINK_6 = 54,
+ CDNS_PCIE_HPA_LTSSM_DISABLE_LINK_7 = 55,
+ CDNS_PCIE_HPA_LTSSM_HOT_RESET = 56,
+ CDNS_PCIE_HPA_LTSSM_HOT_RESET_1 = 57,
+ CDNS_PCIE_HPA_LTSSM_HOT_RESET_2 = 58,
+ CDNS_PCIE_HPA_LTSSM_HOT_RESET_3 = 59,
+ CDNS_PCIE_HPA_LTSSM_L0S_ENTRY = 60,
+ CDNS_PCIE_HPA_LTSSM_L0S_1 = 61,
+ CDNS_PCIE_HPA_LTSSM_L0S_2 = 62,
+ CDNS_PCIE_HPA_LTSSM_L0S_3 = 63,
+ CDNS_PCIE_HPA_LTSSM_L0S_4 = 64,
+ CDNS_PCIE_HPA_LTSSM_L0S_5 = 65,
+ CDNS_PCIE_HPA_LTSSM_WAIT_FOR_LINK_TX = 66,
+ CDNS_PCIE_HPA_LTSSM_TX_FTS_ENTRY = 67,
+ CDNS_PCIE_HPA_LTSSM_TX_FTS_1 = 68,
+ CDNS_PCIE_HPA_LTSSM_TX_FTS_2 = 69,
+ CDNS_PCIE_HPA_LTSSM_TX_ELEC_IDLE_ST = 70,
+ CDNS_PCIE_HPA_LTSSM_TX_ELEC_IDLE_1 = 71,
+ CDNS_PCIE_HPA_LTSSM_TX_ELEC_IDLE_2 = 72,
+ CDNS_PCIE_HPA_LTSSM_TX_ELEC_IDLE_3 = 73,
+ CDNS_PCIE_HPA_LTSSM_RECOVERY_SPEED = 74,
+ CDNS_PCIE_HPA_LTSSM_RECOVERY_SPEED_1 = 75,
+ CDNS_PCIE_HPA_LTSSM_RECOVERY_SPEED_2 = 76,
+ CDNS_PCIE_HPA_LTSSM_RECOVERY_SPEED_3 = 77,
+ CDNS_PCIE_HPA_LTSSM_POLLING_COMPLIANCE_GEN23 = 78,
+ CDNS_PCIE_HPA_LTSSM_POLLING_COMPLIANCE_GEN23_1 = 79,
+ CDNS_PCIE_HPA_LTSSM_POLLING_COMPLIANCE_GEN23_2 = 80,
+ CDNS_PCIE_HPA_LTSSM_POLLING_COMPLIANCE_GEN23_3 = 81,
+ CDNS_PCIE_HPA_LTSSM_POLLING_COMPLIANCE_GEN23_4 = 82,
+ CDNS_PCIE_HPA_LTSSM_POLLING_COMPLIANCE_GEN23_5 = 83,
+ CDNS_PCIE_HPA_LTSSM_POLLING_COMPLIANCE_GEN23_6 = 84,
+ CDNS_PCIE_HPA_LTSSM_POLLING_COMPLIANCE_GEN23_7 = 85,
+ CDNS_PCIE_HPA_LTSSM_POLLING_COMPLIANCE_GEN23_8 = 86,
+ CDNS_PCIE_HPA_LTSSM_LOOPBACK_SLAVE_ENTRY = 87,
+ CDNS_PCIE_HPA_LTSSM_LOOPBACK_SLAVE_ENTRY_FROM_RECOVERY = 88,
+ CDNS_PCIE_HPA_LTSSM_LOOPBACK_SLAVE_EXIT_1 = 89,
+ CDNS_PCIE_HPA_LTSSM_LOOPBACK_SLAVE_EXIT = 90,
+ CDNS_PCIE_HPA_LTSSM_LOOPBACK_SLAVE_GEN2_1 = 91,
+ CDNS_PCIE_HPA_LTSSM_LOOPBACK_SLAVE_GEN2_2 = 92,
+ CDNS_PCIE_HPA_LTSSM_LOOPBACK_SLAVE_GEN2_3 = 93,
+ CDNS_PCIE_HPA_LTSSM_LOOPBACK_SLAVE_GEN2_4 = 94,
+ CDNS_PCIE_HPA_LTSSM_LOOPBACK_SLAVE_GEN2_5 = 95,
+ CDNS_PCIE_HPA_LTSSM_LOOPBACK_SLAVE_ACTIVE = 96,
+ CDNS_PCIE_HPA_LTSSM_L1_ENTRY = 97,
+ CDNS_PCIE_HPA_LTSSM_L1_1 = 98,
+ CDNS_PCIE_HPA_LTSSM_L1_2 = 99,
+ CDNS_PCIE_HPA_LTSSM_L1_3 = 100,
+ CDNS_PCIE_HPA_LTSSM_L1_4 = 101,
+ CDNS_PCIE_HPA_LTSSM_L1_IDLE = 102,
+ CDNS_PCIE_HPA_LTSSM_L1_EXIT = 103,
+ CDNS_PCIE_HPA_LTSSM_L2_ENTRY = 104,
+ CDNS_PCIE_HPA_LTSSM_L2_1 = 105,
+ CDNS_PCIE_HPA_LTSSM_L2_2 = 106,
+ CDNS_PCIE_HPA_LTSSM_L2_3 = 107,
+ CDNS_PCIE_HPA_LTSSM_L2_4 = 108,
+ CDNS_PCIE_HPA_LTSSM_L2_5 = 109,
+ CDNS_PCIE_HPA_LTSSM_L2_IDLE = 110,
+ CDNS_PCIE_HPA_LTSSM_LOOPBACK_MASTER_ENTRY = 111,
+ CDNS_PCIE_HPA_LTSSM_LOOPBACK_MASTER_ENTRY_1 = 112,
+ CDNS_PCIE_HPA_LTSSM_LOOPBACK_MASTER_ENTRY_2 = 113,
+ CDNS_PCIE_HPA_LTSSM_LOOPBACK_MASTER_ENTRY_3 = 114,
+ CDNS_PCIE_HPA_LTSSM_LOOPBACK_MASTER_ENTRY_4 = 115,
+ CDNS_PCIE_HPA_LTSSM_LOOPBACK_MASTER_ENTRY_5 = 116,
+ CDNS_PCIE_HPA_LTSSM_LOOPBACK_MASTER_ENTRY_FROM_RECOVERY = 117,
+ CDNS_PCIE_HPA_LTSSM_LOOPBACK_MASTER_ACTIVE = 118,
+ CDNS_PCIE_HPA_LTSSM_LOOPBACK_MASTER_EXIT = 119,
+ CDNS_PCIE_HPA_LTSSM_LOOPBACK_MASTER_EXIT_1 = 120,
+ CDNS_PCIE_HPA_LTSSM_LOOPBACK_MASTER_EXIT_2 = 121,
+ CDNS_PCIE_HPA_LTSSM_RECOVERY_EQUALIZATION_PHASE0 = 122,
+ CDNS_PCIE_HPA_LTSSM_RECOVERY_EQUALIZATION_PHASE1 = 123,
+ CDNS_PCIE_HPA_LTSSM_RECOVERY_EQUALIZATION_PHASE2_1 = 124,
+ CDNS_PCIE_HPA_LTSSM_RECOVERY_EQUALIZATION_PHASE2_2 = 125,
+ CDNS_PCIE_HPA_LTSSM_RECOVERY_EQUALIZATION_PHASE3_1 = 126,
+ CDNS_PCIE_HPA_LTSSM_RECOVERY_EQUALIZATION_PHASE3_2 = 127,
+ CDNS_PCIE_HPA_LTSSM_UNKNOWN = 0xFFFFFFFF,
+};
+
struct cdns_pcie_ops {
int (*start_link)(struct cdns_pcie *pcie);
void (*stop_link)(struct cdns_pcie *pcie);
@@ -87,6 +221,7 @@ struct cdns_plat_pcie_of_data {
* @ops: Platform-specific ops to control various inputs from Cadence PCIe
* wrapper
* @cdns_pcie_reg_offsets: Register bank offsets for different SoC
+ * @debug_dir: debugfs node
*/
struct cdns_pcie {
void __iomem *reg_base;
@@ -100,6 +235,7 @@ struct cdns_pcie {
struct device_link **link;
const struct cdns_pcie_ops *ops;
const struct cdns_plat_pcie_of_data *cdns_pcie_reg_offsets;
+ struct dentry *debug_dir;
};
/**
@@ -447,6 +583,7 @@ void cdns_pcie_host_disable(struct cdns_pcie_rc *rc);
void __iomem *cdns_pci_map_bus(struct pci_bus *bus, unsigned int devfn,
int where);
int cdns_pcie_hpa_host_setup(struct cdns_pcie_rc *rc);
+void cdns_pcie_hpa_host_disable(struct cdns_pcie_rc *rc);
#else
static inline int cdns_pcie_host_link_setup(struct cdns_pcie_rc *rc)
{
@@ -472,6 +609,10 @@ static inline void cdns_pcie_host_disable(struct cdns_pcie_rc *rc)
{
}
+static inline void cdns_pcie_hpa_host_disable(struct cdns_pcie_rc *rc)
+{
+}
+
static inline void __iomem *cdns_pci_map_bus(struct pci_bus *bus, unsigned int devfn,
int where)
{
@@ -535,4 +676,16 @@ bool cdns_pcie_hpa_link_up(struct cdns_pcie *pcie);
extern const struct dev_pm_ops cdns_pcie_pm_ops;
+#ifdef CONFIG_PCIE_CADENCE_DEBUGFS
+void cdns_pcie_debugfs_deinit(struct cdns_pcie *pci);
+void cdns_pcie_debugfs_init(struct cdns_pcie *pci);
+#else
+static inline void cdns_pcie_debugfs_deinit(struct cdns_pcie *pci)
+{
+}
+static inline void cdns_pcie_debugfs_init(struct cdns_pcie *pci)
+{
+}
+#endif
+
#endif /* _PCIE_CADENCE_H */
--
2.43.0
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH v6 3/3] PCI: cadence: Add LGA IP debugfs for LTSSM status
2026-05-19 12:36 [PATCH v6 0/3] PCI: cadence: Add LTSSM debugfs Hans Zhang
2026-05-19 12:36 ` [PATCH v6 1/3] PCI: cadence: Add HPA architecture flag Hans Zhang
2026-05-19 12:36 ` [PATCH v6 2/3] PCI: cadence: Add HPA IP debugfs for LTSSM status Hans Zhang
@ 2026-05-19 12:36 ` Hans Zhang
2026-05-20 2:34 ` Manikandan Karunakaran Pillai
2 siblings, 1 reply; 13+ messages in thread
From: Hans Zhang @ 2026-05-19 12:36 UTC (permalink / raw)
To: bhelgaas, lpieralisi, kwilczynski, mani
Cc: robh, mpillai, a-garg7, s-vadapalli, linux-pci, linux-kernel,
Hans Zhang
Extend debugfs support to LGA-based Cadence PCIe controllers. The
'ltssm_status' file now works for both HPA and LGA IP by selecting the
appropriate register access based on the 'is_hpa' flag.
Signed-off-by: Hans Zhang <18255117159@163.com>
---
.../controller/cadence/pcie-cadence-debugfs.c | 61 ++++++++++++++++++-
.../pci/controller/cadence/pcie-cadence-ep.c | 3 +
.../controller/cadence/pcie-cadence-host.c | 9 ++-
drivers/pci/controller/cadence/pcie-cadence.h | 43 +++++++++++++
4 files changed, 112 insertions(+), 4 deletions(-)
diff --git a/drivers/pci/controller/cadence/pcie-cadence-debugfs.c b/drivers/pci/controller/cadence/pcie-cadence-debugfs.c
index 97c5deef2b1a..0a308f95e9f6 100644
--- a/drivers/pci/controller/cadence/pcie-cadence-debugfs.c
+++ b/drivers/pci/controller/cadence/pcie-cadence-debugfs.c
@@ -13,6 +13,58 @@
#define CDNS_DEBUGFS_BUF_MAX 128
+static const char *cdns_pcie_lga_ltssm_status_string(enum cdns_pcie_lga_ltssm ltssm)
+{
+ const char *str;
+
+ switch (ltssm) {
+#define CDNS_PCIE_LGA_LTSSM_NAME(n) case n: str = #n; break
+ CDNS_PCIE_LGA_LTSSM_NAME(CDNS_PCIE_LGA_LTSSM_DETECT_QUIET);
+ CDNS_PCIE_LGA_LTSSM_NAME(CDNS_PCIE_LGA_LTSSM_DETECT_ACTIVE);
+ CDNS_PCIE_LGA_LTSSM_NAME(CDNS_PCIE_LGA_LTSSM_POLLING_ACTIVE);
+ CDNS_PCIE_LGA_LTSSM_NAME(CDNS_PCIE_LGA_LTSSM_POLLING_COMPLIANCE);
+ CDNS_PCIE_LGA_LTSSM_NAME(CDNS_PCIE_LGA_LTSSM_POLLING_CONFIGURATION);
+ CDNS_PCIE_LGA_LTSSM_NAME(CDNS_PCIE_LGA_LTSSM_CONFIGURATION_LINKWIDTH_START);
+ CDNS_PCIE_LGA_LTSSM_NAME(CDNS_PCIE_LGA_LTSSM_CONFIGURATION_LINKWIDTH_ACCEPT);
+ CDNS_PCIE_LGA_LTSSM_NAME(CDNS_PCIE_LGA_LTSSM_CONFIGURATION_LANENUM_ACCEPT);
+ CDNS_PCIE_LGA_LTSSM_NAME(CDNS_PCIE_LGA_LTSSM_CONFIGURATION_LANENUM_WAIT);
+ CDNS_PCIE_LGA_LTSSM_NAME(CDNS_PCIE_LGA_LTSSM_CONFIGURATION_COMPLETE);
+ CDNS_PCIE_LGA_LTSSM_NAME(CDNS_PCIE_LGA_LTSSM_CONFIGURATION_IDLE);
+ CDNS_PCIE_LGA_LTSSM_NAME(CDNS_PCIE_LGA_LTSSM_RECOVERY_RCVRLOCK);
+ CDNS_PCIE_LGA_LTSSM_NAME(CDNS_PCIE_LGA_LTSSM_RECOVERY_SPEED);
+ CDNS_PCIE_LGA_LTSSM_NAME(CDNS_PCIE_LGA_LTSSM_RECOVERY_RCVRCFG);
+ CDNS_PCIE_LGA_LTSSM_NAME(CDNS_PCIE_LGA_LTSSM_RECOVERY_IDLE);
+ CDNS_PCIE_LGA_LTSSM_NAME(CDNS_PCIE_LGA_LTSSM_L0);
+ CDNS_PCIE_LGA_LTSSM_NAME(CDNS_PCIE_LGA_LTSSM_RX_L0S_ENTRY);
+ CDNS_PCIE_LGA_LTSSM_NAME(CDNS_PCIE_LGA_LTSSM_RX_L0S_IDLE);
+ CDNS_PCIE_LGA_LTSSM_NAME(CDNS_PCIE_LGA_LTSSM_RX_L0S_FTS);
+ CDNS_PCIE_LGA_LTSSM_NAME(CDNS_PCIE_LGA_LTSSM_TX_L0S_ENTRY);
+ CDNS_PCIE_LGA_LTSSM_NAME(CDNS_PCIE_LGA_LTSSM_TX_L0S_IDLE);
+ CDNS_PCIE_LGA_LTSSM_NAME(CDNS_PCIE_LGA_LTSSM_TX_L0S_FTS);
+ CDNS_PCIE_LGA_LTSSM_NAME(CDNS_PCIE_LGA_LTSSM_L1_ENTRY);
+ CDNS_PCIE_LGA_LTSSM_NAME(CDNS_PCIE_LGA_LTSSM_L1_IDLE);
+ CDNS_PCIE_LGA_LTSSM_NAME(CDNS_PCIE_LGA_LTSSM_L2_IDLE);
+ CDNS_PCIE_LGA_LTSSM_NAME(CDNS_PCIE_LGA_LTSSM_L2_TRANSMITWAKE);
+ CDNS_PCIE_LGA_LTSSM_NAME(CDNS_PCIE_LGA_LTSSM_DISABLED);
+ CDNS_PCIE_LGA_LTSSM_NAME(CDNS_PCIE_LGA_LTSSM_LOOPBACK_ENTRY_MASTER);
+ CDNS_PCIE_LGA_LTSSM_NAME(CDNS_PCIE_LGA_LTSSM_LOOPBACK_ACTIVE_MASTER);
+ CDNS_PCIE_LGA_LTSSM_NAME(CDNS_PCIE_LGA_LTSSM_LOOPBACK_EXIT_MASTER);
+ CDNS_PCIE_LGA_LTSSM_NAME(CDNS_PCIE_LGA_LTSSM_LOOPBACK_ENTRY_SLAVE);
+ CDNS_PCIE_LGA_LTSSM_NAME(CDNS_PCIE_LGA_LTSSM_LOOPBACK_ACTIVE_SLAVE);
+ CDNS_PCIE_LGA_LTSSM_NAME(CDNS_PCIE_LGA_LTSSM_LOOPBACK_EXIT_SLAVE);
+ CDNS_PCIE_LGA_LTSSM_NAME(CDNS_PCIE_LGA_LTSSM_HOT_RESET);
+ CDNS_PCIE_LGA_LTSSM_NAME(CDNS_PCIE_LGA_LTSSM_RECOVERY_EQUALIZATION_PHASE_0);
+ CDNS_PCIE_LGA_LTSSM_NAME(CDNS_PCIE_LGA_LTSSM_RECOVERY_EQUALIZATION_PHASE_1);
+ CDNS_PCIE_LGA_LTSSM_NAME(CDNS_PCIE_LGA_LTSSM_RECOVERY_EQUALIZATION_PHASE_2);
+ CDNS_PCIE_LGA_LTSSM_NAME(CDNS_PCIE_LGA_LTSSM_RECOVERY_EQUALIZATION_PHASE_3);
+ default:
+ str = "CDNS_PCIE_LGA_LTSSM_UNKNOWN";
+ break;
+ }
+
+ return str + strlen("CDNS_PCIE_LGA_LTSSM_");
+}
+
static const char *cdns_pcie_hpa_ltssm_status_string(enum cdns_pcie_hpa_ltssm ltssm)
{
const char *str;
@@ -158,6 +210,7 @@ static const char *cdns_pcie_hpa_ltssm_status_string(enum cdns_pcie_hpa_ltssm lt
static int ltssm_status_show(struct seq_file *s, void *v)
{
struct cdns_pcie *pci = s->private;
+ enum cdns_pcie_lga_ltssm lga_ltssm;
enum cdns_pcie_hpa_ltssm hpa_ltssm;
const char *str_ltssm;
u32 val;
@@ -168,11 +221,13 @@ static int ltssm_status_show(struct seq_file *s, void *v)
hpa_ltssm = FIELD_GET(CDNS_PCIE_HPA_LTSSM_STATUS_MASK, val);
str_ltssm = cdns_pcie_hpa_ltssm_status_string(hpa_ltssm);
} else {
- /* TODO: LGA IP*/
- return 0;
+ val = cdns_pcie_readl(pci, CDNS_PCIE_LM_BASE);
+ lga_ltssm = FIELD_GET(CDNS_PCIE_LGA_LTSSM_STATUS_MASK, val);
+ str_ltssm = cdns_pcie_lga_ltssm_status_string(lga_ltssm);
}
- seq_printf(s, "%s (0x%02x)\n", str_ltssm, hpa_ltssm);
+ seq_printf(s, "%s (0x%02x)\n", str_ltssm,
+ pci->is_hpa ? hpa_ltssm : lga_ltssm);
return 0;
}
diff --git a/drivers/pci/controller/cadence/pcie-cadence-ep.c b/drivers/pci/controller/cadence/pcie-cadence-ep.c
index c0e1194a936b..370b19f4d38f 100644
--- a/drivers/pci/controller/cadence/pcie-cadence-ep.c
+++ b/drivers/pci/controller/cadence/pcie-cadence-ep.c
@@ -655,6 +655,7 @@ void cdns_pcie_ep_disable(struct cdns_pcie_ep *ep)
struct device *dev = ep->pcie.dev;
struct pci_epc *epc = to_pci_epc(dev);
+ cdns_pcie_debugfs_deinit(&ep->pcie);
pci_epc_deinit_notify(epc);
pci_epc_mem_free_addr(epc, ep->irq_phys_addr, ep->irq_cpu_addr,
SZ_128K);
@@ -761,6 +762,8 @@ int cdns_pcie_ep_setup(struct cdns_pcie_ep *ep)
pci_epc_init_notify(epc);
+ cdns_pcie_debugfs_init(pcie);
+
return 0;
free_epc_mem:
diff --git a/drivers/pci/controller/cadence/pcie-cadence-host.c b/drivers/pci/controller/cadence/pcie-cadence-host.c
index 0bc9e6e90e0e..8105bb625eb7 100644
--- a/drivers/pci/controller/cadence/pcie-cadence-host.c
+++ b/drivers/pci/controller/cadence/pcie-cadence-host.c
@@ -364,6 +364,7 @@ void cdns_pcie_host_disable(struct cdns_pcie_rc *rc)
{
struct pci_host_bridge *bridge;
+ cdns_pcie_debugfs_deinit(&rc->pcie);
bridge = pci_host_bridge_from_priv(rc);
pci_stop_root_bus(bridge->bus);
pci_remove_root_bus(bridge->bus);
@@ -423,7 +424,13 @@ int cdns_pcie_host_setup(struct cdns_pcie_rc *rc)
if (!bridge->ops)
bridge->ops = &cdns_pcie_host_ops;
- return pci_host_probe(bridge);
+ ret = pci_host_probe(bridge);
+ if (ret)
+ return ret;
+
+ cdns_pcie_debugfs_init(pcie);
+
+ return 0;
}
EXPORT_SYMBOL_GPL(cdns_pcie_host_setup);
diff --git a/drivers/pci/controller/cadence/pcie-cadence.h b/drivers/pci/controller/cadence/pcie-cadence.h
index 2320319af83b..8bc6564c65b9 100644
--- a/drivers/pci/controller/cadence/pcie-cadence.h
+++ b/drivers/pci/controller/cadence/pcie-cadence.h
@@ -14,6 +14,7 @@
#include "pcie-cadence-lga-regs.h"
#include "pcie-cadence-hpa-regs.h"
+#define CDNS_PCIE_LGA_LTSSM_STATUS_MASK GENMASK(29, 24)
#define CDNS_PCIE_HPA_LTSSM_STATUS_MASK GENMASK(27, 20)
enum cdns_pcie_rp_bar {
@@ -44,6 +45,48 @@ enum cdns_pcie_reg_bank {
REG_BANKS_MAX,
};
+enum cdns_pcie_lga_ltssm {
+ CDNS_PCIE_LGA_LTSSM_DETECT_QUIET = 0x00,
+ CDNS_PCIE_LGA_LTSSM_DETECT_ACTIVE = 0x01,
+ CDNS_PCIE_LGA_LTSSM_POLLING_ACTIVE = 0x02,
+ CDNS_PCIE_LGA_LTSSM_POLLING_COMPLIANCE = 0x03,
+ CDNS_PCIE_LGA_LTSSM_POLLING_CONFIGURATION = 0x04,
+ CDNS_PCIE_LGA_LTSSM_CONFIGURATION_LINKWIDTH_START = 0x05,
+ CDNS_PCIE_LGA_LTSSM_CONFIGURATION_LINKWIDTH_ACCEPT = 0x06,
+ CDNS_PCIE_LGA_LTSSM_CONFIGURATION_LANENUM_ACCEPT = 0x07,
+ CDNS_PCIE_LGA_LTSSM_CONFIGURATION_LANENUM_WAIT = 0x08,
+ CDNS_PCIE_LGA_LTSSM_CONFIGURATION_COMPLETE = 0x09,
+ CDNS_PCIE_LGA_LTSSM_CONFIGURATION_IDLE = 0x0A,
+ CDNS_PCIE_LGA_LTSSM_RECOVERY_RCVRLOCK = 0x0B,
+ CDNS_PCIE_LGA_LTSSM_RECOVERY_SPEED = 0x0C,
+ CDNS_PCIE_LGA_LTSSM_RECOVERY_RCVRCFG = 0x0D,
+ CDNS_PCIE_LGA_LTSSM_RECOVERY_IDLE = 0x0E,
+ CDNS_PCIE_LGA_LTSSM_L0 = 0x10,
+ CDNS_PCIE_LGA_LTSSM_RX_L0S_ENTRY = 0x11,
+ CDNS_PCIE_LGA_LTSSM_RX_L0S_IDLE = 0x12,
+ CDNS_PCIE_LGA_LTSSM_RX_L0S_FTS = 0x13,
+ CDNS_PCIE_LGA_LTSSM_TX_L0S_ENTRY = 0x14,
+ CDNS_PCIE_LGA_LTSSM_TX_L0S_IDLE = 0x15,
+ CDNS_PCIE_LGA_LTSSM_TX_L0S_FTS = 0x16,
+ CDNS_PCIE_LGA_LTSSM_L1_ENTRY = 0x17,
+ CDNS_PCIE_LGA_LTSSM_L1_IDLE = 0x18,
+ CDNS_PCIE_LGA_LTSSM_L2_IDLE = 0x19,
+ CDNS_PCIE_LGA_LTSSM_L2_TRANSMITWAKE = 0x1A,
+ CDNS_PCIE_LGA_LTSSM_DISABLED = 0x20,
+ CDNS_PCIE_LGA_LTSSM_LOOPBACK_ENTRY_MASTER = 0x21,
+ CDNS_PCIE_LGA_LTSSM_LOOPBACK_ACTIVE_MASTER = 0x22,
+ CDNS_PCIE_LGA_LTSSM_LOOPBACK_EXIT_MASTER = 0x23,
+ CDNS_PCIE_LGA_LTSSM_LOOPBACK_ENTRY_SLAVE = 0x24,
+ CDNS_PCIE_LGA_LTSSM_LOOPBACK_ACTIVE_SLAVE = 0x25,
+ CDNS_PCIE_LGA_LTSSM_LOOPBACK_EXIT_SLAVE = 0x26,
+ CDNS_PCIE_LGA_LTSSM_HOT_RESET = 0x27,
+ CDNS_PCIE_LGA_LTSSM_RECOVERY_EQUALIZATION_PHASE_0 = 0x28,
+ CDNS_PCIE_LGA_LTSSM_RECOVERY_EQUALIZATION_PHASE_1 = 0x29,
+ CDNS_PCIE_LGA_LTSSM_RECOVERY_EQUALIZATION_PHASE_2 = 0x2A,
+ CDNS_PCIE_LGA_LTSSM_RECOVERY_EQUALIZATION_PHASE_3 = 0x2B,
+ CDNS_PCIE_LGA_LTSSM_UNKNOWN = 0xFFFFFFFF,
+};
+
enum cdns_pcie_hpa_ltssm {
CDNS_PCIE_HPA_LTSSM_DETECT_QUIET = 0,
CDNS_PCIE_HPA_LTSSM_DETECT_QUIET_ENTRY = 1,
--
2.43.0
^ permalink raw reply related [flat|nested] 13+ messages in thread
* Re: [PATCH v6 2/3] PCI: cadence: Add HPA IP debugfs for LTSSM status
2026-05-19 12:36 ` [PATCH v6 2/3] PCI: cadence: Add HPA IP debugfs for LTSSM status Hans Zhang
@ 2026-05-19 13:20 ` sashiko-bot
2026-05-20 7:26 ` Aksh Garg
1 sibling, 0 replies; 13+ messages in thread
From: sashiko-bot @ 2026-05-19 13:20 UTC (permalink / raw)
To: Hans Zhang; +Cc: linux-pci
Thank you for your contribution! Sashiko AI review found 4 potential issue(s) to consider:
- [High] Unprotected hardware register access in the debugfs read callback can cause a kernel panic if the device is runtime suspended.
- [High] Race condition during root bus teardown due to missing `pci_lock_rescan_remove()`.
- [Medium] Debugfs feature silently fails to initialize when compiled as a module due to incorrect Kconfig and preprocessor macro interaction.
- [Medium] The patch implicitly introduces critical behavioral changes (root bus teardown) not mentioned in the commit message.
--
commit 32300cb8f3d354c5d2edc089c48c2f9d49fdb425
Author: Hans Zhang <18255117159@163.com>
PCI: cadence: Add HPA IP debugfs for LTSSM status
This commit adds debugfs support for HPA-based Cadence PCIe controllers to
allow users to read the current LTSSM state. It also introduces root bus
teardown logic during device removal.
> Add debugfs support for HPA-based Cadence PCIe controllers. A new file
> 'ltssm_status' is created under debugfs, allowing users to read the
> current LTSSM state as a string and raw value.
This isn't a bug, but the patch appears to introduce behavioral changes for
root bus teardown (adding pci_stop_root_bus() and pci_remove_root_bus() via
cdns_pcie_hpa_host_disable()) that aren't mentioned in the commit message.
Should this bus teardown logic be split into a separate patch, or documented
in the commit message?
> diff --git a/drivers/pci/controller/cadence/Kconfig b/drivers/pci/controller/cadence/Kconfig
> index 9e651d5459735..cb010bc97aad3 100644
> --- a/drivers/pci/controller/cadence/Kconfig
> +++ b/drivers/pci/controller/cadence/Kconfig
> @@ -6,6 +6,15 @@ menu "Cadence-based PCIe controllers"
> config PCIE_CADENCE
> tristate
>
> +config PCIE_CADENCE_DEBUGFS
> + tristate "Cadence PCIe debugfs entries"
Could this cause silent failures if configured as a module?
If a user configures this as a module (=m), Kbuild will define
CONFIG_PCIE_CADENCE_DEBUGFS_MODULE instead of CONFIG_PCIE_CADENCE_DEBUGFS.
Because pcie-cadence.h guards the function declarations with
#ifdef CONFIG_PCIE_CADENCE_DEBUGFS, the core drivers will compile against
the empty static inline dummy functions instead.
Additionally, if we fix the macro to use IS_ENABLED(), would it cause linker
errors if the core driver is built-in (=y) but the debugfs is built as a
module (=m)?
Should this configuration option be changed to a bool?
[ ... ]
> diff --git a/drivers/pci/controller/cadence/pcie-cadence-debugfs.c b/drivers/pci/controller/cadence/pcie-cadence-debugfs.c
> new file mode 100644
> index 0000000000000..97c5deef2b1ab
> --- /dev/null
> +++ b/drivers/pci/controller/cadence/pcie-cadence-debugfs.c
[ ... ]
> +static int ltssm_status_show(struct seq_file *s, void *v)
> +{
> + struct cdns_pcie *pci = s->private;
> + enum cdns_pcie_hpa_ltssm hpa_ltssm;
> + const char *str_ltssm;
> + u32 val;
> +
> + if (pci->is_hpa) {
> + val = cdns_pcie_hpa_readl(pci, REG_BANK_IP_REG,
> + CDNS_PCIE_HPA_PHY_DBG_STS_REG0);
Could accessing this register cause a kernel panic if the device is
runtime suspended?
Cadence PCIe platform drivers rely on runtime power management and will gate
clocks and power domains when idle.
If a user reads this debugfs file while the controller is runtime suspended,
will reading the memory-mapped register of a powered-off IP block trigger
a synchronous external abort?
Should this hardware access be wrapped with pm_runtime_get_sync(pci->dev)
and pm_runtime_put(pci->dev)?
[ ... ]
> diff --git a/drivers/pci/controller/cadence/pcie-cadence-host-hpa.c b/drivers/pci/controller/cadence/pcie-cadence-host-hpa.c
> index 0f540bed58e88..abc1d0e58b981 100644
> --- a/drivers/pci/controller/cadence/pcie-cadence-host-hpa.c
> +++ b/drivers/pci/controller/cadence/pcie-cadence-host-hpa.c
[ ... ]
> +void cdns_pcie_hpa_host_disable(struct cdns_pcie_rc *rc)
> +{
> + struct pci_host_bridge *bridge;
> +
> + cdns_pcie_debugfs_deinit(&rc->pcie);
> + bridge = pci_host_bridge_from_priv(rc);
> + pci_stop_root_bus(bridge->bus);
> + pci_remove_root_bus(bridge->bus);
> +}
Could this lead to a race condition during root bus teardown?
Calling pci_stop_root_bus() and pci_remove_root_bus() without holding the
PCI rescan lock allows race conditions with concurrent PCI rescan or hotplug
operations triggered via sysfs.
While this pattern might have been copied from a pre-existing function like
cdns_pcie_host_disable(), does it need to be fixed here to prevent
use-after-free or system crashes?
Should these operations be protected by acquiring the lock using
pci_lock_rescan_remove() and pci_unlock_rescan_remove()?
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260519123609.1595280-1-18255117159@163.com?part=2
^ permalink raw reply [flat|nested] 13+ messages in thread
* RE: [PATCH v6 3/3] PCI: cadence: Add LGA IP debugfs for LTSSM status
2026-05-19 12:36 ` [PATCH v6 3/3] PCI: cadence: Add LGA " Hans Zhang
@ 2026-05-20 2:34 ` Manikandan Karunakaran Pillai
2026-05-20 2:59 ` Hans Zhang
0 siblings, 1 reply; 13+ messages in thread
From: Manikandan Karunakaran Pillai @ 2026-05-20 2:34 UTC (permalink / raw)
To: Hans Zhang, bhelgaas@google.com, lpieralisi@kernel.org,
kwilczynski@kernel.org, mani@kernel.org
Cc: robh@kernel.org, a-garg7@ti.com, s-vadapalli@ti.com,
linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org
>EXTERNAL MAIL
>
>
>Extend debugfs support to LGA-based Cadence PCIe controllers. The
>'ltssm_status' file now works for both HPA and LGA IP by selecting the
>appropriate register access based on the 'is_hpa' flag.
>
>Signed-off-by: Hans Zhang <18255117159@163.com>
>---
> .../controller/cadence/pcie-cadence-debugfs.c | 61 ++++++++++++++++++-
> .../pci/controller/cadence/pcie-cadence-ep.c | 3 +
> .../controller/cadence/pcie-cadence-host.c | 9 ++-
> drivers/pci/controller/cadence/pcie-cadence.h | 43 +++++++++++++
> 4 files changed, 112 insertions(+), 4 deletions(-)
>
>diff --git a/drivers/pci/controller/cadence/pcie-cadence-debugfs.c
>b/drivers/pci/controller/cadence/pcie-cadence-debugfs.c
>index 97c5deef2b1a..0a308f95e9f6 100644
>--- a/drivers/pci/controller/cadence/pcie-cadence-debugfs.c
>+++ b/drivers/pci/controller/cadence/pcie-cadence-debugfs.c
>@@ -13,6 +13,58 @@
>
> #define CDNS_DEBUGFS_BUF_MAX 128
Where is CDNS_DEBUGFS_BUF_MAX used for ?
>
>+static const char *cdns_pcie_lga_ltssm_status_string(enum
>cdns_pcie_lga_ltssm ltssm)
>+{
>+ const char *str;
>+
>+ switch (ltssm) {
>+#define CDNS_PCIE_LGA_LTSSM_NAME(n) case n: str = #n; break
>+
> CDNS_PCIE_LGA_LTSSM_NAME(CDNS_PCIE_LGA_LTSSM_DETECT_QUI
>ET);
>+
> CDNS_PCIE_LGA_LTSSM_NAME(CDNS_PCIE_LGA_LTSSM_DETECT_ACTI
>VE);
>+
> CDNS_PCIE_LGA_LTSSM_NAME(CDNS_PCIE_LGA_LTSSM_POLLING_AC
>TIVE);
>+
> CDNS_PCIE_LGA_LTSSM_NAME(CDNS_PCIE_LGA_LTSSM_POLLING_CO
>MPLIANCE);
>+
> CDNS_PCIE_LGA_LTSSM_NAME(CDNS_PCIE_LGA_LTSSM_POLLING_CO
>NFIGURATION);
>+
> CDNS_PCIE_LGA_LTSSM_NAME(CDNS_PCIE_LGA_LTSSM_CONFIGURAT
>ION_LINKWIDTH_START);
>+
> CDNS_PCIE_LGA_LTSSM_NAME(CDNS_PCIE_LGA_LTSSM_CONFIGURAT
>ION_LINKWIDTH_ACCEPT);
>+
> CDNS_PCIE_LGA_LTSSM_NAME(CDNS_PCIE_LGA_LTSSM_CONFIGURAT
>ION_LANENUM_ACCEPT);
>+
> CDNS_PCIE_LGA_LTSSM_NAME(CDNS_PCIE_LGA_LTSSM_CONFIGURAT
>ION_LANENUM_WAIT);
>+
> CDNS_PCIE_LGA_LTSSM_NAME(CDNS_PCIE_LGA_LTSSM_CONFIGURAT
>ION_COMPLETE);
>+
> CDNS_PCIE_LGA_LTSSM_NAME(CDNS_PCIE_LGA_LTSSM_CONFIGURAT
>ION_IDLE);
>+
> CDNS_PCIE_LGA_LTSSM_NAME(CDNS_PCIE_LGA_LTSSM_RECOVERY_R
>CVRLOCK);
>+
> CDNS_PCIE_LGA_LTSSM_NAME(CDNS_PCIE_LGA_LTSSM_RECOVERY_S
>PEED);
>+
> CDNS_PCIE_LGA_LTSSM_NAME(CDNS_PCIE_LGA_LTSSM_RECOVERY_R
>CVRCFG);
>+
> CDNS_PCIE_LGA_LTSSM_NAME(CDNS_PCIE_LGA_LTSSM_RECOVERY_I
>DLE);
>+ CDNS_PCIE_LGA_LTSSM_NAME(CDNS_PCIE_LGA_LTSSM_L0);
>+
> CDNS_PCIE_LGA_LTSSM_NAME(CDNS_PCIE_LGA_LTSSM_RX_L0S_ENTR
>Y);
>+
> CDNS_PCIE_LGA_LTSSM_NAME(CDNS_PCIE_LGA_LTSSM_RX_L0S_IDLE)
>;
>+ CDNS_PCIE_LGA_LTSSM_NAME(CDNS_PCIE_LGA_LTSSM_RX_L0S_FTS);
>+
> CDNS_PCIE_LGA_LTSSM_NAME(CDNS_PCIE_LGA_LTSSM_TX_L0S_ENTR
>Y);
>+
> CDNS_PCIE_LGA_LTSSM_NAME(CDNS_PCIE_LGA_LTSSM_TX_L0S_IDLE)
>;
>+ CDNS_PCIE_LGA_LTSSM_NAME(CDNS_PCIE_LGA_LTSSM_TX_L0S_FTS);
>+ CDNS_PCIE_LGA_LTSSM_NAME(CDNS_PCIE_LGA_LTSSM_L1_ENTRY);
>+ CDNS_PCIE_LGA_LTSSM_NAME(CDNS_PCIE_LGA_LTSSM_L1_IDLE);
>+ CDNS_PCIE_LGA_LTSSM_NAME(CDNS_PCIE_LGA_LTSSM_L2_IDLE);
>+
> CDNS_PCIE_LGA_LTSSM_NAME(CDNS_PCIE_LGA_LTSSM_L2_TRANSMI
>TWAKE);
>+ CDNS_PCIE_LGA_LTSSM_NAME(CDNS_PCIE_LGA_LTSSM_DISABLED);
>+
> CDNS_PCIE_LGA_LTSSM_NAME(CDNS_PCIE_LGA_LTSSM_LOOPBACK_E
>NTRY_MASTER);
>+
> CDNS_PCIE_LGA_LTSSM_NAME(CDNS_PCIE_LGA_LTSSM_LOOPBACK_A
>CTIVE_MASTER);
>+
> CDNS_PCIE_LGA_LTSSM_NAME(CDNS_PCIE_LGA_LTSSM_LOOPBACK_E
>XIT_MASTER);
>+
> CDNS_PCIE_LGA_LTSSM_NAME(CDNS_PCIE_LGA_LTSSM_LOOPBACK_E
>NTRY_SLAVE);
>+
> CDNS_PCIE_LGA_LTSSM_NAME(CDNS_PCIE_LGA_LTSSM_LOOPBACK_A
>CTIVE_SLAVE);
>+
> CDNS_PCIE_LGA_LTSSM_NAME(CDNS_PCIE_LGA_LTSSM_LOOPBACK_E
>XIT_SLAVE);
>+ CDNS_PCIE_LGA_LTSSM_NAME(CDNS_PCIE_LGA_LTSSM_HOT_RESET);
>+
> CDNS_PCIE_LGA_LTSSM_NAME(CDNS_PCIE_LGA_LTSSM_RECOVERY_E
>QUALIZATION_PHASE_0);
>+
> CDNS_PCIE_LGA_LTSSM_NAME(CDNS_PCIE_LGA_LTSSM_RECOVERY_E
>QUALIZATION_PHASE_1);
>+
> CDNS_PCIE_LGA_LTSSM_NAME(CDNS_PCIE_LGA_LTSSM_RECOVERY_E
>QUALIZATION_PHASE_2);
>+
> CDNS_PCIE_LGA_LTSSM_NAME(CDNS_PCIE_LGA_LTSSM_RECOVERY_E
>QUALIZATION_PHASE_3);
>+ default:
>+ str = "CDNS_PCIE_LGA_LTSSM_UNKNOWN";
>+ break;
>+ }
>+
>+ return str + strlen("CDNS_PCIE_LGA_LTSSM_");
>+}
>+
> static const char *cdns_pcie_hpa_ltssm_status_string(enum
>cdns_pcie_hpa_ltssm ltssm)
> {
> const char *str;
>@@ -158,6 +210,7 @@ static const char
>*cdns_pcie_hpa_ltssm_status_string(enum cdns_pcie_hpa_ltssm lt
> static int ltssm_status_show(struct seq_file *s, void *v)
> {
> struct cdns_pcie *pci = s->private;
>+ enum cdns_pcie_lga_ltssm lga_ltssm;
> enum cdns_pcie_hpa_ltssm hpa_ltssm;
> const char *str_ltssm;
> u32 val;
>@@ -168,11 +221,13 @@ static int ltssm_status_show(struct seq_file *s, void
>*v)
> hpa_ltssm =
>FIELD_GET(CDNS_PCIE_HPA_LTSSM_STATUS_MASK, val);
> str_ltssm = cdns_pcie_hpa_ltssm_status_string(hpa_ltssm);
> } else {
>- /* TODO: LGA IP*/
>- return 0;
>+ val = cdns_pcie_readl(pci, CDNS_PCIE_LM_BASE);
>+ lga_ltssm =
>FIELD_GET(CDNS_PCIE_LGA_LTSSM_STATUS_MASK, val);
>+ str_ltssm = cdns_pcie_lga_ltssm_status_string(lga_ltssm);
> }
>
>- seq_printf(s, "%s (0x%02x)\n", str_ltssm, hpa_ltssm);
>+ seq_printf(s, "%s (0x%02x)\n", str_ltssm,
>+ pci->is_hpa ? hpa_ltssm : lga_ltssm);
>
> return 0;
> }
>diff --git a/drivers/pci/controller/cadence/pcie-cadence-ep.c
>b/drivers/pci/controller/cadence/pcie-cadence-ep.c
>index c0e1194a936b..370b19f4d38f 100644
>--- a/drivers/pci/controller/cadence/pcie-cadence-ep.c
>+++ b/drivers/pci/controller/cadence/pcie-cadence-ep.c
>@@ -655,6 +655,7 @@ void cdns_pcie_ep_disable(struct cdns_pcie_ep *ep)
> struct device *dev = ep->pcie.dev;
> struct pci_epc *epc = to_pci_epc(dev);
>
>+ cdns_pcie_debugfs_deinit(&ep->pcie);
> pci_epc_deinit_notify(epc);
> pci_epc_mem_free_addr(epc, ep->irq_phys_addr, ep->irq_cpu_addr,
> SZ_128K);
>@@ -761,6 +762,8 @@ int cdns_pcie_ep_setup(struct cdns_pcie_ep *ep)
>
> pci_epc_init_notify(epc);
>
>+ cdns_pcie_debugfs_init(pcie);
>+
> return 0;
>
> free_epc_mem:
>diff --git a/drivers/pci/controller/cadence/pcie-cadence-host.c
>b/drivers/pci/controller/cadence/pcie-cadence-host.c
>index 0bc9e6e90e0e..8105bb625eb7 100644
>--- a/drivers/pci/controller/cadence/pcie-cadence-host.c
>+++ b/drivers/pci/controller/cadence/pcie-cadence-host.c
>@@ -364,6 +364,7 @@ void cdns_pcie_host_disable(struct cdns_pcie_rc *rc)
> {
> struct pci_host_bridge *bridge;
>
>+ cdns_pcie_debugfs_deinit(&rc->pcie);
> bridge = pci_host_bridge_from_priv(rc);
> pci_stop_root_bus(bridge->bus);
> pci_remove_root_bus(bridge->bus);
>@@ -423,7 +424,13 @@ int cdns_pcie_host_setup(struct cdns_pcie_rc *rc)
> if (!bridge->ops)
> bridge->ops = &cdns_pcie_host_ops;
>
>- return pci_host_probe(bridge);
>+ ret = pci_host_probe(bridge);
>+ if (ret)
>+ return ret;
>+
>+ cdns_pcie_debugfs_init(pcie);
>+
>+ return 0;
> }
> EXPORT_SYMBOL_GPL(cdns_pcie_host_setup);
>
>diff --git a/drivers/pci/controller/cadence/pcie-cadence.h
>b/drivers/pci/controller/cadence/pcie-cadence.h
>index 2320319af83b..8bc6564c65b9 100644
>--- a/drivers/pci/controller/cadence/pcie-cadence.h
>+++ b/drivers/pci/controller/cadence/pcie-cadence.h
>@@ -14,6 +14,7 @@
> #include "pcie-cadence-lga-regs.h"
> #include "pcie-cadence-hpa-regs.h"
>
>+#define CDNS_PCIE_LGA_LTSSM_STATUS_MASK GENMASK(29, 24)
> #define CDNS_PCIE_HPA_LTSSM_STATUS_MASK GENMASK(27, 20)
>
> enum cdns_pcie_rp_bar {
>@@ -44,6 +45,48 @@ enum cdns_pcie_reg_bank {
> REG_BANKS_MAX,
> };
>
>+enum cdns_pcie_lga_ltssm {
>+ CDNS_PCIE_LGA_LTSSM_DETECT_QUIET = 0x00,
>+ CDNS_PCIE_LGA_LTSSM_DETECT_ACTIVE = 0x01,
>+ CDNS_PCIE_LGA_LTSSM_POLLING_ACTIVE = 0x02,
>+ CDNS_PCIE_LGA_LTSSM_POLLING_COMPLIANCE
> = 0x03,
>+ CDNS_PCIE_LGA_LTSSM_POLLING_CONFIGURATION = 0x04,
>+ CDNS_PCIE_LGA_LTSSM_CONFIGURATION_LINKWIDTH_START = 0x05,
>+ CDNS_PCIE_LGA_LTSSM_CONFIGURATION_LINKWIDTH_ACCEPT
> = 0x06,
>+ CDNS_PCIE_LGA_LTSSM_CONFIGURATION_LANENUM_ACCEPT = 0x07,
>+ CDNS_PCIE_LGA_LTSSM_CONFIGURATION_LANENUM_WAIT
> = 0x08,
>+ CDNS_PCIE_LGA_LTSSM_CONFIGURATION_COMPLETE = 0x09,
>+ CDNS_PCIE_LGA_LTSSM_CONFIGURATION_IDLE
> = 0x0A,
>+ CDNS_PCIE_LGA_LTSSM_RECOVERY_RCVRLOCK = 0x0B,
>+ CDNS_PCIE_LGA_LTSSM_RECOVERY_SPEED = 0x0C,
>+ CDNS_PCIE_LGA_LTSSM_RECOVERY_RCVRCFG = 0x0D,
>+ CDNS_PCIE_LGA_LTSSM_RECOVERY_IDLE = 0x0E,
>+ CDNS_PCIE_LGA_LTSSM_L0 = 0x10,
>+ CDNS_PCIE_LGA_LTSSM_RX_L0S_ENTRY = 0x11,
>+ CDNS_PCIE_LGA_LTSSM_RX_L0S_IDLE = 0x12,
>+ CDNS_PCIE_LGA_LTSSM_RX_L0S_FTS = 0x13,
>+ CDNS_PCIE_LGA_LTSSM_TX_L0S_ENTRY = 0x14,
>+ CDNS_PCIE_LGA_LTSSM_TX_L0S_IDLE = 0x15,
>+ CDNS_PCIE_LGA_LTSSM_TX_L0S_FTS = 0x16,
>+ CDNS_PCIE_LGA_LTSSM_L1_ENTRY = 0x17,
>+ CDNS_PCIE_LGA_LTSSM_L1_IDLE = 0x18,
>+ CDNS_PCIE_LGA_LTSSM_L2_IDLE = 0x19,
>+ CDNS_PCIE_LGA_LTSSM_L2_TRANSMITWAKE = 0x1A,
>+ CDNS_PCIE_LGA_LTSSM_DISABLED = 0x20,
>+ CDNS_PCIE_LGA_LTSSM_LOOPBACK_ENTRY_MASTER = 0x21,
>+ CDNS_PCIE_LGA_LTSSM_LOOPBACK_ACTIVE_MASTER = 0x22,
>+ CDNS_PCIE_LGA_LTSSM_LOOPBACK_EXIT_MASTER = 0x23,
>+ CDNS_PCIE_LGA_LTSSM_LOOPBACK_ENTRY_SLAVE = 0x24,
>+ CDNS_PCIE_LGA_LTSSM_LOOPBACK_ACTIVE_SLAVE = 0x25,
>+ CDNS_PCIE_LGA_LTSSM_LOOPBACK_EXIT_SLAVE
> = 0x26,
>+ CDNS_PCIE_LGA_LTSSM_HOT_RESET = 0x27,
>+ CDNS_PCIE_LGA_LTSSM_RECOVERY_EQUALIZATION_PHASE_0 = 0x28,
>+ CDNS_PCIE_LGA_LTSSM_RECOVERY_EQUALIZATION_PHASE_1 = 0x29,
>+ CDNS_PCIE_LGA_LTSSM_RECOVERY_EQUALIZATION_PHASE_2 = 0x2A,
>+ CDNS_PCIE_LGA_LTSSM_RECOVERY_EQUALIZATION_PHASE_3 = 0x2B,
>+ CDNS_PCIE_LGA_LTSSM_UNKNOWN =
>0xFFFFFFFF,
>+};
>+
> enum cdns_pcie_hpa_ltssm {
> CDNS_PCIE_HPA_LTSSM_DETECT_QUIET = 0,
> CDNS_PCIE_HPA_LTSSM_DETECT_QUIET_ENTRY = 1,
>--
>2.43.0
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH v6 3/3] PCI: cadence: Add LGA IP debugfs for LTSSM status
2026-05-20 2:34 ` Manikandan Karunakaran Pillai
@ 2026-05-20 2:59 ` Hans Zhang
2026-05-20 4:36 ` Aksh Garg
0 siblings, 1 reply; 13+ messages in thread
From: Hans Zhang @ 2026-05-20 2:59 UTC (permalink / raw)
To: Manikandan Karunakaran Pillai, bhelgaas@google.com,
lpieralisi@kernel.org, kwilczynski@kernel.org, mani@kernel.org
Cc: robh@kernel.org, a-garg7@ti.com, s-vadapalli@ti.com,
linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org
On 5/20/26 10:34, Manikandan Karunakaran Pillai wrote:
>> EXTERNAL MAIL
>>
>>
>> Extend debugfs support to LGA-based Cadence PCIe controllers. The
>> 'ltssm_status' file now works for both HPA and LGA IP by selecting the
>> appropriate register access based on the 'is_hpa' flag.
>>
>> Signed-off-by: Hans Zhang <18255117159@163.com>
>> ---
>> .../controller/cadence/pcie-cadence-debugfs.c | 61 ++++++++++++++++++-
>> .../pci/controller/cadence/pcie-cadence-ep.c | 3 +
>> .../controller/cadence/pcie-cadence-host.c | 9 ++-
>> drivers/pci/controller/cadence/pcie-cadence.h | 43 +++++++++++++
>> 4 files changed, 112 insertions(+), 4 deletions(-)
>>
>> diff --git a/drivers/pci/controller/cadence/pcie-cadence-debugfs.c
>> b/drivers/pci/controller/cadence/pcie-cadence-debugfs.c
>> index 97c5deef2b1a..0a308f95e9f6 100644
>> --- a/drivers/pci/controller/cadence/pcie-cadence-debugfs.c
>> +++ b/drivers/pci/controller/cadence/pcie-cadence-debugfs.c
>> @@ -13,6 +13,58 @@
>>
>> #define CDNS_DEBUGFS_BUF_MAX 128
>
> Where is CDNS_DEBUGFS_BUF_MAX used for ?
Hi Manikandan,
Thank you very much for your reply and reminder.
This macro definition was used in patch 0002. Since I compiled the code
after applying all three patches together, I didn't notice this issue.
The next version will be fixed and will be included in patch 0002.
Best regards,
Hans
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH v6 3/3] PCI: cadence: Add LGA IP debugfs for LTSSM status
2026-05-20 2:59 ` Hans Zhang
@ 2026-05-20 4:36 ` Aksh Garg
2026-05-20 4:40 ` Hans Zhang
0 siblings, 1 reply; 13+ messages in thread
From: Aksh Garg @ 2026-05-20 4:36 UTC (permalink / raw)
To: Hans Zhang, Manikandan Karunakaran Pillai, bhelgaas@google.com,
lpieralisi@kernel.org, kwilczynski@kernel.org, mani@kernel.org
Cc: robh@kernel.org, s-vadapalli@ti.com, linux-pci@vger.kernel.org,
linux-kernel@vger.kernel.org
On 20/05/26 08:29, Hans Zhang wrote:
>
>
> On 5/20/26 10:34, Manikandan Karunakaran Pillai wrote:
>>> EXTERNAL MAIL
>>>
>>>
>>> Extend debugfs support to LGA-based Cadence PCIe controllers. The
>>> 'ltssm_status' file now works for both HPA and LGA IP by selecting the
>>> appropriate register access based on the 'is_hpa' flag.
>>>
>>> Signed-off-by: Hans Zhang <18255117159@163.com>
>>> ---
>>> .../controller/cadence/pcie-cadence-debugfs.c | 61 ++++++++++++++++++-
>>> .../pci/controller/cadence/pcie-cadence-ep.c | 3 +
>>> .../controller/cadence/pcie-cadence-host.c | 9 ++-
>>> drivers/pci/controller/cadence/pcie-cadence.h | 43 +++++++++++++
>>> 4 files changed, 112 insertions(+), 4 deletions(-)
>>>
>>> diff --git a/drivers/pci/controller/cadence/pcie-cadence-debugfs.c
>>> b/drivers/pci/controller/cadence/pcie-cadence-debugfs.c
>>> index 97c5deef2b1a..0a308f95e9f6 100644
>>> --- a/drivers/pci/controller/cadence/pcie-cadence-debugfs.c
>>> +++ b/drivers/pci/controller/cadence/pcie-cadence-debugfs.c
>>> @@ -13,6 +13,58 @@
>>>
>>> #define CDNS_DEBUGFS_BUF_MAX 128
>>
>> Where is CDNS_DEBUGFS_BUF_MAX used for ?
>
> Hi Manikandan,
>
> Thank you very much for your reply and reminder.
>
> This macro definition was used in patch 0002. Since I compiled the code
> after applying all three patches together, I didn't notice this issue.
> The next version will be fixed and will be included in patch 0002.
I didn't understood the issue here. The macro definition was indeed
introduced in patch 0002 itself right? Am I missing something here?
>
> Best regards,
> Hans
>
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH v6 3/3] PCI: cadence: Add LGA IP debugfs for LTSSM status
2026-05-20 4:36 ` Aksh Garg
@ 2026-05-20 4:40 ` Hans Zhang
2026-05-20 5:27 ` Aksh Garg
0 siblings, 1 reply; 13+ messages in thread
From: Hans Zhang @ 2026-05-20 4:40 UTC (permalink / raw)
To: Aksh Garg, Manikandan Karunakaran Pillai, bhelgaas@google.com,
lpieralisi@kernel.org, kwilczynski@kernel.org, mani@kernel.org
Cc: robh@kernel.org, s-vadapalli@ti.com, linux-pci@vger.kernel.org,
linux-kernel@vger.kernel.org
On 5/20/26 12:36, Aksh Garg wrote:
>
>
> On 20/05/26 08:29, Hans Zhang wrote:
>>
>>
>> On 5/20/26 10:34, Manikandan Karunakaran Pillai wrote:
>>>> EXTERNAL MAIL
>>>>
>>>>
>>>> Extend debugfs support to LGA-based Cadence PCIe controllers. The
>>>> 'ltssm_status' file now works for both HPA and LGA IP by selecting the
>>>> appropriate register access based on the 'is_hpa' flag.
>>>>
>>>> Signed-off-by: Hans Zhang <18255117159@163.com>
>>>> ---
>>>> .../controller/cadence/pcie-cadence-debugfs.c | 61 ++++++++++++++++++-
>>>> .../pci/controller/cadence/pcie-cadence-ep.c | 3 +
>>>> .../controller/cadence/pcie-cadence-host.c | 9 ++-
>>>> drivers/pci/controller/cadence/pcie-cadence.h | 43 +++++++++++++
>>>> 4 files changed, 112 insertions(+), 4 deletions(-)
>>>>
>>>> diff --git a/drivers/pci/controller/cadence/pcie-cadence-debugfs.c
>>>> b/drivers/pci/controller/cadence/pcie-cadence-debugfs.c
>>>> index 97c5deef2b1a..0a308f95e9f6 100644
>>>> --- a/drivers/pci/controller/cadence/pcie-cadence-debugfs.c
>>>> +++ b/drivers/pci/controller/cadence/pcie-cadence-debugfs.c
>>>> @@ -13,6 +13,58 @@
>>>>
>>>> #define CDNS_DEBUGFS_BUF_MAX 128
>>>
>>> Where is CDNS_DEBUGFS_BUF_MAX used for ?
>>
>> Hi Manikandan,
>>
>> Thank you very much for your reply and reminder.
>>
>> This macro definition was used in patch 0002. Since I compiled the
>> code after applying all three patches together, I didn't notice this
>> issue. The next version will be fixed and will be included in patch 0002.
>
> I didn't understood the issue here. The macro definition was indeed
> introduced in patch 0002 itself right? Am I missing something here?
Hi Aksh,
If only patches 0001 and 0002 are applied, there will be a compilation
error. Patch 0002 will fail to find CDNS_DEBUGFS_BUF_MAX. Previously, I
split LGA into patch 0003. I didn't notice this issue. Do you think I
have explained it clearly?
Best regards,
Hans
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH v6 3/3] PCI: cadence: Add LGA IP debugfs for LTSSM status
2026-05-20 4:40 ` Hans Zhang
@ 2026-05-20 5:27 ` Aksh Garg
2026-05-20 5:44 ` Hans Zhang
0 siblings, 1 reply; 13+ messages in thread
From: Aksh Garg @ 2026-05-20 5:27 UTC (permalink / raw)
To: Hans Zhang, Manikandan Karunakaran Pillai, bhelgaas@google.com,
lpieralisi@kernel.org, kwilczynski@kernel.org, mani@kernel.org
Cc: robh@kernel.org, s-vadapalli@ti.com, linux-pci@vger.kernel.org,
linux-kernel@vger.kernel.org
On 20/05/26 10:10, Hans Zhang wrote:
>
>
> On 5/20/26 12:36, Aksh Garg wrote:
>>
>>
>> On 20/05/26 08:29, Hans Zhang wrote:
>>>
>>>
>>> On 5/20/26 10:34, Manikandan Karunakaran Pillai wrote:
>>>>> EXTERNAL MAIL
>>>>>
>>>>>
>>>>> Extend debugfs support to LGA-based Cadence PCIe controllers. The
>>>>> 'ltssm_status' file now works for both HPA and LGA IP by selecting the
>>>>> appropriate register access based on the 'is_hpa' flag.
>>>>>
>>>>> Signed-off-by: Hans Zhang <18255117159@163.com>
>>>>> ---
>>>>> .../controller/cadence/pcie-cadence-debugfs.c | 61 ++++++++++++++++++-
>>>>> .../pci/controller/cadence/pcie-cadence-ep.c | 3 +
>>>>> .../controller/cadence/pcie-cadence-host.c | 9 ++-
>>>>> drivers/pci/controller/cadence/pcie-cadence.h | 43 +++++++++++++
>>>>> 4 files changed, 112 insertions(+), 4 deletions(-)
>>>>>
>>>>> diff --git a/drivers/pci/controller/cadence/pcie-cadence-debugfs.c
>>>>> b/drivers/pci/controller/cadence/pcie-cadence-debugfs.c
>>>>> index 97c5deef2b1a..0a308f95e9f6 100644
>>>>> --- a/drivers/pci/controller/cadence/pcie-cadence-debugfs.c
>>>>> +++ b/drivers/pci/controller/cadence/pcie-cadence-debugfs.c
>>>>> @@ -13,6 +13,58 @@
>>>>>
>>>>> #define CDNS_DEBUGFS_BUF_MAX 128
>>>>
>>>> Where is CDNS_DEBUGFS_BUF_MAX used for ?
>>>
>>> Hi Manikandan,
>>>
>>> Thank you very much for your reply and reminder.
>>>
>>> This macro definition was used in patch 0002. Since I compiled the
>>> code after applying all three patches together, I didn't notice this
>>> issue. The next version will be fixed and will be included in patch
>>> 0002.
>>
>> I didn't understood the issue here. The macro definition was indeed
>> introduced in patch 0002 itself right? Am I missing something here?
>
> Hi Aksh,
>
> If only patches 0001 and 0002 are applied, there will be a compilation
> error. Patch 0002 will fail to find CDNS_DEBUGFS_BUF_MAX. Previously, I
> split LGA into patch 0003. I didn't notice this issue. Do you think I
> have explained it clearly?
I see no compilation errors after applying only patch 1 and 2.
CDNS_DEBUGFS_BUF_MAX macro is defined in the patch 2 itself.
Patch 3 just uses the CDNS_DEBUGFS_BUF_MAX macro definition code for the
reference point to add the new code lines in that patch, it didn't
introduced the macro here.
>
> Best regards,
> Hans
>
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH v6 3/3] PCI: cadence: Add LGA IP debugfs for LTSSM status
2026-05-20 5:27 ` Aksh Garg
@ 2026-05-20 5:44 ` Hans Zhang
0 siblings, 0 replies; 13+ messages in thread
From: Hans Zhang @ 2026-05-20 5:44 UTC (permalink / raw)
To: Aksh Garg, Manikandan Karunakaran Pillai, bhelgaas@google.com,
lpieralisi@kernel.org, kwilczynski@kernel.org, mani@kernel.org
Cc: robh@kernel.org, s-vadapalli@ti.com, linux-pci@vger.kernel.org,
linux-kernel@vger.kernel.org
On 5/20/26 13:27, Aksh Garg wrote:
>
>
> On 20/05/26 10:10, Hans Zhang wrote:
>>
>>
>> On 5/20/26 12:36, Aksh Garg wrote:
>>>
>>>
>>> On 20/05/26 08:29, Hans Zhang wrote:
>>>>
>>>>
>>>> On 5/20/26 10:34, Manikandan Karunakaran Pillai wrote:
>>>>>> EXTERNAL MAIL
>>>>>>
>>>>>>
>>>>>> Extend debugfs support to LGA-based Cadence PCIe controllers. The
>>>>>> 'ltssm_status' file now works for both HPA and LGA IP by selecting
>>>>>> the
>>>>>> appropriate register access based on the 'is_hpa' flag.
>>>>>>
>>>>>> Signed-off-by: Hans Zhang <18255117159@163.com>
>>>>>> ---
>>>>>> .../controller/cadence/pcie-cadence-debugfs.c | 61 +++++++++++++++
>>>>>> +++-
>>>>>> .../pci/controller/cadence/pcie-cadence-ep.c | 3 +
>>>>>> .../controller/cadence/pcie-cadence-host.c | 9 ++-
>>>>>> drivers/pci/controller/cadence/pcie-cadence.h | 43 +++++++++++++
>>>>>> 4 files changed, 112 insertions(+), 4 deletions(-)
>>>>>>
>>>>>> diff --git a/drivers/pci/controller/cadence/pcie-cadence-debugfs.c
>>>>>> b/drivers/pci/controller/cadence/pcie-cadence-debugfs.c
>>>>>> index 97c5deef2b1a..0a308f95e9f6 100644
>>>>>> --- a/drivers/pci/controller/cadence/pcie-cadence-debugfs.c
>>>>>> +++ b/drivers/pci/controller/cadence/pcie-cadence-debugfs.c
>>>>>> @@ -13,6 +13,58 @@
>>>>>>
>>>>>> #define CDNS_DEBUGFS_BUF_MAX 128
>>>>>
>>>>> Where is CDNS_DEBUGFS_BUF_MAX used for ?
>>>>
>>>> Hi Manikandan,
>>>>
>>>> Thank you very much for your reply and reminder.
>>>>
>>>> This macro definition was used in patch 0002. Since I compiled the
>>>> code after applying all three patches together, I didn't notice this
>>>> issue. The next version will be fixed and will be included in patch
>>>> 0002.
>>>
>>> I didn't understood the issue here. The macro definition was indeed
>>> introduced in patch 0002 itself right? Am I missing something here?
>>
>> Hi Aksh,
>>
>> If only patches 0001 and 0002 are applied, there will be a compilation
>> error. Patch 0002 will fail to find CDNS_DEBUGFS_BUF_MAX. Previously,
>> I split LGA into patch 0003. I didn't notice this issue. Do you think
>> I have explained it clearly?
>
> I see no compilation errors after applying only patch 1 and 2.
> CDNS_DEBUGFS_BUF_MAX macro is defined in the patch 2 itself.
>
> Patch 3 just uses the CDNS_DEBUGFS_BUF_MAX macro definition code for the
> reference point to add the new code lines in that patch, it didn't
> introduced the macro here.
Hi Aksh,
Well, I was misled. Could you please help test this series of patches?
If there are no issues, please add your test label.
Best regards,
Hans
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH v6 2/3] PCI: cadence: Add HPA IP debugfs for LTSSM status
2026-05-19 12:36 ` [PATCH v6 2/3] PCI: cadence: Add HPA IP debugfs for LTSSM status Hans Zhang
2026-05-19 13:20 ` sashiko-bot
@ 2026-05-20 7:26 ` Aksh Garg
2026-05-20 14:54 ` Hans Zhang
1 sibling, 1 reply; 13+ messages in thread
From: Aksh Garg @ 2026-05-20 7:26 UTC (permalink / raw)
To: Hans Zhang, bhelgaas, lpieralisi, kwilczynski, mani
Cc: robh, mpillai, s-vadapalli, linux-pci, linux-kernel
On 19/05/26 18:06, Hans Zhang wrote:
> Add debugfs support for HPA-based Cadence PCIe controllers. A new file
> 'ltssm_status' is created under debugfs, allowing users to read the
> current LTSSM state as a string and raw value.
>
> Signed-off-by: Hans Zhang <18255117159@163.com>
> ---
> Documentation/ABI/testing/debugfs-cdns-pcie | 5 +
> drivers/pci/controller/cadence/Kconfig | 9 +
> drivers/pci/controller/cadence/Makefile | 1 +
> drivers/pci/controller/cadence/pci-sky1.c | 4 +
> .../controller/cadence/pcie-cadence-debugfs.c | 208 ++++++++++++++++++
> .../cadence/pcie-cadence-host-hpa.c | 19 +-
> drivers/pci/controller/cadence/pcie-cadence.h | 153 +++++++++++++
> 7 files changed, 398 insertions(+), 1 deletion(-)
> create mode 100644 Documentation/ABI/testing/debugfs-cdns-pcie
> create mode 100644 drivers/pci/controller/cadence/pcie-cadence-debugfs.c
>
> diff --git a/Documentation/ABI/testing/debugfs-cdns-pcie b/Documentation/ABI/testing/debugfs-cdns-pcie
> new file mode 100644
> index 000000000000..c1104e28e4ee
> --- /dev/null
> +++ b/Documentation/ABI/testing/debugfs-cdns-pcie
> @@ -0,0 +1,5 @@
> +What: /sys/kernel/debug/cdns_pcie_<dev>/ltssm_status
> +Date: March 2026
> +Contact: Hans Zhang <18255117159@163.com>
> +Description: (RO) Read will return the current PCIe LTSSM state in both
> + string and raw value.
> \ No newline at end of file
> diff --git a/drivers/pci/controller/cadence/Kconfig b/drivers/pci/controller/cadence/Kconfig
> index 9e651d545973..cb010bc97aad 100644
> --- a/drivers/pci/controller/cadence/Kconfig
> +++ b/drivers/pci/controller/cadence/Kconfig
> @@ -6,6 +6,15 @@ menu "Cadence-based PCIe controllers"
> config PCIE_CADENCE
> tristate
>
> +config PCIE_CADENCE_DEBUGFS
> + tristate "Cadence PCIe debugfs entries"
> + depends on DEBUG_FS
> + depends on PCIE_CADENCE_HOST || PCIE_CADENCE_EP
> + help
> + Say Y here to enable debugfs entries for the PCIe controller. These
> + entries provide various debug features related to the controller and
> + the LTSSM status of link can be displayed.
> +
> config PCIE_CADENCE_HOST
> tristate
> depends on OF
Sashiko pointed the compilation issues when this is build as a module.
The linkage issue needs to be resolved if we want this as a module.
Also, if we build it as m, it would requires MODULE_LICENSE() and
MODULE_DESCRIPTION().
> diff --git a/drivers/pci/controller/cadence/Makefile b/drivers/pci/controller/cadence/Makefile
> index b8ec1cecfaa8..2cdc4617e0c2 100644
> --- a/drivers/pci/controller/cadence/Makefile
> +++ b/drivers/pci/controller/cadence/Makefile
> @@ -4,6 +4,7 @@ pcie-cadence-host-mod-y := pcie-cadence-host-common.o pcie-cadence-host.o pcie-c
> pcie-cadence-ep-mod-y := pcie-cadence-ep.o
>
> obj-$(CONFIG_PCIE_CADENCE) = pcie-cadence-mod.o
> +obj-$(CONFIG_PCIE_CADENCE_DEBUGFS) += pcie-cadence-debugfs.o
> obj-$(CONFIG_PCIE_CADENCE_HOST) += pcie-cadence-host-mod.o
> obj-$(CONFIG_PCIE_CADENCE_EP) += pcie-cadence-ep-mod.o
> obj-$(CONFIG_PCIE_CADENCE_PLAT) += pcie-cadence-plat.o
> diff --git a/drivers/pci/controller/cadence/pci-sky1.c b/drivers/pci/controller/cadence/pci-sky1.c
> index e1f4a98e2ab6..b8632f1d3156 100644
> --- a/drivers/pci/controller/cadence/pci-sky1.c
> +++ b/drivers/pci/controller/cadence/pci-sky1.c
> @@ -221,6 +221,10 @@ MODULE_DEVICE_TABLE(of, of_sky1_pcie_match);
[ ... ]
> /**
> @@ -447,6 +583,7 @@ void cdns_pcie_host_disable(struct cdns_pcie_rc *rc);
> void __iomem *cdns_pci_map_bus(struct pci_bus *bus, unsigned int devfn,
> int where);
> int cdns_pcie_hpa_host_setup(struct cdns_pcie_rc *rc);
> +void cdns_pcie_hpa_host_disable(struct cdns_pcie_rc *rc);
> #else
> static inline int cdns_pcie_host_link_setup(struct cdns_pcie_rc *rc)
> {
> @@ -472,6 +609,10 @@ static inline void cdns_pcie_host_disable(struct cdns_pcie_rc *rc)
> {
> }
>
> +static inline void cdns_pcie_hpa_host_disable(struct cdns_pcie_rc *rc)
> +{
> +}
> +
> static inline void __iomem *cdns_pci_map_bus(struct pci_bus *bus, unsigned int devfn,
> int where)
> {
> @@ -535,4 +676,16 @@ bool cdns_pcie_hpa_link_up(struct cdns_pcie *pcie);
>
> extern const struct dev_pm_ops cdns_pcie_pm_ops;
>
> +#ifdef CONFIG_PCIE_CADENCE_DEBUGFS
Use "#if IS_ENABLED(CONFIG_PCIE_CADENCE_DEBUGFS)" to resolve the
compilation error when building as a module.
> +void cdns_pcie_debugfs_deinit(struct cdns_pcie *pci);
> +void cdns_pcie_debugfs_init(struct cdns_pcie *pci);
> +#else
> +static inline void cdns_pcie_debugfs_deinit(struct cdns_pcie *pci)
> +{
> +}
> +static inline void cdns_pcie_debugfs_init(struct cdns_pcie *pci)
> +{
> +}
> +#endif
> +
> #endif /* _PCIE_CADENCE_H */
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH v6 2/3] PCI: cadence: Add HPA IP debugfs for LTSSM status
2026-05-20 7:26 ` Aksh Garg
@ 2026-05-20 14:54 ` Hans Zhang
0 siblings, 0 replies; 13+ messages in thread
From: Hans Zhang @ 2026-05-20 14:54 UTC (permalink / raw)
To: Aksh Garg, bhelgaas, lpieralisi, kwilczynski, mani
Cc: robh, mpillai, s-vadapalli, linux-pci, linux-kernel
On 5/20/26 15:26, Aksh Garg wrote:
>
>
> On 19/05/26 18:06, Hans Zhang wrote:
>> Add debugfs support for HPA-based Cadence PCIe controllers. A new file
>> 'ltssm_status' is created under debugfs, allowing users to read the
>> current LTSSM state as a string and raw value.
>>
>> Signed-off-by: Hans Zhang <18255117159@163.com>
>> ---
>> Documentation/ABI/testing/debugfs-cdns-pcie | 5 +
>> drivers/pci/controller/cadence/Kconfig | 9 +
>> drivers/pci/controller/cadence/Makefile | 1 +
>> drivers/pci/controller/cadence/pci-sky1.c | 4 +
>> .../controller/cadence/pcie-cadence-debugfs.c | 208 ++++++++++++++++++
>> .../cadence/pcie-cadence-host-hpa.c | 19 +-
>> drivers/pci/controller/cadence/pcie-cadence.h | 153 +++++++++++++
>> 7 files changed, 398 insertions(+), 1 deletion(-)
>> create mode 100644 Documentation/ABI/testing/debugfs-cdns-pcie
>> create mode 100644 drivers/pci/controller/cadence/pcie-cadence-
>> debugfs.c
>>
>> diff --git a/Documentation/ABI/testing/debugfs-cdns-pcie b/
>> Documentation/ABI/testing/debugfs-cdns-pcie
>> new file mode 100644
>> index 000000000000..c1104e28e4ee
>> --- /dev/null
>> +++ b/Documentation/ABI/testing/debugfs-cdns-pcie
>> @@ -0,0 +1,5 @@
>> +What: /sys/kernel/debug/cdns_pcie_<dev>/ltssm_status
>> +Date: March 2026
>> +Contact: Hans Zhang <18255117159@163.com>
>> +Description: (RO) Read will return the current PCIe LTSSM state in
>> both
>> + string and raw value.
>> \ No newline at end of file
>> diff --git a/drivers/pci/controller/cadence/Kconfig b/drivers/pci/
>> controller/cadence/Kconfig
>> index 9e651d545973..cb010bc97aad 100644
>> --- a/drivers/pci/controller/cadence/Kconfig
>> +++ b/drivers/pci/controller/cadence/Kconfig
>> @@ -6,6 +6,15 @@ menu "Cadence-based PCIe controllers"
>> config PCIE_CADENCE
>> tristate
>> +config PCIE_CADENCE_DEBUGFS
>> + tristate "Cadence PCIe debugfs entries"
>> + depends on DEBUG_FS
>> + depends on PCIE_CADENCE_HOST || PCIE_CADENCE_EP
>> + help
>> + Say Y here to enable debugfs entries for the PCIe controller.
>> These
>> + entries provide various debug features related to the
>> controller and
>> + the LTSSM status of link can be displayed.
>> +
>> config PCIE_CADENCE_HOST
>> tristate
>> depends on OF
>
> Sashiko pointed the compilation issues when this is build as a module.
> The linkage issue needs to be resolved if we want this as a module.
> Also, if we build it as m, it would requires MODULE_LICENSE() and
> MODULE_DESCRIPTION().
Hi Aksh,
Will add.
>
>> diff --git a/drivers/pci/controller/cadence/Makefile b/drivers/pci/
>> controller/cadence/Makefile
>> index b8ec1cecfaa8..2cdc4617e0c2 100644
>> --- a/drivers/pci/controller/cadence/Makefile
>> +++ b/drivers/pci/controller/cadence/Makefile
>> @@ -4,6 +4,7 @@ pcie-cadence-host-mod-y := pcie-cadence-host-common.o
>> pcie-cadence-host.o pcie-c
>> pcie-cadence-ep-mod-y := pcie-cadence-ep.o
>> obj-$(CONFIG_PCIE_CADENCE) = pcie-cadence-mod.o
>> +obj-$(CONFIG_PCIE_CADENCE_DEBUGFS) += pcie-cadence-debugfs.o
>> obj-$(CONFIG_PCIE_CADENCE_HOST) += pcie-cadence-host-mod.o
>> obj-$(CONFIG_PCIE_CADENCE_EP) += pcie-cadence-ep-mod.o
>> obj-$(CONFIG_PCIE_CADENCE_PLAT) += pcie-cadence-plat.o
>> diff --git a/drivers/pci/controller/cadence/pci-sky1.c b/drivers/pci/
>> controller/cadence/pci-sky1.c
>> index e1f4a98e2ab6..b8632f1d3156 100644
>> --- a/drivers/pci/controller/cadence/pci-sky1.c
>> +++ b/drivers/pci/controller/cadence/pci-sky1.c
>> @@ -221,6 +221,10 @@ MODULE_DEVICE_TABLE(of, of_sky1_pcie_match);
>
> [ ... ]
>
>> /**
>> @@ -447,6 +583,7 @@ void cdns_pcie_host_disable(struct cdns_pcie_rc *rc);
>> void __iomem *cdns_pci_map_bus(struct pci_bus *bus, unsigned int devfn,
>> int where);
>> int cdns_pcie_hpa_host_setup(struct cdns_pcie_rc *rc);
>> +void cdns_pcie_hpa_host_disable(struct cdns_pcie_rc *rc);
>> #else
>> static inline int cdns_pcie_host_link_setup(struct cdns_pcie_rc *rc)
>> {
>> @@ -472,6 +609,10 @@ static inline void cdns_pcie_host_disable(struct
>> cdns_pcie_rc *rc)
>> {
>> }
>> +static inline void cdns_pcie_hpa_host_disable(struct cdns_pcie_rc *rc)
>> +{
>> +}
>> +
>> static inline void __iomem *cdns_pci_map_bus(struct pci_bus *bus,
>> unsigned int devfn,
>> int where)
>> {
>> @@ -535,4 +676,16 @@ bool cdns_pcie_hpa_link_up(struct cdns_pcie *pcie);
>> extern const struct dev_pm_ops cdns_pcie_pm_ops;
>> +#ifdef CONFIG_PCIE_CADENCE_DEBUGFS
>
> Use "#if IS_ENABLED(CONFIG_PCIE_CADENCE_DEBUGFS)" to resolve the
> compilation error when building as a module.
>
Will change.
Best regards,
Hans
>> +void cdns_pcie_debugfs_deinit(struct cdns_pcie *pci);
>> +void cdns_pcie_debugfs_init(struct cdns_pcie *pci);
>> +#else
>> +static inline void cdns_pcie_debugfs_deinit(struct cdns_pcie *pci)
>> +{
>> +}
>> +static inline void cdns_pcie_debugfs_init(struct cdns_pcie *pci)
>> +{
>> +}
>> +#endif
>> +
>> #endif /* _PCIE_CADENCE_H */
^ permalink raw reply [flat|nested] 13+ messages in thread
end of thread, other threads:[~2026-05-20 14:55 UTC | newest]
Thread overview: 13+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2026-05-19 12:36 [PATCH v6 0/3] PCI: cadence: Add LTSSM debugfs Hans Zhang
2026-05-19 12:36 ` [PATCH v6 1/3] PCI: cadence: Add HPA architecture flag Hans Zhang
2026-05-19 12:36 ` [PATCH v6 2/3] PCI: cadence: Add HPA IP debugfs for LTSSM status Hans Zhang
2026-05-19 13:20 ` sashiko-bot
2026-05-20 7:26 ` Aksh Garg
2026-05-20 14:54 ` Hans Zhang
2026-05-19 12:36 ` [PATCH v6 3/3] PCI: cadence: Add LGA " Hans Zhang
2026-05-20 2:34 ` Manikandan Karunakaran Pillai
2026-05-20 2:59 ` Hans Zhang
2026-05-20 4:36 ` Aksh Garg
2026-05-20 4:40 ` Hans Zhang
2026-05-20 5:27 ` Aksh Garg
2026-05-20 5:44 ` Hans Zhang
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