From: sashiko-bot@kernel.org
To: "Krishna Chaitanya Chundru" <krishna.chundru@oss.qualcomm.com>
Cc: linux-pci@vger.kernel.org, robh@kernel.org,
devicetree@vger.kernel.org, conor+dt@kernel.org
Subject: Re: [PATCH v4 1/3] arm64: dts: qcom: eliza: Add PCIe PHY and controller nodes
Date: Tue, 28 Jul 2026 07:21:13 +0000 [thread overview]
Message-ID: <20260728072113.8FCBE1F000E9@smtp.kernel.org> (raw)
In-Reply-To: <20260728-eliza_evk-v4-1-decc7fe5246e@oss.qualcomm.com>
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] Missing `msi-map` property in the PCIe host controller nodes, completely breaking Message Signaled Interrupts (MSI/MSI-X).
--
--- Patch [1]: [PATCH v4 1/3] arm64: dts: qcom: eliza: Add PCIe PHY and controller nodes ---
commit 16f01d1efdef1f9640d6946e1dff4bcb10d4c047
Author: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
arm64: dts: qcom: eliza: Add PCIe PHY and controller nodes
This commit introduces PCIe controller and PHY nodes for the Eliza platform.
It also updates the GCC clock references to point to the newly added PHY
nodes instead of placeholder zeros.
> diff --git a/arch/arm64/boot/dts/qcom/eliza.dtsi b/arch/arm64/boot/dts/qcom/eliza.dtsi
> index 357e8066c1768..31835a5828834 100644
> --- a/arch/arm64/boot/dts/qcom/eliza.dtsi
> +++ b/arch/arm64/boot/dts/qcom/eliza.dtsi
[ ... ]
> @@ -1784,6 +1784,369 @@ mmss_noc: interconnect@1780000 {
[ ... ]
> + pcie0: pcie@1c00000 {
> + device_type = "pci";
[ ... ]
> + iommu-map = <0 &apps_smmu 0x1480 0x1>,
> + <0x100 &apps_smmu 0x1481 0x1>;
> +
> + interrupt-map = <0 0 0 1 &intc 0 0 0 564 IRQ_TYPE_LEVEL_HIGH>,
[Severity: High]
Is a msi-map property missing from this pcie0 node?
Without the msi-map property, the kernel's PCI OF core cannot establish an
MSI domain for the PCIe bus. Will this cause MSI/MSI-X interrupts to fail
for all connected PCIe endpoints, forcing them to fall back to legacy INTx
interrupts if supported?
[ ... ]
> + pcie1: pcie@1c08000 {
> + device_type = "pci";
[ ... ]
> + iommu-map = <0 &apps_smmu 0x1400 0x1>,
> + <0x100 &apps_smmu 0x1401 0x1>;
> +
> + interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>,
[Severity: High]
Is a msi-map property also missing from this pcie1 node?
Similar to pcie0, omitting this property might prevent modern devices like
NVMe drives that exclusively rely on MSIs from functioning correctly on
this controller.
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260728-eliza_evk-v4-0-decc7fe5246e@oss.qualcomm.com?part=1
next prev parent reply other threads:[~2026-07-28 7:21 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-07-28 7:06 [PATCH v4 0/3] arm64: dts: qcom: eliza-evk: Enable PCIe0 and PCIe1 with M.2 and TC9563 switch Krishna Chaitanya Chundru
2026-07-28 7:06 ` [PATCH v4 1/3] arm64: dts: qcom: eliza: Add PCIe PHY and controller nodes Krishna Chaitanya Chundru
2026-07-28 7:21 ` sashiko-bot [this message]
2026-07-28 7:06 ` [PATCH v4 2/3] arm64: dts: qcom: eliza-evk: Add PCIe0 with M.2 E key connector Krishna Chaitanya Chundru
2026-07-28 7:22 ` sashiko-bot
2026-07-28 7:06 ` [PATCH v4 3/3] arm64: dts: qcom: eliza-evk: Add PCIe1 with TC9563 PCIe switch Krishna Chaitanya Chundru
2026-07-28 7:21 ` sashiko-bot
2026-07-28 8:08 ` Konrad Dybcio
2026-07-28 8:08 ` Konrad Dybcio
2026-07-28 8:05 ` [PATCH v4 0/3] arm64: dts: qcom: eliza-evk: Enable PCIe0 and PCIe1 with M.2 and TC9563 switch Bartosz Golaszewski
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