Re: [PATCH v3 3/3] PCI: Put PCIe bridges with downstream devices into D3 at hibernate

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] Hibernation restore skips mandatory PCIe bridge link retraining delays due to snapshot state mismatch, leading to fatal PCIe errors when downstream devices are accessed.
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commit daecc28d1bb864ce78fb9c9df2c8ecd53a30fb12
Author: Mario Limonciello (AMD) <superm1@kernel.org>

PCI: Put PCIe bridges with downstream devices into D3 at hibernate

This commit aligns the hibernation path with the S3 suspend path by making
pci_pm_poweroff_noirq() use pci_pm_suspend_noirq_common(). This allows PCIe
bridges with downstream devices to enter low-power states like D3cold during
hibernation.

> diff --git a/drivers/pci/pci-driver.c b/drivers/pci/pci-driver.c
> index d15b3eb55ec53..a6fb731378d9c 100644
> --- a/drivers/pci/pci-driver.c
> +++ b/drivers/pci/pci-driver.c

[ ... ]

> @@ -1278,8 +1281,9 @@ static int pci_pm_poweroff_noirq(struct device *dev)
>  			return error;
>  	}
>  
> -	if (!pci_dev->state_saved && !pci_has_subordinate(pci_dev))
> -		pci_prepare_to_sleep(pci_dev);
> +	pci_pm_suspend_noirq_common(pci_dev, &skip_bus_pm);
> +	if (skip_bus_pm)
> +		goto Fixup;

[Severity: High]
Does this cause mandatory PCIe bridge link retraining delays to be skipped on
resume from hibernation?

During hibernation, pci_pm_freeze_noirq() sets the device state to PCI_UNKNOWN
via pci_pm_set_unknown_state() just before the memory snapshot is taken. The
snapshot therefore records the state as PCI_UNKNOWN.

Later in the hibernation process, pci_pm_suspend_noirq_common() powers the
bridge down to D3cold.

On system resume, the boot kernel loads the memory snapshot, reverting the
in-memory state back to PCI_UNKNOWN.

When pci_pm_restore_noirq() executes, it skips the bridge power up actions
because the restored state doesn't match PCI_D3cold:

    if (!skip_bus_pm && prev_state == PCI_D3cold)
        pci_pm_bridge_power_up_actions(pci_dev);

Can this state mismatch lead to downstream device accesses failing with fatal
PCIe errors on resume?

>  
>  	/*
>  	 * The reason for doing this here is the same as for the analogous code

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Sashiko AI review · https://sashiko.dev/#/patchset/20260831205533.2325747-1-mario.limonciello@amd.com?part=3